Unified Coverage Report :: Module :: prim_secded_inv_39_32_dec

Module : prim_secded_inv_39_32_dec

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_09_03/flash_ctrl-sim-vcs/default/sim-vcs/../src/lowrisc_prim_secded_0.1/rtl/prim_secded_inv_39_32_dec.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_eflash.gen_flash_cores[1].u_core.gen_prog_data.u_prog.u_data_intg_chk.u_data_chk	95.00			95.00
tb.dut.u_reg_core.u_chk.u_tlul_data_integ_dec.u_data_chk	100.00			100.00
tb.dut.u_flash_hw_if.u_data_intg_chk.u_data_chk	100.00			100.00
tb.dut.u_tl_adapter_eflash.gen_cmd_intg_check.u_cmd_intg_chk.u_tlul_data_integ_dec.u_data_chk	100.00			100.00
tb.dut.u_eflash.u_flash.gen_generic.u_impl_generic.u_reg_top.u_chk.u_tlul_data_integ_dec.u_data_chk	100.00			100.00
tb.dut.u_eflash.gen_flash_cores[0].u_core.gen_prog_data.u_prog.u_data_intg_chk.u_data_chk	100.00			100.00

---

Module Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.gen_prog_data.u_prog.u_data_intg_chk.u_data_chk

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
95.00			95.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
95.00			95.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00						u_data_intg_chk

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_reg_core.u_chk.u_tlul_data_integ_dec.u_data_chk

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00						u_tlul_data_integ_dec

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_flash_hw_if.u_data_intg_chk.u_data_chk

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00						u_data_intg_chk

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_tl_adapter_eflash.gen_cmd_intg_check.u_cmd_intg_chk.u_tlul_data_integ_dec.u_data_chk

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00						u_tlul_data_integ_dec

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_eflash.u_flash.gen_generic.u_impl_generic.u_reg_top.u_chk.u_tlul_data_integ_dec.u_data_chk

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00						u_tlul_data_integ_dec

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.gen_prog_data.u_prog.u_data_intg_chk.u_data_chk

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00						u_data_intg_chk

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Toggle Coverage for Module : prim_secded_inv_39_32_dec

	Total	Covered	Percent
Totals	4	4	100.00
Total Bits	160	160	100.00
Total Bits 0->1	80	80	100.00
Total Bits 1->0	80	80	100.00

Ports	4	4	100.00
Port Bits	160	160	100.00
Port Bits 0->1	80	80	100.00
Port Bits 1->0	80	80	100.00

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
data_i[38:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
data_o[31:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
syndrome_o[6:0]	Yes	Yes	T1,T3,T11	Yes	T1,T3,T11	OUTPUT
err_o[1:0]	Yes	Yes	T1,T3,T7	Yes	T1,T3,T7	OUTPUT

Toggle Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.gen_prog_data.u_prog.u_data_intg_chk.u_data_chk

	Total	Covered	Percent
Totals	4	2	50.00
Total Bits	160	152	95.00
Total Bits 0->1	80	76	95.00
Total Bits 1->0	80	76	95.00

Ports	4	2	50.00
Port Bits	160	152	95.00
Port Bits 0->1	80	76	95.00
Port Bits 1->0	80	76	95.00

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
data_i[38:0]	Yes	Yes	T2,T7,T11	Yes	T2,T7,T11	INPUT
data_o[31:0]	Yes	Yes	T2,T7,T11	Yes	T2,T7,T11	OUTPUT
syndrome_o[0]	No	No		No		OUTPUT
syndrome_o[1]	Yes	Yes	*T2,*T7,*T11	Yes	T2,T7,T11	OUTPUT
syndrome_o[2]	No	No		No		OUTPUT
syndrome_o[3]	Yes	Yes	*T2,*T7,*T11	Yes	T2,T7,T11	OUTPUT
syndrome_o[4]	No	No		No		OUTPUT
syndrome_o[6:5]	Yes	Yes	T2,T7,T11	Yes	T2,T7,T11	OUTPUT
err_o[0]	Yes	Yes	*T2,*T7,*T11	Yes	T2,T7,T11	OUTPUT
err_o[1]	No	No		No		OUTPUT

*Tests covering at least one bit in the range

Toggle Coverage for Instance : tb.dut.u_reg_core.u_chk.u_tlul_data_integ_dec.u_data_chk

	Total	Covered	Percent
Totals	4	4	100.00
Total Bits	160	160	100.00
Total Bits 0->1	80	80	100.00
Total Bits 1->0	80	80	100.00

Ports	4	4	100.00
Port Bits	160	160	100.00
Port Bits 0->1	80	80	100.00
Port Bits 1->0	80	80	100.00

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
data_i[38:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
data_o[31:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
syndrome_o[6:0]	Yes	Yes	T1,T3,T23	Yes	T1,T3,T23	OUTPUT
err_o[1:0]	Yes	Yes	T1,T3,T23	Yes	T1,T3,T23	OUTPUT

Toggle Coverage for Instance : tb.dut.u_flash_hw_if.u_data_intg_chk.u_data_chk

	Total	Covered	Percent
Totals	4	4	100.00
Total Bits	160	160	100.00
Total Bits 0->1	80	80	100.00
Total Bits 1->0	80	80	100.00

Ports	4	4	100.00
Port Bits	160	160	100.00
Port Bits 0->1	80	80	100.00
Port Bits 1->0	80	80	100.00

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
data_i[38:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
data_o[31:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
syndrome_o[6:0]	Yes	Yes	T63,T169,T278	Yes	T63,T169,T278	OUTPUT
err_o[1:0]	Yes	Yes	T279,T280,T281	Yes	T279,T280,T281	OUTPUT

Toggle Coverage for Instance : tb.dut.u_tl_adapter_eflash.gen_cmd_intg_check.u_cmd_intg_chk.u_tlul_data_integ_dec.u_data_chk

	Total	Covered	Percent
Totals	4	4	100.00
Total Bits	160	160	100.00
Total Bits 0->1	80	80	100.00
Total Bits 1->0	80	80	100.00

Ports	4	4	100.00
Port Bits	160	160	100.00
Port Bits 0->1	80	80	100.00
Port Bits 1->0	80	80	100.00

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
data_i[38:0]	Yes	Yes	T7,T13,T8	Yes	T7,T11,T13	INPUT
data_o[31:0]	Yes	Yes	T7,T13,T8	Yes	T7,T11,T13	OUTPUT
syndrome_o[6:0]	Yes	Yes	T11,T13,T8	Yes	T11,T13,T4	OUTPUT
err_o[1:0]	Yes	Yes	T3,T7,T11	Yes	T7,T13,T8	OUTPUT

Toggle Coverage for Instance : tb.dut.u_eflash.u_flash.gen_generic.u_impl_generic.u_reg_top.u_chk.u_tlul_data_integ_dec.u_data_chk

	Total	Covered	Percent
Totals	4	4	100.00
Total Bits	160	160	100.00
Total Bits 0->1	80	80	100.00
Total Bits 1->0	80	80	100.00

Ports	4	4	100.00
Port Bits	160	160	100.00
Port Bits 0->1	80	80	100.00
Port Bits 1->0	80	80	100.00

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
data_i[38:0]	Yes	Yes	T8,T55,T24	Yes	T8,T55,T19	INPUT
data_o[31:0]	Yes	Yes	T8,T55,T24	Yes	T8,T55,T19	OUTPUT
syndrome_o[6:0]	Yes	Yes	T8,T55,T24	Yes	T8,T55,T24	OUTPUT
err_o[1:0]	Yes	Yes	T8,T55,T111	Yes	T8,T55,T24	OUTPUT

Toggle Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.gen_prog_data.u_prog.u_data_intg_chk.u_data_chk

	Total	Covered	Percent
Totals	4	4	100.00
Total Bits	160	160	100.00
Total Bits 0->1	80	80	100.00
Total Bits 1->0	80	80	100.00

Ports	4	4	100.00
Port Bits	160	160	100.00
Port Bits 0->1	80	80	100.00
Port Bits 1->0	80	80	100.00

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
data_i[38:0]	Yes	Yes	T2,T7,T11	Yes	T2,T7,T11	INPUT
data_o[31:0]	Yes	Yes	T2,T7,T11	Yes	T2,T7,T11	OUTPUT
syndrome_o[6:0]	Yes	Yes	T121,T123,T184	Yes	T121,T123,T184	OUTPUT
err_o[1:0]	Yes	Yes	T2,T7,T11	Yes	T2,T7,T11	OUTPUT