Detail Report for Assertions

Assertions Uncovered:

ASSERTIONS	CATEGORY	SEVERITY	ATTEMPTS	REAL SUCCESSES	FAILURES	INCOMPLETE	SRC
tb.dut.FpvSecCmEflashReqFifoRptrCheck_A	0	0	398386977	0	0	0
tb.dut.FpvSecCmEflashReqFifoWptrCheck_A	0	0	398386977	0	0	0
tb.dut.FpvSecCmEflashRspFifoRptrCheck_A	0	0	398386977	0	0	0
tb.dut.FpvSecCmEflashRspFifoWptrCheck_A	0	0	398386977	0	0	0
tb.dut.FpvSecCmEflashSramReqFifoRptrCheck_A	0	0	398386977	0	0	0
tb.dut.FpvSecCmEflashSramReqFifoWptrCheck_A	0	0	398386977	0	0	0
tb.dut.FpvSecCmRdReqFifoRptrCheck_A	0	0	398386977	0	0	0
tb.dut.FpvSecCmRdReqFifoWptrCheck_A	0	0	398386977	0	0	0
tb.dut.FpvSecCmRdSramReqFifoRptrCheck_A	0	0	398386977	0	0	0
tb.dut.FpvSecCmRdSramReqFifoWptrCheck_A	0	0	398386977	0	0	0
tb.dut.PrimRspPayLoad_A	0	0	398386977	0	0	0
tb.dut.u_eflash.gen_flash_cores[0].u_core.u_rd.u_valid_random.LockArbDecision_A	0	0	398386977	0	0	0
tb.dut.u_eflash.gen_flash_cores[0].u_core.u_rd.u_valid_random.ReqStaysHighUntilGranted0_M	0	0	398386977	0	0	0
tb.dut.u_eflash.gen_flash_cores[0].u_core.u_rd.u_valid_random.RoundRobin_A	0	0	398386977	0	0	1051
tb.dut.u_eflash.gen_flash_cores[1].u_core.u_rd.u_valid_random.LockArbDecision_A	0	0	398386977	0	0	0
tb.dut.u_eflash.gen_flash_cores[1].u_core.u_rd.u_valid_random.ReqStaysHighUntilGranted0_M	0	0	398386977	0	0	0
tb.dut.u_eflash.gen_flash_cores[1].u_core.u_rd.u_valid_random.RoundRobin_A	0	0	398386977	0	0	1051
tb.dut.u_eflash.u_scramble.u_prim_arbiter_tree_calc.gen_input_bufs[0].gen_rr_arbiter.u_arb.RoundRobin_A	0	0	398386977	0	0	1051
tb.dut.u_eflash.u_scramble.u_prim_arbiter_tree_calc.gen_input_bufs[1].gen_rr_arbiter.u_arb.RoundRobin_A	0	0	398386977	0	0	1051
tb.dut.u_eflash.u_scramble.u_prim_arbiter_tree_op.gen_input_bufs[0].gen_rr_arbiter.u_arb.RoundRobin_A	0	0	398386977	0	0	1051
tb.dut.u_eflash.u_scramble.u_prim_arbiter_tree_op.gen_input_bufs[1].gen_rr_arbiter.u_arb.RoundRobin_A	0	0	398386977	0	0	1051
tb.dut.u_prog_tl_gate.OutStandingOvfl_A	0	0	398386977	0	0	0
tb.dut.u_tl_gate.OutStandingOvfl_A	0	0	398386977	0	0	0
tb.dut.u_to_prog_fifo.rvalidHighReqFifoEmpty	0	0	398386977	0	0	0
tb.dut.u_to_prog_fifo.rvalidHighWhenRspFifoFull	0	0	398386977	0	0	0
tb.dut.u_to_prog_fifo.u_rspfifo.DataKnown_A	0	0	398386977	0	0	0
tb.dut.u_to_prog_fifo.u_rspfifo.gen_normal_fifo.depthShallNotExceedParamDepth	0	0	398386977	0	0	0
tb.dut.u_to_prog_fifo.u_sramreqfifo.DataKnown_A	0	0	398386977	0	0	0
tb.dut.u_to_prog_fifo.u_sramreqfifo.gen_normal_fifo.depthShallNotExceedParamDepth	0	0	398386977	0	0	0

Assertions Success:

ASSERTIONS	CATEGORY	SEVERITY	ATTEMPTS	REAL SUCCESSES	FAILURES	INCOMPLETE	SRC
tb.dut.FifoDepthCheck_A	0	0	1056	1056	0	0
tb.dut.FlashAddrKnown_A	0	0	398386977	267326623	0	0
tb.dut.FlashAddrKnown_AKnownEnable	0	0	398386977	397525516	0	0
tb.dut.FlashKnownO_A	0	0	398386977	397525516	0	0
tb.dut.FlashProgKnown_A	0	0	398386977	157659597	0	0
tb.dut.FlashProgKnown_AKnownEnable	0	0	398386977	397525516	0	0
tb.dut.FpvSecCmAddrCntAlertCheck_A	0	0	398386977	50	0	0
tb.dut.FpvSecCmArbFsmCheck_A	0	0	398386977	50	0	0
tb.dut.FpvSecCmLcCtrlFsmCheck_A	0	0	398386977	50	0	0
tb.dut.FpvSecCmLcCtrlRmaFsmCheck_A	0	0	398386977	50	0	0
tb.dut.FpvSecCmPageCntAlertCheck_A	0	0	398386977	50	0	0
tb.dut.FpvSecCmProgCnt_A	0	0	398386977	50	0	0
tb.dut.FpvSecCmRdCnt_A	0	0	398386977	50	0	0
tb.dut.FpvSecCmRdRspFifoRptrCheck_A	0	0	398386977	50	0	0
tb.dut.FpvSecCmRdRspFifoWptrCheck_A	0	0	398386977	50	0	0
tb.dut.FpvSecCmRegWeOnehotCheck_A	0	0	398386977	50	0	0
tb.dut.FpvSecCmSeedCntAlertCheck_A	0	0	398386977	50	0	0
tb.dut.FpvSecCmTlLcGateFsm_A	0	0	398386977	50	0	0
tb.dut.FpvSecCmTlProgLcGateFsm_A	0	0	398386977	50	0	0
tb.dut.FpvSecCmWipeIdx_A	0	0	398386977	50	0	0
tb.dut.FpvSecCmWordCntAlertCheck_A	0	0	398386977	50	0	0
tb.dut.IntrErrO_A	0	0	398386977	397525516	0	0
tb.dut.IntrOpDoneKnownO_A	0	0	398386977	397525516	0	0
tb.dut.IntrProgEmptyKnownO_A	0	0	398386977	397525516	0	0
tb.dut.IntrProgLvlKnownO_A	0	0	398386977	397525516	0	0
tb.dut.IntrProgRdFullKnownO_A	0	0	398386977	397525516	0	0
tb.dut.IntrRdLvlKnownO_A	0	0	398386977	397525516	0	0
tb.dut.MemRspPayLoad_A	0	0	398386977	5034235	0	0
tb.dut.MemRspPayLoad_AKnownEnable	0	0	398386977	397525516	0	0
tb.dut.MemTlAReadyKnownO_A	0	0	398386977	397525516	0	0
tb.dut.MemTlDValidKnownO_A	0	0	398386977	397525516	0	0
tb.dut.PrimRspPayLoad_AKnownEnable	0	0	398386977	397525516	0	0
tb.dut.PrimTlAReadyKnownO_A	0	0	398386977	397525516	0	0
tb.dut.PrimTlDValidKnownO_A	0	0	398386977	397525516	0	0
tb.dut.RspPayLoad_A	0	0	398207920	42054974	0	0
tb.dut.RspPayLoad_AKnownEnable	0	0	398386977	397525516	0	0
tb.dut.TdoEnIsOne_A	0	0	398386977	397525516	0	0
tb.dut.TdoKnown_A	0	0	398386977	397525516	0	0
tb.dut.TlAReadyKnownO_A	0	0	398386977	397525516	0	0
tb.dut.TlDValidKnownO_A	0	0	398386977	397525516	0	0
tb.dut.flash_ctrl_core_csr_assert.TlulOOBAddrErr_A	0	0	401508767	4442	0	0
tb.dut.flash_ctrl_core_csr_assert.addr_rd_A	0	0	401508767	842	0	0
tb.dut.flash_ctrl_core_csr_assert.bank0_info0_page_cfg_0_rd_A	0	0	401508767	1562	0	0
tb.dut.flash_ctrl_core_csr_assert.bank0_info0_page_cfg_1_rd_A	0	0	401508767	1475	0	0
tb.dut.flash_ctrl_core_csr_assert.bank0_info0_page_cfg_2_rd_A	0	0	401508767	1520	0	0
tb.dut.flash_ctrl_core_csr_assert.bank0_info0_page_cfg_3_rd_A	0	0	401508767	1474	0	0
tb.dut.flash_ctrl_core_csr_assert.bank0_info0_page_cfg_4_rd_A	0	0	401508767	1584	0	0
tb.dut.flash_ctrl_core_csr_assert.bank0_info0_page_cfg_5_rd_A	0	0	401508767	1583	0	0
tb.dut.flash_ctrl_core_csr_assert.bank0_info0_page_cfg_6_rd_A	0	0	401508767	1600	0	0
tb.dut.flash_ctrl_core_csr_assert.bank0_info0_page_cfg_7_rd_A	0	0	401508767	1588	0	0
tb.dut.flash_ctrl_core_csr_assert.bank0_info0_page_cfg_8_rd_A	0	0	401508767	1354	0	0
tb.dut.flash_ctrl_core_csr_assert.bank0_info0_page_cfg_9_rd_A	0	0	401508767	1555	0	0
tb.dut.flash_ctrl_core_csr_assert.bank0_info0_regwen_0_rd_A	0	0	401508767	845	0	0
tb.dut.flash_ctrl_core_csr_assert.bank0_info0_regwen_1_rd_A	0	0	401508767	931	0	0
tb.dut.flash_ctrl_core_csr_assert.bank0_info0_regwen_2_rd_A	0	0	401508767	883	0	0
tb.dut.flash_ctrl_core_csr_assert.bank0_info0_regwen_3_rd_A	0	0	401508767	832	0	0
tb.dut.flash_ctrl_core_csr_assert.bank0_info0_regwen_4_rd_A	0	0	401508767	917	0	0
tb.dut.flash_ctrl_core_csr_assert.bank0_info0_regwen_5_rd_A	0	0	401508767	925	0	0
tb.dut.flash_ctrl_core_csr_assert.bank0_info0_regwen_6_rd_A	0	0	401508767	805	0	0
tb.dut.flash_ctrl_core_csr_assert.bank0_info0_regwen_7_rd_A	0	0	401508767	782	0	0
tb.dut.flash_ctrl_core_csr_assert.bank0_info0_regwen_8_rd_A	0	0	401508767	907	0	0
tb.dut.flash_ctrl_core_csr_assert.bank0_info0_regwen_9_rd_A	0	0	401508767	926	0	0
tb.dut.flash_ctrl_core_csr_assert.bank0_info1_page_cfg_rd_A	0	0	401508767	1686	0	0
tb.dut.flash_ctrl_core_csr_assert.bank0_info1_regwen_rd_A	0	0	401508767	804	0	0
tb.dut.flash_ctrl_core_csr_assert.bank0_info2_page_cfg_0_rd_A	0	0	401508767	1527	0	0
tb.dut.flash_ctrl_core_csr_assert.bank0_info2_page_cfg_1_rd_A	0	0	401508767	1531	0	0
tb.dut.flash_ctrl_core_csr_assert.bank0_info2_regwen_0_rd_A	0	0	401508767	859	0	0
tb.dut.flash_ctrl_core_csr_assert.bank0_info2_regwen_1_rd_A	0	0	401508767	937	0	0
tb.dut.flash_ctrl_core_csr_assert.bank1_info0_page_cfg_0_rd_A	0	0	401508767	1733	0	0
tb.dut.flash_ctrl_core_csr_assert.bank1_info0_page_cfg_1_rd_A	0	0	401508767	1676	0	0
tb.dut.flash_ctrl_core_csr_assert.bank1_info0_page_cfg_2_rd_A	0	0	401508767	1480	0	0
tb.dut.flash_ctrl_core_csr_assert.bank1_info0_page_cfg_3_rd_A	0	0	401508767	1565	0	0
tb.dut.flash_ctrl_core_csr_assert.bank1_info0_page_cfg_4_rd_A	0	0	401508767	1583	0	0
tb.dut.flash_ctrl_core_csr_assert.bank1_info0_page_cfg_5_rd_A	0	0	401508767	1417	0	0
tb.dut.flash_ctrl_core_csr_assert.bank1_info0_page_cfg_6_rd_A	0	0	401508767	1686	0	0
tb.dut.flash_ctrl_core_csr_assert.bank1_info0_page_cfg_7_rd_A	0	0	401508767	1736	0	0
tb.dut.flash_ctrl_core_csr_assert.bank1_info0_page_cfg_8_rd_A	0	0	401508767	1569	0	0
tb.dut.flash_ctrl_core_csr_assert.bank1_info0_page_cfg_9_rd_A	0	0	401508767	1416	0	0
tb.dut.flash_ctrl_core_csr_assert.bank1_info0_regwen_0_rd_A	0	0	401508767	861	0	0
tb.dut.flash_ctrl_core_csr_assert.bank1_info0_regwen_1_rd_A	0	0	401508767	884	0	0
tb.dut.flash_ctrl_core_csr_assert.bank1_info0_regwen_2_rd_A	0	0	401508767	842	0	0
tb.dut.flash_ctrl_core_csr_assert.bank1_info0_regwen_3_rd_A	0	0	401508767	842	0	0
tb.dut.flash_ctrl_core_csr_assert.bank1_info0_regwen_4_rd_A	0	0	401508767	795	0	0
tb.dut.flash_ctrl_core_csr_assert.bank1_info0_regwen_5_rd_A	0	0	401508767	936	0	0
tb.dut.flash_ctrl_core_csr_assert.bank1_info0_regwen_6_rd_A	0	0	401508767	904	0	0
tb.dut.flash_ctrl_core_csr_assert.bank1_info0_regwen_7_rd_A	0	0	401508767	868	0	0
tb.dut.flash_ctrl_core_csr_assert.bank1_info0_regwen_8_rd_A	0	0	401508767	855	0	0
tb.dut.flash_ctrl_core_csr_assert.bank1_info0_regwen_9_rd_A	0	0	401508767	864	0	0
tb.dut.flash_ctrl_core_csr_assert.bank1_info1_page_cfg_rd_A	0	0	401508767	1830	0	0
tb.dut.flash_ctrl_core_csr_assert.bank1_info1_regwen_rd_A	0	0	401508767	899	0	0
tb.dut.flash_ctrl_core_csr_assert.bank1_info2_page_cfg_0_rd_A	0	0	401508767	1617	0	0
tb.dut.flash_ctrl_core_csr_assert.bank1_info2_page_cfg_1_rd_A	0	0	401508767	1666	0	0
tb.dut.flash_ctrl_core_csr_assert.bank1_info2_regwen_0_rd_A	0	0	401508767	781	0	0
tb.dut.flash_ctrl_core_csr_assert.bank1_info2_regwen_1_rd_A	0	0	401508767	920	0	0
tb.dut.flash_ctrl_core_csr_assert.bank_cfg_regwen_rd_A	0	0	401508767	815	0	0
tb.dut.flash_ctrl_core_csr_assert.default_region_rd_A	0	0	401508767	1500	0	0
tb.dut.flash_ctrl_core_csr_assert.exec_rd_A	0	0	401508767	835	0	0
tb.dut.flash_ctrl_core_csr_assert.fifo_lvl_rd_A	0	0	401508767	882	0	0
tb.dut.flash_ctrl_core_csr_assert.fifo_rst_rd_A	0	0	401508767	890	0	0
tb.dut.flash_ctrl_core_csr_assert.hw_info_cfg_override_rd_A	0	0	401508767	950	0	0
tb.dut.flash_ctrl_core_csr_assert.intr_enable_rd_A	0	0	401508767	1504	0	0
tb.dut.flash_ctrl_core_csr_assert.mp_region_0_rd_A	0	0	401508767	1001	0	0
tb.dut.flash_ctrl_core_csr_assert.mp_region_1_rd_A	0	0	401508767	1070	0	0
tb.dut.flash_ctrl_core_csr_assert.mp_region_2_rd_A	0	0	401508767	1072	0	0
tb.dut.flash_ctrl_core_csr_assert.mp_region_3_rd_A	0	0	401508767	943	0	0
tb.dut.flash_ctrl_core_csr_assert.mp_region_4_rd_A	0	0	401508767	1016	0	0
tb.dut.flash_ctrl_core_csr_assert.mp_region_5_rd_A	0	0	401508767	1098	0	0
tb.dut.flash_ctrl_core_csr_assert.mp_region_6_rd_A	0	0	401508767	1133	0	0
tb.dut.flash_ctrl_core_csr_assert.mp_region_7_rd_A	0	0	401508767	951	0	0
tb.dut.flash_ctrl_core_csr_assert.mp_region_cfg_0_rd_A	0	0	401508767	1529	0	0
tb.dut.flash_ctrl_core_csr_assert.mp_region_cfg_1_rd_A	0	0	401508767	1766	0	0
tb.dut.flash_ctrl_core_csr_assert.mp_region_cfg_2_rd_A	0	0	401508767	1598	0	0
tb.dut.flash_ctrl_core_csr_assert.mp_region_cfg_3_rd_A	0	0	401508767	1605	0	0
tb.dut.flash_ctrl_core_csr_assert.mp_region_cfg_4_rd_A	0	0	401508767	1505	0	0
tb.dut.flash_ctrl_core_csr_assert.mp_region_cfg_5_rd_A	0	0	401508767	1637	0	0
tb.dut.flash_ctrl_core_csr_assert.mp_region_cfg_6_rd_A	0	0	401508767	1722	0	0
tb.dut.flash_ctrl_core_csr_assert.mp_region_cfg_7_rd_A	0	0	401508767	1675	0	0
tb.dut.flash_ctrl_core_csr_assert.phy_alert_cfg_rd_A	0	0	401508767	134	0	0
tb.dut.flash_ctrl_core_csr_assert.region_cfg_regwen_0_rd_A	0	0	401508767	912	0	0
tb.dut.flash_ctrl_core_csr_assert.region_cfg_regwen_1_rd_A	0	0	401508767	879	0	0
tb.dut.flash_ctrl_core_csr_assert.region_cfg_regwen_2_rd_A	0	0	401508767	942	0	0
tb.dut.flash_ctrl_core_csr_assert.region_cfg_regwen_3_rd_A	0	0	401508767	948	0	0
tb.dut.flash_ctrl_core_csr_assert.region_cfg_regwen_4_rd_A	0	0	401508767	913	0	0
tb.dut.flash_ctrl_core_csr_assert.region_cfg_regwen_5_rd_A	0	0	401508767	998	0	0
tb.dut.flash_ctrl_core_csr_assert.region_cfg_regwen_6_rd_A	0	0	401508767	870	0	0
tb.dut.flash_ctrl_core_csr_assert.region_cfg_regwen_7_rd_A	0	0	401508767	928	0	0
tb.dut.flash_ctrl_core_csr_assert.scratch_rd_A	0	0	401508767	843	0	0
tb.dut.gen_phy_assertions[0].FpvSecCmPhyFsmCheck_A	0	0	398386977	50	0	0
tb.dut.gen_phy_assertions[0].FpvSecCmPhyProgFsmCheck_A	0	0	398386977	50	0	0
tb.dut.gen_phy_assertions[1].FpvSecCmPhyFsmCheck_A	0	0	398386977	50	0	0
tb.dut.gen_phy_assertions[1].FpvSecCmPhyProgFsmCheck_A	0	0	398386977	50	0	0
tb.dut.gen_phy_cnt_errs[0].FpvSecCmPhyHostCnt_A	0	0	398386977	50	0	0
tb.dut.gen_phy_cnt_errs[0].FpvSecCmPhyRdDataFifoRPtr_A	0	0	398386977	50	0	0
tb.dut.gen_phy_cnt_errs[0].FpvSecCmPhyRdDataFifoWPtr_A	0	0	398386977	50	0	0
tb.dut.gen_phy_cnt_errs[0].FpvSecCmPhyRdRspFifoRPtr_A	0	0	398386977	50	0	0
tb.dut.gen_phy_cnt_errs[0].FpvSecCmPhyRdRspFifoWPtr_A	0	0	398386977	50	0	0
tb.dut.gen_phy_cnt_errs[0].FpvSecCmPhyRspFifoRPtr_A	0	0	398386977	50	0	0
tb.dut.gen_phy_cnt_errs[0].FpvSecCmPhyRspFifoWPtr_A	0	0	398386977	50	0	0
tb.dut.gen_phy_cnt_errs[1].FpvSecCmPhyHostCnt_A	0	0	398386977	50	0	0
tb.dut.gen_phy_cnt_errs[1].FpvSecCmPhyRdDataFifoRPtr_A	0	0	398386977	50	0	0
tb.dut.gen_phy_cnt_errs[1].FpvSecCmPhyRdDataFifoWPtr_A	0	0	398386977	50	0	0
tb.dut.gen_phy_cnt_errs[1].FpvSecCmPhyRdRspFifoRPtr_A	0	0	398386977	50	0	0
tb.dut.gen_phy_cnt_errs[1].FpvSecCmPhyRdRspFifoWPtr_A	0	0	398386977	50	0	0
tb.dut.gen_phy_cnt_errs[1].FpvSecCmPhyRspFifoRPtr_A	0	0	398386977	50	0	0
tb.dut.gen_phy_cnt_errs[1].FpvSecCmPhyRspFifoWPtr_A	0	0	398386977	50	0	0
tb.dut.gen_reg_we_assert_generic.FpvSecCmPrimRegWeOnehotCheck_A	0	0	398386977	31	0	0
tb.dut.tlul_assert_device.aKnown_A	0	0	401508707	34449830	0	0
tb.dut.tlul_assert_device.aKnown_AKnownEnable	0	0	401508707	400559625	0	0
tb.dut.tlul_assert_device.aReadyKnown_A	0	0	401508707	400559625	0	0
tb.dut.tlul_assert_device.dKnown_A	0	0	401508707	42779538	0	0
tb.dut.tlul_assert_device.dKnown_AKnownEnable	0	0	401508707	400559625	0	0
tb.dut.tlul_assert_device.dReadyKnown_A	0	0	401508707	400559625	0	0
tb.dut.tlul_assert_device.gen_assert_final[0].noOutstandingReqsAtEndOfSim_A	0	0	1266	1266	0	0
tb.dut.tlul_assert_device.gen_assert_final[100].noOutstandingReqsAtEndOfSim_A	0	0	1266	1266	0	0
tb.dut.tlul_assert_device.gen_assert_final[101].noOutstandingReqsAtEndOfSim_A	0	0	1266	1266	0	0
tb.dut.tlul_assert_device.gen_assert_final[102].noOutstandingReqsAtEndOfSim_A	0	0	1266	1266	0	0
tb.dut.tlul_assert_device.gen_assert_final[103].noOutstandingReqsAtEndOfSim_A	0	0	1266	1266	0	0
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tb.dut.tlul_assert_device.gen_assert_final[172].noOutstandingReqsAtEndOfSim_A	0	0	1266	1266	0	0
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tb.dut.tlul_assert_device.gen_assert_final[174].noOutstandingReqsAtEndOfSim_A	0	0	1266	1266	0	0
tb.dut.tlul_assert_device.gen_assert_final[175].noOutstandingReqsAtEndOfSim_A	0	0	1266	1266	0	0

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