Tests
dashboard | hierarchy | modlist | groups | tests | asserts
Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
96.20 95.74 94.03 98.31 91.84 98.34 96.89 98.24


Total tests in report: 1271
Tests are in graded order

Scores are accumulated (Total) and incremental (Incr) for each test.

SCORE LINE COND TOGGLE FSM BRANCH ASSERT GROUP  
TOTAL INCRTOTALINCRTOTALINCRTOTALINCRTOTALINCRTOTALINCRTOTALINCRTOTALINCRNAME
60.27 60.27 85.88 85.88 69.54 69.54 54.58 54.58 19.73 19.73 81.97 81.97 80.58 80.58 29.59 29.59 /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/0.flash_ctrl_fetch_code.3199175620
70.32 10.05 88.07 2.20 74.55 5.01 61.08 6.50 48.30 28.57 84.89 2.92 82.14 1.55 53.21 23.61 /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/0.flash_ctrl_mp_regions.3386694143
75.01 4.69 91.16 3.09 80.38 5.84 63.33 2.25 48.30 0.00 90.70 5.80 83.01 0.87 68.22 15.01 /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/cover_reg_top/0.flash_ctrl_csr_mem_rw_with_rand_reset.3025139238
78.68 3.67 91.89 0.73 80.93 0.54 72.34 9.01 62.59 14.29 91.66 0.96 83.11 0.10 68.25 0.03 /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/1.flash_ctrl_otp_reset.247990062
81.63 2.95 92.87 0.98 83.10 2.17 79.62 7.28 66.67 4.08 93.47 1.81 83.50 0.39 72.16 3.91 /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/0.flash_ctrl_rw_evict.1926195226
83.51 1.89 92.87 0.00 83.22 0.12 79.62 0.00 66.67 0.00 93.47 0.00 91.84 8.35 76.91 4.75 /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/cover_reg_top/6.flash_ctrl_csr_mem_rw_with_rand_reset.888240498
85.05 1.54 93.05 0.18 84.08 0.86 83.65 4.03 68.03 1.36 94.22 0.75 95.15 3.30 77.19 0.28 /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/2.flash_ctrl_sec_cm.870293537
86.42 1.36 93.57 0.52 84.96 0.89 86.04 2.39 72.79 4.76 94.84 0.62 95.34 0.19 77.37 0.18 /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/0.flash_ctrl_rma_err.3264676531
87.78 1.36 93.77 0.20 85.08 0.11 91.41 5.36 75.51 2.72 95.09 0.26 95.34 0.00 78.27 0.89 /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/0.flash_ctrl_serr_address.2893528581
88.82 1.03 93.89 0.12 85.56 0.48 92.74 1.33 80.27 4.76 95.31 0.21 95.44 0.10 78.51 0.25 /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/0.flash_ctrl_mid_op_rst.2130553357
89.72 0.90 94.06 0.18 88.36 2.81 92.85 0.11 80.27 0.00 95.67 0.36 95.92 0.49 80.89 2.37 /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/0.flash_ctrl_rw_serr.3676583535
90.49 0.77 94.06 0.00 88.78 0.42 92.85 0.00 80.27 0.00 95.67 0.00 95.92 0.00 85.88 4.99 /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/cover_reg_top/0.flash_ctrl_csr_bit_bash.3231902517
91.10 0.61 94.15 0.09 88.80 0.02 92.85 0.00 84.35 4.08 95.75 0.09 95.92 0.00 85.88 0.00 /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/3.flash_ctrl_mid_op_rst.2392082646
91.50 0.40 95.05 0.90 89.03 0.23 92.85 0.00 84.35 0.00 97.38 1.62 95.92 0.00 85.94 0.06 /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/2.flash_ctrl_phy_host_grant_err.2983577582
91.88 0.37 95.09 0.04 89.23 0.20 94.70 1.85 84.35 0.00 97.42 0.04 95.92 0.00 86.44 0.49 /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/0.flash_ctrl_hw_sec_otp.953586226
92.21 0.34 95.24 0.15 90.04 0.81 94.70 0.00 84.35 0.00 97.42 0.00 95.92 0.00 87.82 1.39 /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/cover_reg_top/3.flash_ctrl_tl_errors.3381752525
92.52 0.31 95.31 0.07 90.30 0.26 94.83 0.13 84.35 0.00 97.59 0.17 95.92 0.00 89.33 1.51 /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/0.flash_ctrl_intr_rd_slow_flash.2857095289
92.80 0.28 95.32 0.01 90.30 0.00 95.28 0.45 85.71 1.36 97.61 0.02 96.02 0.10 89.33 0.00 /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/1.flash_ctrl_hw_rma.86747096
93.02 0.23 95.32 0.00 90.44 0.14 95.81 0.53 86.39 0.68 97.63 0.02 96.02 0.00 89.55 0.22 /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/0.flash_ctrl_wr_intg.1938708451
93.24 0.21 95.32 0.00 90.47 0.03 95.87 0.06 87.76 1.36 97.63 0.00 96.02 0.00 89.58 0.03 /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/8.flash_ctrl_otp_reset.563006603
93.44 0.21 95.32 0.00 90.48 0.01 95.87 0.00 87.76 0.00 97.63 0.00 96.02 0.00 91.03 1.45 /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/cover_reg_top/7.flash_ctrl_intr_test.546552720
93.65 0.20 95.33 0.01 90.49 0.01 95.87 0.00 89.12 1.36 97.67 0.04 96.02 0.00 91.03 0.00 /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/77.flash_ctrl_otp_reset.3716159848
93.85 0.20 95.34 0.01 90.55 0.07 95.90 0.03 89.12 0.00 97.70 0.02 96.02 0.00 92.29 1.26 /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/cover_reg_top/15.flash_ctrl_tl_intg_err.4236721658
94.02 0.17 95.40 0.06 90.68 0.12 96.26 0.35 89.12 0.00 97.82 0.13 96.02 0.00 92.85 0.55 /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/1.flash_ctrl_sec_info_access.2625821658
94.17 0.14 95.41 0.01 91.12 0.44 96.31 0.05 89.12 0.00 97.85 0.02 96.12 0.10 93.25 0.40 /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/0.flash_ctrl_rw_derr.749817179
94.31 0.14 95.48 0.07 91.33 0.22 96.32 0.02 89.12 0.00 97.93 0.09 96.50 0.39 93.46 0.22 /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/1.flash_ctrl_mp_regions.680726535
94.43 0.12 95.58 0.10 91.44 0.10 96.79 0.47 89.12 0.00 97.93 0.00 96.50 0.00 93.65 0.18 /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/0.flash_ctrl_alert_test.2906666777
94.55 0.12 95.66 0.08 91.91 0.47 97.06 0.27 89.12 0.00 97.93 0.00 96.50 0.00 93.65 0.00 /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/5.flash_ctrl_hw_sec_otp.3076158832
94.65 0.11 95.66 0.00 92.03 0.12 97.19 0.13 89.12 0.00 97.97 0.04 96.50 0.00 94.11 0.46 /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/0.flash_ctrl_re_evict.620289488
94.76 0.11 95.66 0.00 92.03 0.00 97.22 0.03 89.80 0.68 97.97 0.00 96.50 0.00 94.14 0.03 /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/18.flash_ctrl_otp_reset.898300605
94.87 0.11 95.67 0.01 92.03 0.00 97.22 0.00 90.48 0.68 97.99 0.02 96.50 0.00 94.17 0.03 /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/71.flash_ctrl_otp_reset.2334021869
94.97 0.10 95.67 0.00 92.03 0.00 97.24 0.02 91.16 0.68 97.99 0.00 96.50 0.00 94.17 0.00 /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/1.flash_ctrl_mid_op_rst.3704917737
95.06 0.10 95.67 0.00 92.03 0.00 97.24 0.00 91.84 0.68 97.99 0.00 96.50 0.00 94.17 0.00 /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/4.flash_ctrl_host_ctrl_arb.1082570313
95.16 0.09 95.67 0.00 92.20 0.17 97.24 0.00 91.84 0.00 97.99 0.00 96.50 0.00 94.67 0.49 /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/cover_reg_top/0.flash_ctrl_csr_aliasing.609211848
95.21 0.06 95.67 0.00 92.20 0.00 97.24 0.00 91.84 0.00 97.99 0.00 96.89 0.39 94.67 0.00 /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/cover_reg_top/2.flash_ctrl_mem_partial_access.882676224
95.27 0.06 95.67 0.00 92.26 0.06 97.24 0.00 91.84 0.00 98.02 0.02 96.89 0.00 94.98 0.31 /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/1.flash_ctrl_rd_buff_evict.1763793742
95.32 0.05 95.67 0.00 92.27 0.01 97.24 0.00 91.84 0.00 98.02 0.00 96.89 0.00 95.35 0.37 /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/2.flash_ctrl_intr_rd.1727579998
95.37 0.05 95.67 0.00 92.30 0.03 97.46 0.22 91.84 0.00 98.04 0.02 96.89 0.00 95.41 0.06 /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/1.flash_ctrl_hw_prog_rma_wipe_err.3714441726
95.42 0.05 95.67 0.00 92.34 0.05 97.69 0.22 91.84 0.00 98.06 0.02 96.89 0.00 95.44 0.03 /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/8.flash_ctrl_lcmgr_intg.1715593407
95.46 0.04 95.67 0.00 92.50 0.15 97.75 0.06 91.84 0.00 98.06 0.00 96.89 0.00 95.53 0.09 /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/0.flash_ctrl_oversize_error.2999247206
95.50 0.04 95.67 0.00 92.50 0.00 97.75 0.00 91.84 0.00 98.06 0.00 96.89 0.00 95.81 0.28 /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/cover_reg_top/0.flash_ctrl_intr_test.3354742508
95.54 0.04 95.67 0.00 92.56 0.07 97.77 0.02 91.84 0.00 98.06 0.00 96.89 0.00 95.99 0.18 /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/0.flash_ctrl_invalid_op.2867479541
95.57 0.03 95.67 0.00 92.58 0.02 97.77 0.00 91.84 0.00 98.06 0.00 96.89 0.00 96.21 0.22 /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/cover_reg_top/9.flash_ctrl_tl_intg_err.3402364058
95.61 0.03 95.67 0.00 92.75 0.17 97.77 0.00 91.84 0.00 98.06 0.00 96.89 0.00 96.27 0.06 /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/cover_reg_top/4.flash_ctrl_tl_errors.624314458
95.64 0.03 95.67 0.00 92.82 0.07 97.77 0.00 91.84 0.00 98.06 0.00 96.89 0.00 96.42 0.15 /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/2.flash_ctrl_rw_derr.2814285857
95.66 0.02 95.69 0.03 92.86 0.04 97.77 0.00 91.84 0.00 98.17 0.11 96.89 0.00 96.42 0.00 /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/4.flash_ctrl_phy_host_grant_err.1097048969
95.69 0.02 95.69 0.00 92.86 0.00 97.93 0.16 91.84 0.00 98.17 0.00 96.89 0.00 96.42 0.00 /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/3.flash_ctrl_hw_rma_reset.609416205
95.71 0.02 95.69 0.00 92.93 0.08 97.94 0.02 91.84 0.00 98.19 0.02 96.89 0.00 96.45 0.03 /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/0.flash_ctrl_phy_ack_consistency.1694877633
95.73 0.02 95.69 0.00 92.94 0.01 97.94 0.00 91.84 0.00 98.19 0.00 96.89 0.00 96.58 0.12 /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/4.flash_ctrl_fs_sup.1768169245
95.74 0.02 95.69 0.00 92.97 0.03 97.99 0.05 91.84 0.00 98.21 0.02 96.89 0.00 96.61 0.03 /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/17.flash_ctrl_disable.2345370290
95.76 0.02 95.69 0.00 93.04 0.07 97.99 0.00 91.84 0.00 98.21 0.00 96.89 0.00 96.67 0.06 /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/0.flash_ctrl_rd_intg.2576296948
95.78 0.02 95.69 0.00 93.04 0.00 97.99 0.00 91.84 0.00 98.21 0.00 96.89 0.00 96.79 0.12 /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/cover_reg_top/6.flash_ctrl_tl_intg_err.2682621881
95.80 0.02 95.69 0.00 93.11 0.07 97.99 0.00 91.84 0.00 98.23 0.02 96.89 0.00 96.82 0.03 /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/2.flash_ctrl_phy_arb_redun.677485512
95.81 0.02 95.69 0.00 93.13 0.02 97.99 0.00 91.84 0.00 98.23 0.00 96.89 0.00 96.92 0.09 /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/0.flash_ctrl_rw.4058362743
95.83 0.02 95.69 0.00 93.20 0.08 97.99 0.00 91.84 0.00 98.23 0.00 96.89 0.00 96.95 0.03 /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/1.flash_ctrl_error_prog_type.4262920892
95.84 0.01 95.69 0.00 93.21 0.01 98.02 0.03 91.84 0.00 98.23 0.00 96.89 0.00 97.01 0.06 /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/4.flash_ctrl_intr_rd.4166578093
95.86 0.01 95.69 0.00 93.25 0.04 98.02 0.00 91.84 0.00 98.23 0.00 96.89 0.00 97.07 0.06 /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/cover_reg_top/1.flash_ctrl_csr_aliasing.1522925840
95.87 0.01 95.69 0.00 93.25 0.00 98.02 0.00 91.84 0.00 98.23 0.00 96.89 0.00 97.16 0.09 /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/cover_reg_top/12.flash_ctrl_tl_intg_err.500245331
95.88 0.01 95.69 0.00 93.25 0.00 98.02 0.00 91.84 0.00 98.23 0.00 96.89 0.00 97.26 0.09 /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/8.flash_ctrl_re_evict.1134177993
95.90 0.01 95.74 0.04 93.25 0.00 98.04 0.02 91.84 0.00 98.23 0.00 96.89 0.00 97.29 0.03 /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/7.flash_ctrl_connect.1768277971
95.91 0.01 95.74 0.00 93.31 0.06 98.04 0.00 91.84 0.00 98.25 0.02 96.89 0.00 97.29 0.00 /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/1.flash_ctrl_fetch_code.865922735
95.92 0.01 95.74 0.00 93.32 0.01 98.10 0.06 91.84 0.00 98.25 0.00 96.89 0.00 97.29 0.00 /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/0.flash_ctrl_error_prog_win.4081478633
95.93 0.01 95.74 0.00 93.33 0.01 98.17 0.06 91.84 0.00 98.25 0.00 96.89 0.00 97.29 0.00 /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/3.flash_ctrl_lcmgr_intg.291812739
95.94 0.01 95.74 0.00 93.34 0.02 98.17 0.00 91.84 0.00 98.27 0.02 96.89 0.00 97.32 0.03 /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/11.flash_ctrl_hw_prog_rma_wipe_err.2504664496
95.95 0.01 95.74 0.00 93.39 0.05 98.17 0.00 91.84 0.00 98.29 0.02 96.89 0.00 97.32 0.00 /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/0.flash_ctrl_phy_host_grant_err.2552572478
95.96 0.01 95.74 0.00 93.43 0.04 98.17 0.00 91.84 0.00 98.29 0.00 96.89 0.00 97.35 0.03 /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/5.flash_ctrl_otp_reset.1827735637
95.97 0.01 95.74 0.00 93.45 0.02 98.19 0.02 91.84 0.00 98.29 0.00 96.89 0.00 97.38 0.03 /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/7.flash_ctrl_disable.2150329001
95.98 0.01 95.74 0.00 93.50 0.05 98.20 0.02 91.84 0.00 98.29 0.00 96.89 0.00 97.38 0.00 /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/0.flash_ctrl_access_after_disable.2227090079
95.99 0.01 95.74 0.00 93.51 0.01 98.20 0.00 91.84 0.00 98.31 0.02 96.89 0.00 97.41 0.03 /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/0.flash_ctrl_hw_prog_rma_wipe_err.3205806279
95.99 0.01 95.74 0.00 93.52 0.01 98.20 0.00 91.84 0.00 98.34 0.02 96.89 0.00 97.44 0.03 /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/0.flash_ctrl_hw_read_seed_err.1813969164
96.00 0.01 95.74 0.00 93.52 0.00 98.20 0.00 91.84 0.00 98.34 0.00 96.89 0.00 97.50 0.06 /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/cover_reg_top/15.flash_ctrl_intr_test.3702703632
96.01 0.01 95.74 0.00 93.52 0.00 98.20 0.00 91.84 0.00 98.34 0.00 96.89 0.00 97.56 0.06 /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/cover_reg_top/18.flash_ctrl_tl_intg_err.1156504367
96.02 0.01 95.74 0.00 93.52 0.00 98.20 0.00 91.84 0.00 98.34 0.00 96.89 0.00 97.63 0.06 /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/0.flash_ctrl_sec_info_access.3502968244
96.03 0.01 95.74 0.00 93.52 0.00 98.20 0.00 91.84 0.00 98.34 0.00 96.89 0.00 97.69 0.06 /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/11.flash_ctrl_rw_evict_all_en.1456842471
96.04 0.01 95.74 0.00 93.52 0.00 98.20 0.00 91.84 0.00 98.34 0.00 96.89 0.00 97.75 0.06 /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/11.flash_ctrl_sec_info_access.1017702409
96.05 0.01 95.74 0.00 93.52 0.00 98.20 0.00 91.84 0.00 98.34 0.00 96.89 0.00 97.81 0.06 /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/20.flash_ctrl_rw_evict_all_en.43970977
96.06 0.01 95.74 0.00 93.52 0.00 98.20 0.00 91.84 0.00 98.34 0.00 96.89 0.00 97.87 0.06 /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/25.flash_ctrl_sec_info_access.2976322900
96.06 0.01 95.74 0.00 93.57 0.06 98.20 0.00 91.84 0.00 98.34 0.00 96.89 0.00 97.87 0.00 /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/0.flash_ctrl_erase_suspend.3595356841
96.07 0.01 95.74 0.00 93.61 0.04 98.22 0.02 91.84 0.00 98.34 0.00 96.89 0.00 97.87 0.00 /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/16.flash_ctrl_hw_sec_otp.789692692
96.08 0.01 95.74 0.00 93.63 0.02 98.25 0.03 91.84 0.00 98.34 0.00 96.89 0.00 97.87 0.00 /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/1.flash_ctrl_rw_evict.1462123476
96.09 0.01 95.74 0.00 93.68 0.05 98.25 0.00 91.84 0.00 98.34 0.00 96.89 0.00 97.87 0.00 /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/0.flash_ctrl_phy_arb_redun.3420118129
96.09 0.01 95.74 0.00 93.73 0.05 98.25 0.00 91.84 0.00 98.34 0.00 96.89 0.00 97.87 0.00 /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/1.flash_ctrl_phy_ack_consistency.1240076788
96.10 0.01 95.74 0.00 93.73 0.01 98.28 0.03 91.84 0.00 98.34 0.00 96.89 0.00 97.87 0.00 /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/1.flash_ctrl_sec_cm.4290880825
96.10 0.01 95.74 0.00 93.74 0.01 98.28 0.00 91.84 0.00 98.34 0.00 96.89 0.00 97.90 0.03 /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/0.flash_ctrl_fs_sup.3009267976
96.11 0.01 95.74 0.00 93.75 0.01 98.28 0.00 91.84 0.00 98.34 0.00 96.89 0.00 97.93 0.03 /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/0.flash_ctrl_full_mem_access.3963244808
96.12 0.01 95.74 0.00 93.79 0.04 98.28 0.00 91.84 0.00 98.34 0.00 96.89 0.00 97.93 0.00 /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/cover_reg_top/16.flash_ctrl_tl_errors.4283130396
96.12 0.01 95.74 0.00 93.83 0.04 98.28 0.00 91.84 0.00 98.34 0.00 96.89 0.00 97.93 0.00 /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/1.flash_ctrl_wr_intg.4056994345
96.13 0.01 95.74 0.00 93.87 0.04 98.28 0.00 91.84 0.00 98.34 0.00 96.89 0.00 97.93 0.00 /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/4.flash_ctrl_ro_derr.1309816142
96.13 0.01 95.74 0.00 93.87 0.00 98.31 0.03 91.84 0.00 98.34 0.00 96.89 0.00 97.93 0.00 /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/0.flash_ctrl_disable.518145303
96.14 0.01 95.74 0.00 93.87 0.00 98.31 0.00 91.84 0.00 98.34 0.00 96.89 0.00 97.97 0.03 /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/0.flash_ctrl_config_regwen.2237006450
96.14 0.01 95.74 0.00 93.87 0.00 98.31 0.00 91.84 0.00 98.34 0.00 96.89 0.00 98.00 0.03 /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/10.flash_ctrl_sec_info_access.2557207388
96.14 0.01 95.74 0.00 93.87 0.00 98.31 0.00 91.84 0.00 98.34 0.00 96.89 0.00 98.03 0.03 /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/11.flash_ctrl_hw_read_seed_err.4217191438
96.15 0.01 95.74 0.00 93.87 0.00 98.31 0.00 91.84 0.00 98.34 0.00 96.89 0.00 98.06 0.03 /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/12.flash_ctrl_disable.2423447632
96.15 0.01 95.74 0.00 93.87 0.00 98.31 0.00 91.84 0.00 98.34 0.00 96.89 0.00 98.09 0.03 /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/14.flash_ctrl_sec_info_access.980722312
96.16 0.01 95.74 0.00 93.87 0.00 98.31 0.00 91.84 0.00 98.34 0.00 96.89 0.00 98.12 0.03 /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/15.flash_ctrl_disable.135910862
96.16 0.01 95.74 0.00 93.87 0.00 98.31 0.00 91.84 0.00 98.34 0.00 96.89 0.00 98.15 0.03 /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/19.flash_ctrl_disable.640321200
96.17 0.01 95.74 0.00 93.87 0.00 98.31 0.00 91.84 0.00 98.34 0.00 96.89 0.00 98.18 0.03 /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/22.flash_ctrl_disable.407280344
96.17 0.01 95.74 0.00 93.87 0.00 98.31 0.00 91.84 0.00 98.34 0.00 96.89 0.00 98.21 0.03 /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/22.flash_ctrl_sec_info_access.211468712
96.18 0.01 95.74 0.00 93.87 0.00 98.31 0.00 91.84 0.00 98.34 0.00 96.89 0.00 98.24 0.03 /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/43.flash_ctrl_sec_info_access.2233386206
96.18 0.01 95.74 0.00 93.90 0.03 98.31 0.00 91.84 0.00 98.34 0.00 96.89 0.00 98.24 0.00 /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/0.flash_ctrl_intr_wr.1935464315
96.18 0.01 95.74 0.00 93.92 0.03 98.31 0.00 91.84 0.00 98.34 0.00 96.89 0.00 98.24 0.00 /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/0.flash_ctrl_rd_buff_evict.1100043867
96.19 0.01 95.74 0.00 93.95 0.03 98.31 0.00 91.84 0.00 98.34 0.00 96.89 0.00 98.24 0.00 /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/19.flash_ctrl_hw_rma_reset.1335105355
96.19 0.01 95.74 0.00 93.98 0.03 98.31 0.00 91.84 0.00 98.34 0.00 96.89 0.00 98.24 0.00 /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/4.flash_ctrl_phy_arb_redun.1210476561
96.19 0.01 95.74 0.00 94.00 0.02 98.31 0.00 91.84 0.00 98.34 0.00 96.89 0.00 98.24 0.00 /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/15.flash_ctrl_intr_rd_slow_flash.3339464122
96.20 0.01 95.74 0.00 94.01 0.01 98.31 0.00 91.84 0.00 98.34 0.00 96.89 0.00 98.24 0.00 /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/0.flash_ctrl_error_mp.1495035004
96.20 0.01 95.74 0.00 94.02 0.01 98.31 0.00 91.84 0.00 98.34 0.00 96.89 0.00 98.24 0.00 /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/2.flash_ctrl_host_ctrl_arb.1791407686
96.20 0.01 95.74 0.00 94.03 0.01 98.31 0.00 91.84 0.00 98.34 0.00 96.89 0.00 98.24 0.00 /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/4.flash_ctrl_oversize_error.807383684

Tests that do not contribute to grading

Name
/workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/cover_reg_top/0.flash_ctrl_csr_hw_reset.2318526888
/workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/cover_reg_top/0.flash_ctrl_csr_rw.1250176619
/workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/cover_reg_top/0.flash_ctrl_mem_partial_access.3822853289
/workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/cover_reg_top/0.flash_ctrl_mem_walk.620669932
/workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/cover_reg_top/0.flash_ctrl_same_csr_outstanding.3953465280
/workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/cover_reg_top/0.flash_ctrl_shadow_reg_errors.490963841
/workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/cover_reg_top/0.flash_ctrl_shadow_reg_errors_with_csr_rw.2325408885
/workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/cover_reg_top/0.flash_ctrl_tl_errors.410689845
/workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/cover_reg_top/0.flash_ctrl_tl_intg_err.1071098066
/workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/cover_reg_top/1.flash_ctrl_csr_bit_bash.75582770
/workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/cover_reg_top/1.flash_ctrl_csr_hw_reset.1023470652
/workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/cover_reg_top/1.flash_ctrl_csr_mem_rw_with_rand_reset.4286345876
/workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/cover_reg_top/1.flash_ctrl_csr_rw.4038798724
/workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/cover_reg_top/1.flash_ctrl_intr_test.4082942056
/workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/cover_reg_top/1.flash_ctrl_mem_partial_access.1975354945
/workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/cover_reg_top/1.flash_ctrl_mem_walk.2080496316
/workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/cover_reg_top/1.flash_ctrl_same_csr_outstanding.2248169285
/workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/cover_reg_top/1.flash_ctrl_shadow_reg_errors.194447666
/workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/cover_reg_top/1.flash_ctrl_shadow_reg_errors_with_csr_rw.2674728810
/workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/cover_reg_top/1.flash_ctrl_tl_errors.2986601089
/workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/cover_reg_top/1.flash_ctrl_tl_intg_err.770517876
/workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/cover_reg_top/10.flash_ctrl_csr_mem_rw_with_rand_reset.2400121954
/workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/cover_reg_top/10.flash_ctrl_csr_rw.1814793551
/workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/cover_reg_top/10.flash_ctrl_intr_test.3448680838
/workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/cover_reg_top/10.flash_ctrl_same_csr_outstanding.3529961989
/workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/cover_reg_top/10.flash_ctrl_shadow_reg_errors.1559320769
/workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/cover_reg_top/10.flash_ctrl_shadow_reg_errors_with_csr_rw.3914102558
/workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/cover_reg_top/10.flash_ctrl_tl_errors.3115838422
/workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/cover_reg_top/10.flash_ctrl_tl_intg_err.2456106567
/workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/cover_reg_top/11.flash_ctrl_csr_mem_rw_with_rand_reset.1022497825
/workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/cover_reg_top/11.flash_ctrl_csr_rw.387453283
/workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/cover_reg_top/11.flash_ctrl_intr_test.3382807577
/workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/cover_reg_top/11.flash_ctrl_same_csr_outstanding.2023603738
/workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/cover_reg_top/11.flash_ctrl_shadow_reg_errors.3210940126
/workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/cover_reg_top/11.flash_ctrl_shadow_reg_errors_with_csr_rw.716186207
/workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/cover_reg_top/11.flash_ctrl_tl_errors.515208078
/workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/cover_reg_top/11.flash_ctrl_tl_intg_err.3036075140
/workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/cover_reg_top/12.flash_ctrl_csr_mem_rw_with_rand_reset.2374549642
/workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/cover_reg_top/12.flash_ctrl_csr_rw.2931172740
/workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/cover_reg_top/12.flash_ctrl_intr_test.4014061292
/workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/cover_reg_top/12.flash_ctrl_same_csr_outstanding.1675325187
/workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/cover_reg_top/12.flash_ctrl_shadow_reg_errors.2579129524
/workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/cover_reg_top/12.flash_ctrl_shadow_reg_errors_with_csr_rw.3684161154
/workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/cover_reg_top/12.flash_ctrl_tl_errors.314987224
/workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/cover_reg_top/13.flash_ctrl_csr_mem_rw_with_rand_reset.3426535429
/workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/cover_reg_top/13.flash_ctrl_csr_rw.854913799
/workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/cover_reg_top/13.flash_ctrl_intr_test.1653634491
/workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/cover_reg_top/13.flash_ctrl_same_csr_outstanding.3970289001
/workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/cover_reg_top/13.flash_ctrl_shadow_reg_errors.3775003343
/workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/cover_reg_top/13.flash_ctrl_shadow_reg_errors_with_csr_rw.1830048990
/workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/cover_reg_top/13.flash_ctrl_tl_errors.1359126749
/workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/cover_reg_top/13.flash_ctrl_tl_intg_err.2044961451
/workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/cover_reg_top/14.flash_ctrl_csr_mem_rw_with_rand_reset.1320721389
/workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/cover_reg_top/14.flash_ctrl_csr_rw.260454705
/workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/cover_reg_top/14.flash_ctrl_intr_test.3284613962
/workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/cover_reg_top/14.flash_ctrl_same_csr_outstanding.4075302487
/workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/cover_reg_top/14.flash_ctrl_shadow_reg_errors.1688576061
/workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/cover_reg_top/14.flash_ctrl_shadow_reg_errors_with_csr_rw.2020102700
/workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/cover_reg_top/14.flash_ctrl_tl_errors.2239360963
/workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/cover_reg_top/14.flash_ctrl_tl_intg_err.3354587161
/workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/cover_reg_top/15.flash_ctrl_csr_mem_rw_with_rand_reset.876632969
/workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/cover_reg_top/15.flash_ctrl_csr_rw.1377455028
/workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/cover_reg_top/15.flash_ctrl_same_csr_outstanding.1385177357
/workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/cover_reg_top/15.flash_ctrl_shadow_reg_errors.3836170336
/workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/cover_reg_top/15.flash_ctrl_shadow_reg_errors_with_csr_rw.3367444625
/workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/cover_reg_top/15.flash_ctrl_tl_errors.1100528691
/workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/cover_reg_top/16.flash_ctrl_csr_mem_rw_with_rand_reset.3792650064
/workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/cover_reg_top/16.flash_ctrl_csr_rw.782150716
/workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/cover_reg_top/16.flash_ctrl_intr_test.1576129146
/workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/cover_reg_top/16.flash_ctrl_same_csr_outstanding.2460814603
/workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/cover_reg_top/16.flash_ctrl_shadow_reg_errors.4165171287
/workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/cover_reg_top/16.flash_ctrl_shadow_reg_errors_with_csr_rw.2817881557
/workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/cover_reg_top/16.flash_ctrl_tl_intg_err.81193823
/workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/cover_reg_top/17.flash_ctrl_csr_mem_rw_with_rand_reset.3895434091
/workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/cover_reg_top/17.flash_ctrl_csr_rw.1152888181
/workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/cover_reg_top/17.flash_ctrl_intr_test.1772966868
/workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/cover_reg_top/17.flash_ctrl_same_csr_outstanding.2153891784
/workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/cover_reg_top/17.flash_ctrl_shadow_reg_errors.2875074380
/workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/cover_reg_top/17.flash_ctrl_shadow_reg_errors_with_csr_rw.2440556494
/workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/cover_reg_top/17.flash_ctrl_tl_errors.500951300
/workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/cover_reg_top/17.flash_ctrl_tl_intg_err.3787215812
/workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/cover_reg_top/18.flash_ctrl_csr_mem_rw_with_rand_reset.179570331
/workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/cover_reg_top/18.flash_ctrl_csr_rw.2517111346
/workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/cover_reg_top/18.flash_ctrl_intr_test.1493088256
/workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/cover_reg_top/18.flash_ctrl_same_csr_outstanding.148621790
/workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/cover_reg_top/18.flash_ctrl_shadow_reg_errors.110655735
/workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/cover_reg_top/18.flash_ctrl_shadow_reg_errors_with_csr_rw.3700140187
/workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/cover_reg_top/18.flash_ctrl_tl_errors.3048465211
/workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/cover_reg_top/19.flash_ctrl_csr_mem_rw_with_rand_reset.637075127
/workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/cover_reg_top/19.flash_ctrl_csr_rw.1565431472
/workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/cover_reg_top/19.flash_ctrl_intr_test.2740461148
/workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/cover_reg_top/19.flash_ctrl_same_csr_outstanding.1631714421
/workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/cover_reg_top/19.flash_ctrl_shadow_reg_errors.2292540125
/workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/cover_reg_top/19.flash_ctrl_shadow_reg_errors_with_csr_rw.2982636488
/workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/cover_reg_top/19.flash_ctrl_tl_errors.2926029189
/workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/cover_reg_top/19.flash_ctrl_tl_intg_err.525827642
/workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/cover_reg_top/2.flash_ctrl_csr_aliasing.32172055
/workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/cover_reg_top/2.flash_ctrl_csr_bit_bash.2147010019
/workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/cover_reg_top/2.flash_ctrl_csr_hw_reset.1144189584
/workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/cover_reg_top/2.flash_ctrl_csr_mem_rw_with_rand_reset.4077841063
/workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/cover_reg_top/2.flash_ctrl_csr_rw.1094094184
/workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/cover_reg_top/2.flash_ctrl_intr_test.1554701921
/workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/cover_reg_top/2.flash_ctrl_mem_walk.3629713433
/workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/cover_reg_top/2.flash_ctrl_same_csr_outstanding.1303751097
/workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/cover_reg_top/2.flash_ctrl_shadow_reg_errors.4132266172
/workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/cover_reg_top/2.flash_ctrl_shadow_reg_errors_with_csr_rw.2307416966
/workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/cover_reg_top/2.flash_ctrl_tl_errors.2381453683
/workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/cover_reg_top/2.flash_ctrl_tl_intg_err.2628875100
/workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/cover_reg_top/20.flash_ctrl_intr_test.1709798540
/workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/cover_reg_top/21.flash_ctrl_intr_test.1623960270
/workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/cover_reg_top/22.flash_ctrl_intr_test.2576642467
/workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/cover_reg_top/23.flash_ctrl_intr_test.2643963984
/workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/cover_reg_top/24.flash_ctrl_intr_test.1264528824
/workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/cover_reg_top/25.flash_ctrl_intr_test.2160135327
/workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/cover_reg_top/26.flash_ctrl_intr_test.37753002
/workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/cover_reg_top/27.flash_ctrl_intr_test.1920435258
/workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/cover_reg_top/28.flash_ctrl_intr_test.3095606709
/workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/cover_reg_top/29.flash_ctrl_intr_test.996812166
/workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/cover_reg_top/3.flash_ctrl_csr_aliasing.2855094441
/workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/cover_reg_top/3.flash_ctrl_csr_bit_bash.171681327
/workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/cover_reg_top/3.flash_ctrl_csr_hw_reset.2391256190
/workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/cover_reg_top/3.flash_ctrl_csr_mem_rw_with_rand_reset.1212236792
/workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/cover_reg_top/3.flash_ctrl_csr_rw.2817523686
/workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/cover_reg_top/3.flash_ctrl_intr_test.2070942315
/workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/cover_reg_top/3.flash_ctrl_mem_partial_access.534475474
/workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/cover_reg_top/3.flash_ctrl_mem_walk.1332096789
/workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/cover_reg_top/3.flash_ctrl_same_csr_outstanding.4110605019
/workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/cover_reg_top/3.flash_ctrl_shadow_reg_errors.3972067917
/workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/cover_reg_top/3.flash_ctrl_shadow_reg_errors_with_csr_rw.2395400691
/workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/cover_reg_top/3.flash_ctrl_tl_intg_err.3777333796
/workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/cover_reg_top/30.flash_ctrl_intr_test.1587752824
/workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/cover_reg_top/31.flash_ctrl_intr_test.2571043532
/workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/cover_reg_top/32.flash_ctrl_intr_test.687371573
/workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/cover_reg_top/33.flash_ctrl_intr_test.1915870717
/workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/cover_reg_top/34.flash_ctrl_intr_test.2734308269
/workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/cover_reg_top/35.flash_ctrl_intr_test.2905720762
/workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/cover_reg_top/36.flash_ctrl_intr_test.957837461
/workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/cover_reg_top/37.flash_ctrl_intr_test.2987715070
/workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/cover_reg_top/38.flash_ctrl_intr_test.1752921189
/workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/cover_reg_top/39.flash_ctrl_intr_test.1983998195
/workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/cover_reg_top/4.flash_ctrl_csr_aliasing.3360854568
/workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/cover_reg_top/4.flash_ctrl_csr_bit_bash.1688017482
/workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/cover_reg_top/4.flash_ctrl_csr_hw_reset.1763495433
/workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/cover_reg_top/4.flash_ctrl_csr_mem_rw_with_rand_reset.3953646449
/workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/cover_reg_top/4.flash_ctrl_csr_rw.2204462477
/workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/cover_reg_top/4.flash_ctrl_intr_test.221794680
/workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/cover_reg_top/4.flash_ctrl_mem_partial_access.1915518937
/workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/cover_reg_top/4.flash_ctrl_mem_walk.3552954418
/workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/cover_reg_top/4.flash_ctrl_same_csr_outstanding.2793307766
/workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/cover_reg_top/4.flash_ctrl_shadow_reg_errors.3423303255
/workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/cover_reg_top/4.flash_ctrl_shadow_reg_errors_with_csr_rw.3629020459
/workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/cover_reg_top/4.flash_ctrl_tl_intg_err.3896772948
/workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/cover_reg_top/40.flash_ctrl_intr_test.647585063
/workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/cover_reg_top/41.flash_ctrl_intr_test.2945730601
/workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/cover_reg_top/42.flash_ctrl_intr_test.2075093435
/workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/cover_reg_top/43.flash_ctrl_intr_test.3500533748
/workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/cover_reg_top/44.flash_ctrl_intr_test.54009979
/workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/cover_reg_top/45.flash_ctrl_intr_test.3949538627
/workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/cover_reg_top/46.flash_ctrl_intr_test.1052090107
/workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/cover_reg_top/47.flash_ctrl_intr_test.2646249567
/workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/cover_reg_top/48.flash_ctrl_intr_test.1896923140
/workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/cover_reg_top/49.flash_ctrl_intr_test.759927686
/workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/cover_reg_top/5.flash_ctrl_csr_mem_rw_with_rand_reset.679025548
/workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/cover_reg_top/5.flash_ctrl_csr_rw.107407463
/workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/cover_reg_top/5.flash_ctrl_intr_test.51551912
/workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/cover_reg_top/5.flash_ctrl_same_csr_outstanding.2232079820
/workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/cover_reg_top/5.flash_ctrl_shadow_reg_errors.4253435587
/workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/cover_reg_top/5.flash_ctrl_shadow_reg_errors_with_csr_rw.203753756
/workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/cover_reg_top/5.flash_ctrl_tl_errors.1404179010
/workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/cover_reg_top/5.flash_ctrl_tl_intg_err.2380994710
/workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/cover_reg_top/6.flash_ctrl_csr_rw.457092272
/workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/cover_reg_top/6.flash_ctrl_intr_test.1230069661
/workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/cover_reg_top/6.flash_ctrl_same_csr_outstanding.3307507537
/workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/cover_reg_top/6.flash_ctrl_shadow_reg_errors.3313981238
/workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/cover_reg_top/6.flash_ctrl_shadow_reg_errors_with_csr_rw.2444969514
/workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/cover_reg_top/6.flash_ctrl_tl_errors.2680993726
/workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/cover_reg_top/7.flash_ctrl_csr_mem_rw_with_rand_reset.3033899840
/workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/cover_reg_top/7.flash_ctrl_csr_rw.1220473187
/workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/cover_reg_top/7.flash_ctrl_same_csr_outstanding.2777609693
/workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/cover_reg_top/7.flash_ctrl_shadow_reg_errors.1296613144
/workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/cover_reg_top/7.flash_ctrl_shadow_reg_errors_with_csr_rw.879424189
/workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/cover_reg_top/7.flash_ctrl_tl_errors.885285102
/workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/cover_reg_top/7.flash_ctrl_tl_intg_err.2981638514
/workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/cover_reg_top/8.flash_ctrl_csr_mem_rw_with_rand_reset.2071597295
/workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/cover_reg_top/8.flash_ctrl_csr_rw.1712534942
/workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/cover_reg_top/8.flash_ctrl_intr_test.2312229664
/workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/cover_reg_top/8.flash_ctrl_same_csr_outstanding.1439615024
/workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/cover_reg_top/8.flash_ctrl_shadow_reg_errors.1595398716
/workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/cover_reg_top/8.flash_ctrl_shadow_reg_errors_with_csr_rw.1300180977
/workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/cover_reg_top/8.flash_ctrl_tl_errors.930496597
/workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/cover_reg_top/8.flash_ctrl_tl_intg_err.429975817
/workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/cover_reg_top/9.flash_ctrl_csr_mem_rw_with_rand_reset.783079651
/workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/cover_reg_top/9.flash_ctrl_csr_rw.4215715390
/workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/cover_reg_top/9.flash_ctrl_intr_test.2320424793
/workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/cover_reg_top/9.flash_ctrl_same_csr_outstanding.2196968061
/workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/cover_reg_top/9.flash_ctrl_shadow_reg_errors.2814974810
/workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/cover_reg_top/9.flash_ctrl_shadow_reg_errors_with_csr_rw.2952766079
/workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/cover_reg_top/9.flash_ctrl_tl_errors.2648195023
/workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/0.flash_ctrl_connect.3985234731
/workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/0.flash_ctrl_derr_detect.3379159762
/workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/0.flash_ctrl_host_addr_infection.4209868870
/workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/0.flash_ctrl_host_ctrl_arb.1764126058
/workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/0.flash_ctrl_host_dir_rd.3969367004
/workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/0.flash_ctrl_hw_rma.529507818
/workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/0.flash_ctrl_hw_rma_reset.1805674723
/workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/0.flash_ctrl_integrity.2380296237
/workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/0.flash_ctrl_intr_rd.3284738176
/workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/0.flash_ctrl_intr_wr_slow_flash.281289929
/workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/0.flash_ctrl_lcmgr_intg.3327513843
/workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/0.flash_ctrl_otp_reset.2540871239
/workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/0.flash_ctrl_phy_arb.625269978
/workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/0.flash_ctrl_prog_reset.2313418965
/workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/0.flash_ctrl_rand_ops.2611036791
/workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/0.flash_ctrl_rd_ooo.2222212677
/workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/0.flash_ctrl_read_word_sweep.1857817590
/workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/0.flash_ctrl_read_word_sweep_derr.398442348
/workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/0.flash_ctrl_read_word_sweep_serr.4102734495
/workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/0.flash_ctrl_ro.176654613
/workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/0.flash_ctrl_ro_derr.3009225734
/workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/0.flash_ctrl_ro_serr.3116835678
/workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/0.flash_ctrl_rw_evict_all_en.53519437
/workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/0.flash_ctrl_sec_cm.2867594089
/workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/0.flash_ctrl_serr_counter.475596563
/workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/0.flash_ctrl_smoke.4031768799
/workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/0.flash_ctrl_smoke_hw.3391579057
/workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/0.flash_ctrl_stress_all.2322899116
/workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/0.flash_ctrl_sw_op.122455886
/workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/0.flash_ctrl_wo.578038009
/workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/0.flash_ctrl_write_word_sweep.2937732399
/workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/1.flash_ctrl_access_after_disable.1507516686
/workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/1.flash_ctrl_alert_test.744134193
/workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/1.flash_ctrl_config_regwen.362808816
/workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/1.flash_ctrl_connect.2079753966
/workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/1.flash_ctrl_derr_detect.487065119
/workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/1.flash_ctrl_disable.390741902
/workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/1.flash_ctrl_erase_suspend.3331916889
/workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/1.flash_ctrl_error_mp.688262517
/workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/1.flash_ctrl_error_prog_win.31844294
/workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/1.flash_ctrl_fs_sup.3708602680
/workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/1.flash_ctrl_full_mem_access.4280648156
/workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/1.flash_ctrl_host_addr_infection.2146105188
/workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/1.flash_ctrl_host_ctrl_arb.2760592695
/workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/1.flash_ctrl_host_dir_rd.4118212858
/workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/1.flash_ctrl_hw_read_seed_err.3849782107
/workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/1.flash_ctrl_hw_rma_reset.2363643674
/workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/1.flash_ctrl_hw_sec_otp.3272686431
/workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/1.flash_ctrl_integrity.2252446038
/workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/1.flash_ctrl_intr_rd.2945997567
/workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/1.flash_ctrl_intr_rd_slow_flash.349308498
/workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/1.flash_ctrl_intr_wr.349474850
/workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/1.flash_ctrl_intr_wr_slow_flash.3633403629
/workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/1.flash_ctrl_invalid_op.9356920
/workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/1.flash_ctrl_lcmgr_intg.3230020156
/workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/1.flash_ctrl_oversize_error.536616134
/workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/1.flash_ctrl_phy_arb.1646147595
/workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/1.flash_ctrl_phy_arb_redun.3804903680
/workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/1.flash_ctrl_phy_host_grant_err.2467173467
/workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/1.flash_ctrl_prog_reset.185194169
/workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/1.flash_ctrl_rand_ops.3730941250
/workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/1.flash_ctrl_rd_intg.2351148993
/workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/1.flash_ctrl_re_evict.935544876
/workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/1.flash_ctrl_read_word_sweep_derr.1283790033
/workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/1.flash_ctrl_read_word_sweep_serr.3496306376
/workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/1.flash_ctrl_rma_err.3875281456
/workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/1.flash_ctrl_ro.3093025309
/workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/1.flash_ctrl_ro_derr.515646628
/workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/1.flash_ctrl_ro_serr.3667811319
/workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/1.flash_ctrl_rw.312943239
/workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/1.flash_ctrl_rw_derr.2636250387
/workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/1.flash_ctrl_rw_evict_all_en.2175339349
/workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/1.flash_ctrl_rw_serr.2723204012
/workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/1.flash_ctrl_serr_address.1597725250
/workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/1.flash_ctrl_serr_counter.3353137793
/workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/1.flash_ctrl_smoke.823098157
/workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/1.flash_ctrl_smoke_hw.4159348001
/workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/1.flash_ctrl_stress_all.177448704
/workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/1.flash_ctrl_sw_op.2392205847
/workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/1.flash_ctrl_wo.564847151
/workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/10.flash_ctrl_alert_test.89266959
/workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/10.flash_ctrl_connect.214540982
/workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/10.flash_ctrl_disable.292206915
/workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/10.flash_ctrl_hw_prog_rma_wipe_err.2159518389
/workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/10.flash_ctrl_hw_read_seed_err.3418050044
/workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/10.flash_ctrl_hw_rma_reset.871702408
/workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/10.flash_ctrl_hw_sec_otp.480142472
/workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/10.flash_ctrl_intr_rd.32419988
/workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/10.flash_ctrl_intr_rd_slow_flash.3095114339
/workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/10.flash_ctrl_invalid_op.1225011795
/workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/10.flash_ctrl_lcmgr_intg.513761573
/workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/10.flash_ctrl_mp_regions.881135421
/workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/10.flash_ctrl_otp_reset.1188696459
/workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/10.flash_ctrl_phy_arb.2425293284
/workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/10.flash_ctrl_prog_reset.1966197732
/workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/10.flash_ctrl_rand_ops.3984049661
/workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/10.flash_ctrl_re_evict.262075243
/workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/10.flash_ctrl_ro.131846103
/workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/10.flash_ctrl_rw_evict.2309458158
/workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/10.flash_ctrl_rw_evict_all_en.2747681995
/workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/10.flash_ctrl_smoke.4194894572
/workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/10.flash_ctrl_wo.2594823845
/workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/11.flash_ctrl_alert_test.516942472
/workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/11.flash_ctrl_connect.2771754652
/workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/11.flash_ctrl_disable.4217699176
/workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/11.flash_ctrl_hw_rma_reset.3657113540
/workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/11.flash_ctrl_hw_sec_otp.2689500118
/workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/11.flash_ctrl_intr_rd.1411103907
/workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/11.flash_ctrl_intr_rd_slow_flash.774885624
/workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/11.flash_ctrl_invalid_op.1746084873
/workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/11.flash_ctrl_lcmgr_intg.1156420201
/workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/11.flash_ctrl_mp_regions.3700876681
/workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/11.flash_ctrl_otp_reset.3149863273
/workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/11.flash_ctrl_phy_arb.2844475892
/workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/11.flash_ctrl_prog_reset.37721980
/workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/11.flash_ctrl_rand_ops.841895920
/workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/11.flash_ctrl_re_evict.3174911007
/workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/11.flash_ctrl_ro.2575722396
/workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/11.flash_ctrl_rw.4238621024
/workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/11.flash_ctrl_rw_evict.1644841636
/workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/11.flash_ctrl_smoke.135472797
/workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/11.flash_ctrl_wo.2729522148
/workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/12.flash_ctrl_alert_test.1975905596
/workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/12.flash_ctrl_connect.1028799862
/workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/12.flash_ctrl_hw_prog_rma_wipe_err.2766714525
/workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/12.flash_ctrl_hw_read_seed_err.437832481
/workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/12.flash_ctrl_hw_rma_reset.4126689830
/workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/12.flash_ctrl_hw_sec_otp.3189360610
/workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/12.flash_ctrl_intr_rd.503748849
/workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/12.flash_ctrl_intr_rd_slow_flash.3568331904
/workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/12.flash_ctrl_invalid_op.502522743
/workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/12.flash_ctrl_lcmgr_intg.1669092229
/workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/12.flash_ctrl_mp_regions.764502893
/workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/12.flash_ctrl_otp_reset.3537578557
/workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/12.flash_ctrl_phy_arb.405421377
/workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/12.flash_ctrl_prog_reset.2269441818
/workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/12.flash_ctrl_rand_ops.3631509776
/workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/12.flash_ctrl_re_evict.2160015562
/workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/12.flash_ctrl_ro.4018302626
/workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/12.flash_ctrl_rw.2812350274
/workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/12.flash_ctrl_rw_evict.687474242
/workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/12.flash_ctrl_rw_evict_all_en.54420773
/workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/12.flash_ctrl_sec_info_access.3843925604
/workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/12.flash_ctrl_smoke.2952463781
/workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/12.flash_ctrl_wo.1480831783
/workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/13.flash_ctrl_alert_test.2319041482
/workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/13.flash_ctrl_connect.1499152575
/workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/13.flash_ctrl_disable.2146091925
/workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/13.flash_ctrl_hw_prog_rma_wipe_err.2828521271
/workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/13.flash_ctrl_hw_read_seed_err.3819937357
/workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/13.flash_ctrl_hw_rma_reset.1832684410
/workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/13.flash_ctrl_hw_sec_otp.3456460940
/workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/13.flash_ctrl_intr_rd.1472193754
/workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/13.flash_ctrl_intr_rd_slow_flash.3072027910
/workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/13.flash_ctrl_invalid_op.3529640086
/workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/13.flash_ctrl_lcmgr_intg.4100099072
/workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/13.flash_ctrl_mp_regions.3021719410
/workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/13.flash_ctrl_otp_reset.987163297
/workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/13.flash_ctrl_phy_arb.1557454812
/workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/13.flash_ctrl_prog_reset.3115395298
/workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/13.flash_ctrl_rand_ops.3487656320
/workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/13.flash_ctrl_re_evict.474811414
/workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/13.flash_ctrl_ro.1489698672
/workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/13.flash_ctrl_rw.2998436154
/workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/13.flash_ctrl_rw_evict.1751802011
/workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/13.flash_ctrl_rw_evict_all_en.831292486
/workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/13.flash_ctrl_sec_info_access.3220787310
/workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/13.flash_ctrl_smoke.1660197431
/workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/13.flash_ctrl_wo.3183948033
/workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/14.flash_ctrl_alert_test.3238993792
/workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/14.flash_ctrl_connect.28851525
/workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/14.flash_ctrl_disable.1335836712
/workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/14.flash_ctrl_hw_prog_rma_wipe_err.1929875841
/workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/14.flash_ctrl_hw_read_seed_err.2117219284
/workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/14.flash_ctrl_hw_rma_reset.3253705782
/workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/14.flash_ctrl_hw_sec_otp.2935343802
/workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/14.flash_ctrl_intr_rd.130038154
/workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/14.flash_ctrl_intr_rd_slow_flash.3937717095
/workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/14.flash_ctrl_invalid_op.988441047
/workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/14.flash_ctrl_lcmgr_intg.259821092
/workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/14.flash_ctrl_mp_regions.1976218844
/workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/14.flash_ctrl_otp_reset.1363806648
/workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/14.flash_ctrl_phy_arb.2444462209
/workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/14.flash_ctrl_prog_reset.1301797100
/workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/14.flash_ctrl_rand_ops.3770079992
/workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/14.flash_ctrl_re_evict.692186394
/workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/14.flash_ctrl_ro.1945341999
/workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/14.flash_ctrl_rw.4177583904
/workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/14.flash_ctrl_rw_evict.2643932130
/workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/14.flash_ctrl_rw_evict_all_en.1597677716
/workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/14.flash_ctrl_smoke.1275473654
/workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/14.flash_ctrl_wo.3124429033
/workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/15.flash_ctrl_alert_test.1033795459
/workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/15.flash_ctrl_connect.3992887062
/workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/15.flash_ctrl_hw_prog_rma_wipe_err.4192612153
/workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/15.flash_ctrl_hw_read_seed_err.3601165341
/workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/15.flash_ctrl_hw_rma_reset.4275108245
/workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/15.flash_ctrl_hw_sec_otp.1875924696
/workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/15.flash_ctrl_intr_rd.734641676
/workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/15.flash_ctrl_invalid_op.1264888385
/workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/15.flash_ctrl_lcmgr_intg.1566776690
/workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/15.flash_ctrl_mp_regions.700666415
/workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/15.flash_ctrl_otp_reset.936837964
/workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/15.flash_ctrl_phy_arb.2539814953
/workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/15.flash_ctrl_prog_reset.3747928728
/workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/15.flash_ctrl_rand_ops.2373711377
/workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/15.flash_ctrl_re_evict.2041653274
/workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/15.flash_ctrl_ro.3600264784
/workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/15.flash_ctrl_rw.4092938719
/workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/15.flash_ctrl_rw_evict.3380607213
/workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/15.flash_ctrl_rw_evict_all_en.452387213
/workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/15.flash_ctrl_sec_info_access.3940134684
/workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/15.flash_ctrl_smoke.3975966678
/workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/15.flash_ctrl_wo.1050864090
/workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/16.flash_ctrl_alert_test.4283042162
/workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/16.flash_ctrl_connect.4096693120
/workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/16.flash_ctrl_disable.4161165495
/workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/16.flash_ctrl_hw_prog_rma_wipe_err.4087509667
/workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/16.flash_ctrl_hw_read_seed_err.2261312658
/workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/16.flash_ctrl_hw_rma_reset.3910103317
/workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/16.flash_ctrl_intr_rd.1741968709
/workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/16.flash_ctrl_intr_rd_slow_flash.3562556841
/workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/16.flash_ctrl_invalid_op.3860142540
/workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/16.flash_ctrl_lcmgr_intg.1333261099
/workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/16.flash_ctrl_mp_regions.1345529245
/workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/16.flash_ctrl_otp_reset.2341295648
/workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/16.flash_ctrl_phy_arb.2160728956
/workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/16.flash_ctrl_prog_reset.3198617153
/workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/16.flash_ctrl_rand_ops.1989399766
/workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/16.flash_ctrl_re_evict.3848944310
/workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/16.flash_ctrl_ro.3971446420
/workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/16.flash_ctrl_rw.1569377633
/workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/16.flash_ctrl_rw_evict.1271541667
/workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/16.flash_ctrl_rw_evict_all_en.3361451694
/workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/16.flash_ctrl_sec_info_access.3869377861
/workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/16.flash_ctrl_smoke.4201472561
/workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/16.flash_ctrl_wo.3255917959
/workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/17.flash_ctrl_alert_test.2647138140
/workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/17.flash_ctrl_connect.2681059625
/workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/17.flash_ctrl_hw_prog_rma_wipe_err.3877690011
/workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/17.flash_ctrl_hw_read_seed_err.4782939
/workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/17.flash_ctrl_hw_rma_reset.2394736001
/workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/17.flash_ctrl_hw_sec_otp.585874212
/workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/17.flash_ctrl_intr_rd.1734563691
/workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/17.flash_ctrl_intr_rd_slow_flash.2205865072
/workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/17.flash_ctrl_invalid_op.1515131470
/workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/17.flash_ctrl_lcmgr_intg.804765876
/workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/17.flash_ctrl_mp_regions.3983704005
/workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/17.flash_ctrl_otp_reset.1028388271
/workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/17.flash_ctrl_phy_arb.2004295225
/workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/17.flash_ctrl_prog_reset.1001962077
/workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/17.flash_ctrl_rand_ops.2867396814
/workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/17.flash_ctrl_re_evict.2566585227
/workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/17.flash_ctrl_ro.3802820173
/workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/17.flash_ctrl_rw.1363741229
/workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/17.flash_ctrl_rw_evict_all_en.449129580
/workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/17.flash_ctrl_sec_info_access.4280837774
/workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/17.flash_ctrl_smoke.3993198529
/workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/17.flash_ctrl_wo.277548379
/workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/18.flash_ctrl_alert_test.3126570512
/workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/18.flash_ctrl_connect.1064734097
/workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/18.flash_ctrl_disable.1694354698
/workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/18.flash_ctrl_hw_prog_rma_wipe_err.1704858117
/workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/18.flash_ctrl_hw_read_seed_err.3283201947
/workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/18.flash_ctrl_hw_rma_reset.148096331
/workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/18.flash_ctrl_hw_sec_otp.910900822
/workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/18.flash_ctrl_intr_rd.4238767809
/workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/18.flash_ctrl_intr_rd_slow_flash.4106600101
/workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/18.flash_ctrl_invalid_op.385109753
/workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/18.flash_ctrl_lcmgr_intg.1209389595
/workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/18.flash_ctrl_mp_regions.797494618
/workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/18.flash_ctrl_phy_arb.3732584553
/workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/18.flash_ctrl_prog_reset.3993969940
/workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/18.flash_ctrl_rand_ops.150658383
/workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/18.flash_ctrl_re_evict.423304523
/workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/18.flash_ctrl_ro.464781944
/workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/18.flash_ctrl_rw.2574018814
/workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/18.flash_ctrl_rw_evict.1590793942
/workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/18.flash_ctrl_rw_evict_all_en.2462772387
/workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/18.flash_ctrl_sec_info_access.4226518216
/workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/18.flash_ctrl_smoke.2606362728
/workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/18.flash_ctrl_wo.3696576997
/workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/19.flash_ctrl_alert_test.1296538512
/workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/19.flash_ctrl_connect.523232284
/workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/19.flash_ctrl_hw_prog_rma_wipe_err.2493395213
/workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/19.flash_ctrl_hw_read_seed_err.1268856243
/workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/19.flash_ctrl_hw_sec_otp.966888809
/workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/19.flash_ctrl_intr_rd.1124269741
/workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/19.flash_ctrl_intr_rd_slow_flash.792058028
/workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/19.flash_ctrl_invalid_op.448339165
/workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/19.flash_ctrl_lcmgr_intg.3527228012
/workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/19.flash_ctrl_mp_regions.838351725
/workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/19.flash_ctrl_otp_reset.1508362157
/workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/19.flash_ctrl_phy_arb.2090217066
/workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/19.flash_ctrl_rand_ops.1000333822
/workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/19.flash_ctrl_re_evict.4205336616
/workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/19.flash_ctrl_ro.1098804656
/workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/19.flash_ctrl_rw.3221510094
/workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/19.flash_ctrl_rw_evict.688651550
/workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/19.flash_ctrl_rw_evict_all_en.440390972
/workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/19.flash_ctrl_sec_info_access.2865093595
/workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/19.flash_ctrl_smoke.3437606069
/workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/19.flash_ctrl_wo.1521945463
/workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/2.flash_ctrl_access_after_disable.4280399723
/workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/2.flash_ctrl_alert_test.540518097
/workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/2.flash_ctrl_config_regwen.3087455357
/workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/2.flash_ctrl_connect.4259215925
/workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/2.flash_ctrl_derr_detect.227495958
/workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/2.flash_ctrl_disable.3817247549
/workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/2.flash_ctrl_erase_suspend.980328821
/workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/2.flash_ctrl_error_mp.3437444714
/workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/2.flash_ctrl_error_prog_type.3330095429
/workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/2.flash_ctrl_error_prog_win.55109980
/workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/2.flash_ctrl_fetch_code.8342506
/workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/2.flash_ctrl_fs_sup.4065995921
/workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/2.flash_ctrl_full_mem_access.3285640424
/workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/2.flash_ctrl_host_addr_infection.3782333650
/workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/2.flash_ctrl_host_dir_rd.4064335948
/workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/2.flash_ctrl_hw_prog_rma_wipe_err.368733333
/workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/2.flash_ctrl_hw_read_seed_err.3068778074
/workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/2.flash_ctrl_hw_rma.1052345208
/workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/2.flash_ctrl_hw_rma_reset.3315702952
/workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/2.flash_ctrl_hw_sec_otp.2718849348
/workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/2.flash_ctrl_integrity.525307942
/workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/2.flash_ctrl_intr_rd_slow_flash.3391729979
/workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/2.flash_ctrl_intr_wr.2113429812
/workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/2.flash_ctrl_intr_wr_slow_flash.1244170991
/workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/2.flash_ctrl_invalid_op.3527823580
/workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/2.flash_ctrl_lcmgr_intg.3550011449
/workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/2.flash_ctrl_mid_op_rst.453480753
/workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/2.flash_ctrl_mp_regions.3546643645
/workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/2.flash_ctrl_otp_reset.517451295
/workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/2.flash_ctrl_oversize_error.3950700824
/workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/2.flash_ctrl_phy_ack_consistency.2160378239
/workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/2.flash_ctrl_phy_arb.1014943127
/workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/2.flash_ctrl_prog_reset.3004476445
/workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/2.flash_ctrl_rand_ops.1774167167
/workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/2.flash_ctrl_rd_buff_evict.1438490607
/workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/2.flash_ctrl_rd_intg.3436437161
/workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/2.flash_ctrl_re_evict.3106270190
/workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/2.flash_ctrl_read_word_sweep_derr.2659766682
/workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/2.flash_ctrl_read_word_sweep_serr.3747994986
/workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/2.flash_ctrl_rma_err.2258963418
/workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/2.flash_ctrl_ro.217989448
/workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/2.flash_ctrl_ro_derr.2607758581
/workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/2.flash_ctrl_ro_serr.2371403695
/workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/2.flash_ctrl_rw.1348398604
/workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/2.flash_ctrl_rw_evict.10237805
/workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/2.flash_ctrl_rw_evict_all_en.2182496236
/workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/2.flash_ctrl_rw_serr.3332433741
/workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/2.flash_ctrl_sec_info_access.4178193890
/workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/2.flash_ctrl_serr_address.1579818407
/workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/2.flash_ctrl_serr_counter.3059533894
/workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/2.flash_ctrl_smoke.668741884
/workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/2.flash_ctrl_smoke_hw.1572623676
/workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/2.flash_ctrl_stress_all.574222222
/workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/2.flash_ctrl_sw_op.349387670
/workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/2.flash_ctrl_wo.1105906448
/workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/2.flash_ctrl_wr_intg.3011161323
/workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/20.flash_ctrl_alert_test.764525307
/workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/20.flash_ctrl_connect.713922335
/workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/20.flash_ctrl_disable.1790071999
/workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/20.flash_ctrl_hw_sec_otp.345069187
/workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/20.flash_ctrl_intr_rd.1516335510
/workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/20.flash_ctrl_intr_rd_slow_flash.2797814222
/workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/20.flash_ctrl_otp_reset.1491237641
/workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/20.flash_ctrl_prog_reset.2699390747
/workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/20.flash_ctrl_rw_evict.2915399455
/workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/20.flash_ctrl_sec_info_access.2204296001
/workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/20.flash_ctrl_smoke.3800202171
/workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/21.flash_ctrl_alert_test.4211590052
/workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/21.flash_ctrl_connect.3257739665
/workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/21.flash_ctrl_disable.1607969094
/workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/21.flash_ctrl_hw_sec_otp.3809949883
/workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/21.flash_ctrl_intr_rd.2535346049
/workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/21.flash_ctrl_intr_rd_slow_flash.889672268
/workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/21.flash_ctrl_otp_reset.2833690423
/workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/21.flash_ctrl_prog_reset.2000411376
/workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/21.flash_ctrl_rw_evict.1119091590
/workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/21.flash_ctrl_rw_evict_all_en.3501317576
/workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/21.flash_ctrl_sec_info_access.413342313
/workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/21.flash_ctrl_smoke.3891246746
/workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/22.flash_ctrl_alert_test.3671820359
/workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/22.flash_ctrl_connect.4223084901
/workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/22.flash_ctrl_hw_sec_otp.4002043462
/workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/22.flash_ctrl_intr_rd.4197057316
/workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/22.flash_ctrl_intr_rd_slow_flash.3938537779
/workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/22.flash_ctrl_otp_reset.1904818378
/workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/22.flash_ctrl_prog_reset.3113639395
/workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/22.flash_ctrl_rw_evict.2241261867
/workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/22.flash_ctrl_rw_evict_all_en.3222002842
/workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/22.flash_ctrl_smoke.1721932290
/workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/23.flash_ctrl_alert_test.536793393
/workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/23.flash_ctrl_connect.1810389933
/workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/23.flash_ctrl_disable.2343420592
/workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/23.flash_ctrl_hw_sec_otp.2728364517
/workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/23.flash_ctrl_intr_rd.3348663455
/workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/23.flash_ctrl_intr_rd_slow_flash.3264660998
/workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/23.flash_ctrl_otp_reset.1742658244
/workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/23.flash_ctrl_prog_reset.1944249518
/workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/23.flash_ctrl_rw_evict.3928448543
/workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/23.flash_ctrl_rw_evict_all_en.1779756305
/workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/23.flash_ctrl_sec_info_access.1932287064
/workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/23.flash_ctrl_smoke.833092773
/workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/24.flash_ctrl_alert_test.733154617
/workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/24.flash_ctrl_connect.3302559852
/workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/24.flash_ctrl_disable.309404890
/workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/24.flash_ctrl_hw_sec_otp.51183767
/workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/24.flash_ctrl_intr_rd.402833925
/workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/24.flash_ctrl_intr_rd_slow_flash.2303164743
/workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/24.flash_ctrl_otp_reset.1413573047
/workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/24.flash_ctrl_prog_reset.191877063
/workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/24.flash_ctrl_rw_evict.2544324587
/workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/24.flash_ctrl_rw_evict_all_en.607733795
/workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/24.flash_ctrl_sec_info_access.15885717
/workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/24.flash_ctrl_smoke.757937570
/workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/25.flash_ctrl_alert_test.3427262357
/workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/25.flash_ctrl_connect.3886165261
/workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/25.flash_ctrl_disable.481149815
/workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/25.flash_ctrl_hw_sec_otp.3837745363
/workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/25.flash_ctrl_intr_rd.3862983643
/workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/25.flash_ctrl_intr_rd_slow_flash.3245871403
/workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/25.flash_ctrl_otp_reset.1175051604
/workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/25.flash_ctrl_prog_reset.479844190
/workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/25.flash_ctrl_rw_evict.2309714103
/workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/25.flash_ctrl_rw_evict_all_en.2588938211
/workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/25.flash_ctrl_smoke.3704687120
/workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/26.flash_ctrl_alert_test.3395055783
/workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/26.flash_ctrl_connect.1268983047
/workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/26.flash_ctrl_disable.785035916
/workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/26.flash_ctrl_hw_sec_otp.2063728000
/workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/26.flash_ctrl_intr_rd.2025708128
/workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/26.flash_ctrl_intr_rd_slow_flash.219734843
/workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/26.flash_ctrl_otp_reset.1314930742
/workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/26.flash_ctrl_prog_reset.343361794
/workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/26.flash_ctrl_rw_evict.2889031946
/workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/26.flash_ctrl_rw_evict_all_en.3537885113
/workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/26.flash_ctrl_sec_info_access.2672130371
/workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/26.flash_ctrl_smoke.976630070
/workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/27.flash_ctrl_alert_test.3045434811
/workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/27.flash_ctrl_connect.3294014484
/workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/27.flash_ctrl_disable.673835041
/workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/27.flash_ctrl_hw_sec_otp.2979758211
/workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/27.flash_ctrl_intr_rd.2430348645
/workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/27.flash_ctrl_intr_rd_slow_flash.4048865187
/workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/27.flash_ctrl_otp_reset.794306734
/workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/27.flash_ctrl_prog_reset.3320627409
/workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/27.flash_ctrl_rw_evict.2429017987
/workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/27.flash_ctrl_rw_evict_all_en.1792937394
/workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/27.flash_ctrl_sec_info_access.2928244573
/workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/27.flash_ctrl_smoke.1513313725
/workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/28.flash_ctrl_alert_test.3036209439
/workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/28.flash_ctrl_connect.4215577965
/workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/28.flash_ctrl_disable.2868181578
/workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/28.flash_ctrl_hw_sec_otp.4074253865
/workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/28.flash_ctrl_intr_rd.2092873080
/workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/28.flash_ctrl_intr_rd_slow_flash.3664284857
/workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/28.flash_ctrl_otp_reset.1498888526
/workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/28.flash_ctrl_prog_reset.4141400205
/workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/28.flash_ctrl_rw_evict_all_en.2287074268
/workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/28.flash_ctrl_sec_info_access.2565004045
/workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/28.flash_ctrl_smoke.2477161694
/workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/29.flash_ctrl_alert_test.1011235731
/workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/29.flash_ctrl_connect.2637549384
/workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/29.flash_ctrl_disable.2428719579
/workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/29.flash_ctrl_hw_sec_otp.2369510611
/workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/29.flash_ctrl_intr_rd.46518410
/workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/29.flash_ctrl_intr_rd_slow_flash.2627019914
/workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/29.flash_ctrl_otp_reset.3759202686
/workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/29.flash_ctrl_prog_reset.309174728
/workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/29.flash_ctrl_rw_evict_all_en.3623947007
/workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/29.flash_ctrl_sec_info_access.575938613
/workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/29.flash_ctrl_smoke.1421771327
/workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/3.flash_ctrl_alert_test.1081145347
/workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/3.flash_ctrl_config_regwen.2998106232
/workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/3.flash_ctrl_connect.1293842737
/workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/3.flash_ctrl_derr_detect.1473911461
/workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/3.flash_ctrl_disable.2579821172
/workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/3.flash_ctrl_erase_suspend.2731133218
/workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/3.flash_ctrl_error_mp.2767246538
/workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/3.flash_ctrl_error_prog_type.1030985590
/workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/3.flash_ctrl_error_prog_win.1009563373
/workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/3.flash_ctrl_fetch_code.4078620391
/workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/3.flash_ctrl_fs_sup.3121562705
/workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/3.flash_ctrl_full_mem_access.4125303451
/workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/3.flash_ctrl_host_ctrl_arb.384096946
/workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/3.flash_ctrl_host_dir_rd.338966361
/workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/3.flash_ctrl_hw_prog_rma_wipe_err.1108597414
/workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/3.flash_ctrl_hw_read_seed_err.673942228
/workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/3.flash_ctrl_hw_sec_otp.3416719421
/workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/3.flash_ctrl_integrity.2936939876
/workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/3.flash_ctrl_intr_rd.3008472121
/workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/3.flash_ctrl_intr_rd_slow_flash.1916443870
/workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/3.flash_ctrl_intr_wr.628792622
/workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/3.flash_ctrl_intr_wr_slow_flash.1495899356
/workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/3.flash_ctrl_invalid_op.2626607101
/workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/3.flash_ctrl_mp_regions.623204253
/workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/3.flash_ctrl_otp_reset.1217058996
/workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/3.flash_ctrl_oversize_error.344542370
/workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/3.flash_ctrl_phy_ack_consistency.3759564762
/workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/3.flash_ctrl_phy_arb.1065801612
/workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/3.flash_ctrl_phy_arb_redun.53379701
/workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/3.flash_ctrl_phy_host_grant_err.3369721351
/workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/3.flash_ctrl_prog_reset.2176212295
/workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/3.flash_ctrl_rand_ops.2194245487
/workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/3.flash_ctrl_rd_buff_evict.4053942498
/workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/3.flash_ctrl_re_evict.1032222686
/workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/3.flash_ctrl_read_word_sweep_derr.541499722
/workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/3.flash_ctrl_read_word_sweep_serr.1763173507
/workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/3.flash_ctrl_ro.2839985534
/workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/3.flash_ctrl_ro_derr.771905865
/workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/3.flash_ctrl_ro_serr.3578211100
/workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/3.flash_ctrl_rw.4115529894
/workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/3.flash_ctrl_rw_derr.1257503785
/workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/3.flash_ctrl_rw_evict.4054567647
/workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/3.flash_ctrl_rw_evict_all_en.2585055054
/workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/3.flash_ctrl_rw_serr.1014758437
/workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/3.flash_ctrl_sec_cm.934097974
/workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/3.flash_ctrl_sec_info_access.2005359666
/workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/3.flash_ctrl_serr_address.4000630452
/workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/3.flash_ctrl_serr_counter.1037467362
/workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/3.flash_ctrl_smoke.1283717430
/workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/3.flash_ctrl_smoke_hw.1652896163
/workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/3.flash_ctrl_stress_all.1797883173
/workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/3.flash_ctrl_sw_op.321912864
/workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/3.flash_ctrl_wo.1762558815
/workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/30.flash_ctrl_alert_test.31681734
/workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/30.flash_ctrl_connect.450510911
/workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/30.flash_ctrl_disable.297251356
/workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/30.flash_ctrl_hw_sec_otp.508199389
/workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/30.flash_ctrl_intr_rd.3110115443
/workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/30.flash_ctrl_intr_rd_slow_flash.3653058631
/workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/30.flash_ctrl_otp_reset.2646769394
/workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/30.flash_ctrl_rw_evict.1922887604
/workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/30.flash_ctrl_rw_evict_all_en.685672843
/workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/30.flash_ctrl_sec_info_access.1103560199
/workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/30.flash_ctrl_smoke.1838312213
/workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/31.flash_ctrl_alert_test.207915156
/workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/31.flash_ctrl_connect.1875853292
/workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/31.flash_ctrl_disable.1833510100
/workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/31.flash_ctrl_hw_sec_otp.2856703442
/workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/31.flash_ctrl_intr_rd.1419821318
/workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/31.flash_ctrl_intr_rd_slow_flash.2850633188
/workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/31.flash_ctrl_otp_reset.1034218800
/workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/31.flash_ctrl_rw_evict.3850261240
/workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/31.flash_ctrl_rw_evict_all_en.2073410123
/workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/31.flash_ctrl_sec_info_access.4035972720
/workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/31.flash_ctrl_smoke.1297647011
/workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/32.flash_ctrl_alert_test.3863203080
/workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/32.flash_ctrl_connect.1537313946
/workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/32.flash_ctrl_disable.3277067651
/workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/32.flash_ctrl_hw_sec_otp.2289337347
/workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/32.flash_ctrl_intr_rd.1868845398
/workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/32.flash_ctrl_intr_rd_slow_flash.2232237435
/workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/32.flash_ctrl_otp_reset.2651279154
/workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/32.flash_ctrl_rw_evict.2385615461
/workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/32.flash_ctrl_rw_evict_all_en.2536902562
/workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/32.flash_ctrl_sec_info_access.3385123734
/workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/32.flash_ctrl_smoke.615639494
/workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/33.flash_ctrl_alert_test.1009919211
/workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/33.flash_ctrl_connect.1753714165
/workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/33.flash_ctrl_disable.1299804558
/workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/33.flash_ctrl_hw_sec_otp.202532856
/workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/33.flash_ctrl_intr_rd.3511729207
/workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/33.flash_ctrl_intr_rd_slow_flash.1385347332
/workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/33.flash_ctrl_otp_reset.3774508020
/workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/33.flash_ctrl_rw_evict.2055979814
/workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/33.flash_ctrl_rw_evict_all_en.4046732062
/workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/33.flash_ctrl_sec_info_access.1497938030
/workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/33.flash_ctrl_smoke.969508874
/workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/34.flash_ctrl_alert_test.2275516388
/workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/34.flash_ctrl_connect.484812974
/workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/34.flash_ctrl_disable.4179639437
/workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/34.flash_ctrl_hw_sec_otp.688956779
/workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/34.flash_ctrl_intr_rd.1617908249
/workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/34.flash_ctrl_intr_rd_slow_flash.3547087860
/workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/34.flash_ctrl_otp_reset.2293702903
/workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/34.flash_ctrl_rw_evict.2326196590
/workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/34.flash_ctrl_rw_evict_all_en.2252902600
/workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/34.flash_ctrl_sec_info_access.652141189
/workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/34.flash_ctrl_smoke.1474278277
/workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/35.flash_ctrl_alert_test.1949298709
/workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/35.flash_ctrl_connect.1118591840
/workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/35.flash_ctrl_disable.4291686752
/workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/35.flash_ctrl_hw_sec_otp.3907462325
/workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/35.flash_ctrl_intr_rd.3399737108
/workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/35.flash_ctrl_intr_rd_slow_flash.54951579
/workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/35.flash_ctrl_otp_reset.4252100435
/workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/35.flash_ctrl_rw_evict.3770726384
/workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/35.flash_ctrl_rw_evict_all_en.3531976933
/workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/35.flash_ctrl_sec_info_access.2053298040
/workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/35.flash_ctrl_smoke.591582872
/workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/36.flash_ctrl_alert_test.608476467
/workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/36.flash_ctrl_connect.2655621720
/workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/36.flash_ctrl_disable.672868743
/workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/36.flash_ctrl_hw_sec_otp.705389028
/workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/36.flash_ctrl_intr_rd.1747172245
/workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/36.flash_ctrl_intr_rd_slow_flash.163035866
/workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/36.flash_ctrl_otp_reset.1003298997
/workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/36.flash_ctrl_rw_evict.2157640177
/workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/36.flash_ctrl_rw_evict_all_en.3362981028
/workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/36.flash_ctrl_sec_info_access.2615986418
/workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/36.flash_ctrl_smoke.1178516354
/workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/37.flash_ctrl_alert_test.4016387937
/workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/37.flash_ctrl_connect.3881514814
/workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/37.flash_ctrl_disable.2949449802
/workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/37.flash_ctrl_hw_sec_otp.2235955961
/workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/37.flash_ctrl_intr_rd.2549296558
/workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/37.flash_ctrl_intr_rd_slow_flash.676468618
/workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/37.flash_ctrl_otp_reset.186193188
/workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/37.flash_ctrl_rw_evict.667722221
/workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/37.flash_ctrl_rw_evict_all_en.816403075
/workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/37.flash_ctrl_sec_info_access.1797084739
/workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/37.flash_ctrl_smoke.1318999718
/workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/38.flash_ctrl_alert_test.3929910409
/workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/38.flash_ctrl_connect.3505538467
/workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/38.flash_ctrl_disable.549413128
/workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/38.flash_ctrl_hw_sec_otp.3890668828
/workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/38.flash_ctrl_intr_rd.3517487718
/workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/38.flash_ctrl_intr_rd_slow_flash.1125525548
/workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/38.flash_ctrl_otp_reset.3168864570
/workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/38.flash_ctrl_rw_evict.600526705
/workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/38.flash_ctrl_rw_evict_all_en.35346701
/workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/38.flash_ctrl_sec_info_access.2060412490
/workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/38.flash_ctrl_smoke.2476960825
/workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/39.flash_ctrl_alert_test.1151176958
/workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/39.flash_ctrl_connect.495683733
/workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/39.flash_ctrl_disable.2398516977
/workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/39.flash_ctrl_hw_sec_otp.860559159
/workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/39.flash_ctrl_intr_rd.3337982961
/workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/39.flash_ctrl_intr_rd_slow_flash.3543934146
/workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/39.flash_ctrl_otp_reset.634802658
/workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/39.flash_ctrl_rw_evict.397010356
/workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/39.flash_ctrl_rw_evict_all_en.925393427
/workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/39.flash_ctrl_sec_info_access.1133599756
/workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/39.flash_ctrl_smoke.2961169354
/workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/4.flash_ctrl_alert_test.2713898568
/workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/4.flash_ctrl_config_regwen.1214474081
/workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/4.flash_ctrl_connect.1772479535
/workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/4.flash_ctrl_derr_detect.3328679513
/workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/4.flash_ctrl_disable.3999616267
/workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/4.flash_ctrl_erase_suspend.1092185872
/workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/4.flash_ctrl_error_mp.1226461880
/workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/4.flash_ctrl_error_prog_win.3760339783
/workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/4.flash_ctrl_fetch_code.3589540089
/workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/4.flash_ctrl_full_mem_access.677185139
/workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/4.flash_ctrl_host_dir_rd.1592321932
/workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/4.flash_ctrl_hw_prog_rma_wipe_err.159110764
/workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/4.flash_ctrl_hw_read_seed_err.1222620753
/workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/4.flash_ctrl_hw_rma_reset.2696559880
/workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/4.flash_ctrl_hw_sec_otp.1357294376
/workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/4.flash_ctrl_integrity.602315595
/workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/4.flash_ctrl_intr_rd_slow_flash.1353395887
/workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/4.flash_ctrl_intr_wr.1378388805
/workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/4.flash_ctrl_intr_wr_slow_flash.1117612610
/workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/4.flash_ctrl_invalid_op.3602010185
/workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/4.flash_ctrl_lcmgr_intg.2586007530
/workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/4.flash_ctrl_mid_op_rst.3077782859
/workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/4.flash_ctrl_mp_regions.1295260571
/workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/4.flash_ctrl_otp_reset.1820466398
/workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/4.flash_ctrl_phy_arb.2349152661
/workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/4.flash_ctrl_prog_reset.2145828929
/workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/4.flash_ctrl_rand_ops.1861993747
/workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/4.flash_ctrl_rd_buff_evict.3464724584
/workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/4.flash_ctrl_re_evict.1303969858
/workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/4.flash_ctrl_read_word_sweep_derr.2348473879
/workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/4.flash_ctrl_read_word_sweep_serr.3286964051
/workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/4.flash_ctrl_ro.469065461
/workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/4.flash_ctrl_ro_serr.3161976382
/workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/4.flash_ctrl_rw_derr.2668328284
/workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/4.flash_ctrl_rw_evict.302281389
/workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/4.flash_ctrl_rw_evict_all_en.558607476
/workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/4.flash_ctrl_rw_serr.2259512716
/workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/4.flash_ctrl_sec_cm.2556556510
/workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/4.flash_ctrl_sec_info_access.469469252
/workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/4.flash_ctrl_serr_address.2798136090
/workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/4.flash_ctrl_serr_counter.1956957297
/workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/4.flash_ctrl_smoke.1053056019
/workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/4.flash_ctrl_smoke_hw.2464421339
/workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/4.flash_ctrl_stress_all.2498890933
/workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/4.flash_ctrl_sw_op.3737825439
/workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/4.flash_ctrl_wo.2612911905
/workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/40.flash_ctrl_alert_test.1970090351
/workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/40.flash_ctrl_connect.3079822934
/workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/40.flash_ctrl_disable.434586153
/workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/40.flash_ctrl_hw_sec_otp.1016212535
/workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/40.flash_ctrl_otp_reset.582011365
/workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/40.flash_ctrl_sec_info_access.2878147205
/workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/40.flash_ctrl_smoke.3698058112
/workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/41.flash_ctrl_alert_test.3731451397
/workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/41.flash_ctrl_connect.3202200089
/workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/41.flash_ctrl_disable.376341087
/workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/41.flash_ctrl_hw_sec_otp.615867505
/workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/41.flash_ctrl_otp_reset.150037549
/workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/41.flash_ctrl_sec_info_access.837169791
/workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/41.flash_ctrl_smoke.2071861385
/workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/42.flash_ctrl_alert_test.1135880777
/workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/42.flash_ctrl_connect.4045535892
/workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/42.flash_ctrl_disable.3730586730
/workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/42.flash_ctrl_hw_sec_otp.1844939049
/workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/42.flash_ctrl_otp_reset.3399303551
/workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/42.flash_ctrl_sec_info_access.2444577780
/workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/42.flash_ctrl_smoke.3466917514
/workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/43.flash_ctrl_alert_test.2357314767
/workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/43.flash_ctrl_connect.3452022534
/workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/43.flash_ctrl_disable.92238772
/workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/43.flash_ctrl_hw_sec_otp.3155139345
/workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/43.flash_ctrl_otp_reset.187511045
/workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/43.flash_ctrl_smoke.3389798249
/workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/44.flash_ctrl_alert_test.1210837916
/workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/44.flash_ctrl_connect.4290967035
/workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/44.flash_ctrl_disable.2244222255
/workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/44.flash_ctrl_hw_sec_otp.3295692568
/workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/44.flash_ctrl_otp_reset.2018442260
/workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/44.flash_ctrl_sec_info_access.4151555470
/workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/44.flash_ctrl_smoke.367869360
/workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/45.flash_ctrl_alert_test.2020557261
/workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/45.flash_ctrl_connect.4017760099
/workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/45.flash_ctrl_disable.2653581689
/workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/45.flash_ctrl_hw_sec_otp.3113855799
/workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/45.flash_ctrl_otp_reset.797148225
/workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/45.flash_ctrl_sec_info_access.2386971934
/workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/45.flash_ctrl_smoke.1217816746
/workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/46.flash_ctrl_alert_test.2466317360
/workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/46.flash_ctrl_connect.3913562956
/workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/46.flash_ctrl_disable.1934124359
/workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/46.flash_ctrl_hw_sec_otp.3505576832
/workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/46.flash_ctrl_otp_reset.2204076369
/workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/46.flash_ctrl_sec_info_access.1732177868
/workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/46.flash_ctrl_smoke.2001527172
/workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/47.flash_ctrl_alert_test.740104744
/workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/47.flash_ctrl_connect.4107717997
/workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/47.flash_ctrl_disable.3639534840
/workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/47.flash_ctrl_hw_sec_otp.3614135924
/workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/47.flash_ctrl_otp_reset.2993863035
/workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/47.flash_ctrl_sec_info_access.4194268212
/workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/47.flash_ctrl_smoke.1449918078
/workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/48.flash_ctrl_alert_test.1160527334
/workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/48.flash_ctrl_connect.3535575334
/workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/48.flash_ctrl_disable.1392931934
/workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/48.flash_ctrl_hw_sec_otp.1481911925
/workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/48.flash_ctrl_otp_reset.196290997
/workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/48.flash_ctrl_sec_info_access.946632487
/workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/48.flash_ctrl_smoke.4286306256
/workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/49.flash_ctrl_alert_test.764124950
/workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/49.flash_ctrl_connect.1084321316
/workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/49.flash_ctrl_disable.3483687302
/workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/49.flash_ctrl_hw_sec_otp.3672820558
/workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/49.flash_ctrl_otp_reset.3767061985
/workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/49.flash_ctrl_sec_info_access.3574762052
/workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/49.flash_ctrl_smoke.3732366530
/workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/5.flash_ctrl_alert_test.1103027641
/workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/5.flash_ctrl_connect.3087608581
/workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/5.flash_ctrl_disable.202289730
/workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/5.flash_ctrl_error_mp.3939191168
/workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/5.flash_ctrl_error_prog_win.2301736036
/workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/5.flash_ctrl_fetch_code.1519313067
/workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/5.flash_ctrl_hw_prog_rma_wipe_err.2024237415
/workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/5.flash_ctrl_hw_read_seed_err.3658981865
/workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/5.flash_ctrl_hw_rma_reset.3247254418
/workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/5.flash_ctrl_intr_rd.987385650
/workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/5.flash_ctrl_intr_rd_slow_flash.99970491
/workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/5.flash_ctrl_intr_wr.1591169371
/workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/5.flash_ctrl_intr_wr_slow_flash.3388062934
/workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/5.flash_ctrl_invalid_op.733941178
/workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/5.flash_ctrl_lcmgr_intg.1042200335
/workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/5.flash_ctrl_mp_regions.479098823
/workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/5.flash_ctrl_phy_arb.2049090749
/workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/5.flash_ctrl_prog_reset.302321037
/workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/5.flash_ctrl_rand_ops.325095994
/workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/5.flash_ctrl_re_evict.4180569235
/workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/5.flash_ctrl_ro.1419962939
/workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/5.flash_ctrl_ro_derr.2301098729
/workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/5.flash_ctrl_ro_serr.1443581412
/workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/5.flash_ctrl_rw.2654454888
/workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/5.flash_ctrl_rw_derr.2123802205
/workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/5.flash_ctrl_rw_evict.1059387671
/workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/5.flash_ctrl_rw_evict_all_en.2847986919
/workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/5.flash_ctrl_rw_serr.4271096752
/workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/5.flash_ctrl_sec_info_access.3855240080
/workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/5.flash_ctrl_smoke.2126581827
/workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/5.flash_ctrl_wo.2406727434
/workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/50.flash_ctrl_connect.3249419963
/workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/50.flash_ctrl_otp_reset.1364052124
/workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/51.flash_ctrl_connect.3149476774
/workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/51.flash_ctrl_otp_reset.67350381
/workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/52.flash_ctrl_connect.464582806
/workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/52.flash_ctrl_otp_reset.1217375636
/workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/53.flash_ctrl_connect.3534233470
/workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/53.flash_ctrl_otp_reset.175128372
/workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/54.flash_ctrl_connect.3520663239
/workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/54.flash_ctrl_otp_reset.3287243814
/workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/55.flash_ctrl_connect.954537712
/workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/55.flash_ctrl_otp_reset.1347186153
/workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/56.flash_ctrl_connect.1926450942
/workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/56.flash_ctrl_otp_reset.1500778671
/workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/57.flash_ctrl_connect.433748960
/workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/57.flash_ctrl_otp_reset.1504271591
/workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/58.flash_ctrl_connect.1127521448
/workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/58.flash_ctrl_otp_reset.2874929465
/workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/59.flash_ctrl_connect.1637501308
/workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/59.flash_ctrl_otp_reset.2271509386
/workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/6.flash_ctrl_alert_test.4235511218
/workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/6.flash_ctrl_connect.1745284686
/workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/6.flash_ctrl_disable.3868218909
/workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/6.flash_ctrl_error_mp.2700938017
/workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/6.flash_ctrl_error_prog_win.3457855123
/workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/6.flash_ctrl_fetch_code.2601039412
/workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/6.flash_ctrl_hw_prog_rma_wipe_err.1738511988
/workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/6.flash_ctrl_hw_read_seed_err.3796687453
/workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/6.flash_ctrl_hw_rma_reset.2794139624
/workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/6.flash_ctrl_hw_sec_otp.207690171
/workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/6.flash_ctrl_intr_rd.118191990
/workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/6.flash_ctrl_intr_rd_slow_flash.185956287
/workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/6.flash_ctrl_intr_wr.1740652985
/workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/6.flash_ctrl_invalid_op.322062666
/workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/6.flash_ctrl_lcmgr_intg.2845277275
/workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/6.flash_ctrl_mp_regions.3224011903
/workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/6.flash_ctrl_otp_reset.2982127734
/workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/6.flash_ctrl_phy_arb.2860867305
/workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/6.flash_ctrl_prog_reset.2141033553
/workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/6.flash_ctrl_rand_ops.4274124431
/workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/6.flash_ctrl_re_evict.2999115688
/workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/6.flash_ctrl_ro.879789297
/workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/6.flash_ctrl_ro_derr.2401372506
/workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/6.flash_ctrl_ro_serr.1995369351
/workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/6.flash_ctrl_rw.123655665
/workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/6.flash_ctrl_rw_derr.2150091112
/workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/6.flash_ctrl_rw_evict.1556346571
/workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/6.flash_ctrl_rw_evict_all_en.4177337047
/workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/6.flash_ctrl_rw_serr.1560941276
/workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/6.flash_ctrl_sec_info_access.1795561225
/workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/6.flash_ctrl_smoke.2956824058
/workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/6.flash_ctrl_wo.766914565
/workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/60.flash_ctrl_connect.3402209999
/workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/60.flash_ctrl_otp_reset.1611042825
/workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/61.flash_ctrl_connect.1385132191
/workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/61.flash_ctrl_otp_reset.1987631663
/workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/62.flash_ctrl_connect.2761045064
/workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/62.flash_ctrl_otp_reset.1914197277
/workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/63.flash_ctrl_connect.1575260349
/workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/63.flash_ctrl_otp_reset.2044561546
/workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/64.flash_ctrl_connect.153144035
/workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/64.flash_ctrl_otp_reset.871128974
/workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/65.flash_ctrl_connect.2177481510
/workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/65.flash_ctrl_otp_reset.160816838
/workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/66.flash_ctrl_connect.253017055
/workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/66.flash_ctrl_otp_reset.72572881
/workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/67.flash_ctrl_connect.788475084
/workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/67.flash_ctrl_otp_reset.2754768641
/workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/68.flash_ctrl_connect.3740902169
/workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/68.flash_ctrl_otp_reset.4162464463
/workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/69.flash_ctrl_connect.41085367
/workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/69.flash_ctrl_otp_reset.292149964
/workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/7.flash_ctrl_alert_test.292664062
/workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/7.flash_ctrl_error_mp.3521271581
/workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/7.flash_ctrl_error_prog_win.3303991323
/workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/7.flash_ctrl_fetch_code.3929991644
/workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/7.flash_ctrl_hw_prog_rma_wipe_err.3933846283
/workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/7.flash_ctrl_hw_read_seed_err.1220699198
/workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/7.flash_ctrl_hw_rma_reset.657185488
/workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/7.flash_ctrl_hw_sec_otp.1854205569
/workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/7.flash_ctrl_intr_rd.2268417573
/workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/7.flash_ctrl_intr_rd_slow_flash.3503644120
/workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/7.flash_ctrl_intr_wr.1211584940
/workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/7.flash_ctrl_intr_wr_slow_flash.1883134691
/workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/7.flash_ctrl_invalid_op.1083139986
/workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/7.flash_ctrl_lcmgr_intg.2160558538
/workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/7.flash_ctrl_mp_regions.4039033284
/workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/7.flash_ctrl_otp_reset.1189501182
/workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/7.flash_ctrl_phy_arb.4000150590
/workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/7.flash_ctrl_prog_reset.4176190039
/workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/7.flash_ctrl_rand_ops.2061388438
/workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/7.flash_ctrl_re_evict.3010117949
/workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/7.flash_ctrl_ro.3903741980
/workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/7.flash_ctrl_ro_derr.951436429
/workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/7.flash_ctrl_ro_serr.2913128674
/workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/7.flash_ctrl_rw.200231776
/workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/7.flash_ctrl_rw_derr.2826360630
/workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/7.flash_ctrl_rw_evict.4217034777
/workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/7.flash_ctrl_rw_evict_all_en.2325010259
/workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/7.flash_ctrl_rw_serr.1139668369
/workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/7.flash_ctrl_sec_info_access.3455334608
/workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/7.flash_ctrl_smoke.4094784735
/workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/7.flash_ctrl_wo.1659341065
/workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/70.flash_ctrl_connect.1038121698
/workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/70.flash_ctrl_otp_reset.1828844334
/workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/71.flash_ctrl_connect.131060549
/workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/72.flash_ctrl_connect.3842701438
/workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/72.flash_ctrl_otp_reset.3737725582
/workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/73.flash_ctrl_connect.3590332270
/workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/73.flash_ctrl_otp_reset.1600049057
/workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/74.flash_ctrl_connect.845626745
/workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/74.flash_ctrl_otp_reset.437242497
/workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/75.flash_ctrl_connect.1657699986
/workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/75.flash_ctrl_otp_reset.4058081661
/workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/76.flash_ctrl_connect.1023585905
/workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/76.flash_ctrl_otp_reset.2743816138
/workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/77.flash_ctrl_connect.4123698942
/workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/78.flash_ctrl_connect.1283231354
/workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/78.flash_ctrl_otp_reset.2294326730
/workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/79.flash_ctrl_connect.910327668
/workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/79.flash_ctrl_otp_reset.3942749713
/workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/8.flash_ctrl_alert_test.4127446397
/workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/8.flash_ctrl_connect.291690988
/workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/8.flash_ctrl_disable.1133501655
/workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/8.flash_ctrl_error_mp.2181430858
/workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/8.flash_ctrl_error_prog_win.3568071128
/workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/8.flash_ctrl_fetch_code.621951636
/workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/8.flash_ctrl_hw_prog_rma_wipe_err.3858631373
/workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/8.flash_ctrl_hw_read_seed_err.1317510005
/workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/8.flash_ctrl_hw_rma_reset.2726508069
/workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/8.flash_ctrl_hw_sec_otp.446249269
/workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/8.flash_ctrl_intr_rd.1765693586
/workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/8.flash_ctrl_intr_rd_slow_flash.1212754083
/workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/8.flash_ctrl_intr_wr.3156461765
/workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/8.flash_ctrl_intr_wr_slow_flash.26941223
/workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/8.flash_ctrl_invalid_op.3996221053
/workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/8.flash_ctrl_mp_regions.857808351
/workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/8.flash_ctrl_phy_arb.1753283701
/workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/8.flash_ctrl_prog_reset.1955362744
/workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/8.flash_ctrl_rand_ops.3798012220
/workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/8.flash_ctrl_ro.4079775813
/workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/8.flash_ctrl_ro_derr.2596720299
/workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/8.flash_ctrl_ro_serr.3918272464
/workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/8.flash_ctrl_rw.2033771701
/workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/8.flash_ctrl_rw_derr.3616928819
/workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/8.flash_ctrl_rw_evict.3096011133
/workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/8.flash_ctrl_rw_evict_all_en.3670033179
/workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/8.flash_ctrl_rw_serr.4252980585
/workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/8.flash_ctrl_sec_info_access.2062232809
/workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/8.flash_ctrl_smoke.2117379103
/workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/8.flash_ctrl_wo.1718948779
/workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/9.flash_ctrl_alert_test.3213703048
/workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/9.flash_ctrl_connect.1268896753
/workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/9.flash_ctrl_disable.3650703129
/workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/9.flash_ctrl_error_mp.2190958778
/workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/9.flash_ctrl_error_prog_win.1486887543
/workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/9.flash_ctrl_fetch_code.2012818635
/workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/9.flash_ctrl_hw_prog_rma_wipe_err.281861225
/workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/9.flash_ctrl_hw_read_seed_err.1547816728
/workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/9.flash_ctrl_hw_rma_reset.3370494145
/workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/9.flash_ctrl_hw_sec_otp.2684100278
/workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/9.flash_ctrl_intr_rd.585507439
/workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/9.flash_ctrl_intr_rd_slow_flash.157822417
/workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/9.flash_ctrl_intr_wr.507485975
/workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/9.flash_ctrl_intr_wr_slow_flash.3171210379
/workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/9.flash_ctrl_invalid_op.2524940223
/workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/9.flash_ctrl_lcmgr_intg.2470771630
/workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/9.flash_ctrl_mp_regions.1303716769
/workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/9.flash_ctrl_otp_reset.671015341
/workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/9.flash_ctrl_phy_arb.2255032564
/workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/9.flash_ctrl_prog_reset.2284547097
/workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/9.flash_ctrl_rand_ops.2479957901
/workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/9.flash_ctrl_re_evict.4070506194
/workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/9.flash_ctrl_ro.1769653419
/workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/9.flash_ctrl_ro_derr.2562873424
/workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/9.flash_ctrl_ro_serr.2314996571
/workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/9.flash_ctrl_rw.1999056195
/workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/9.flash_ctrl_rw_derr.4165316991
/workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/9.flash_ctrl_rw_evict.2594455211
/workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/9.flash_ctrl_rw_evict_all_en.112442571
/workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/9.flash_ctrl_rw_serr.4062271874
/workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/9.flash_ctrl_sec_info_access.4262913087
/workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/9.flash_ctrl_smoke.103788168
/workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/9.flash_ctrl_wo.2665384011



Total test records in report: 1271
tests.html | tests1.html | tests2.html | tests3.html | tests4.html | tests5.html | tests6.html | tests7.html | tests8.html | tests9.html | tests10.html | tests11.html | tests12.html | tests13.html | tests14.html | tests15.html | tests16.html | tests17.html | tests18.html | tests19.html | tests20.html | tests21.html | tests22.html | tests23.html | tests24.html | tests25.html | tests26.html
TEST NOTEST LOCATIONTEST NAMESTATUSSTARTEDFINISHEDSIMULATION TIME
T1 /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/0.flash_ctrl_read_word_sweep.1857817590 Sep 09 05:33:02 PM UTC 24 Sep 09 05:33:21 PM UTC 24 48526000 ps
T2 /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/0.flash_ctrl_smoke_hw.3391579057 Sep 09 05:32:47 PM UTC 24 Sep 09 05:33:22 PM UTC 24 144894300 ps
T3 /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/0.flash_ctrl_write_word_sweep.2937732399 Sep 09 05:33:02 PM UTC 24 Sep 09 05:33:31 PM UTC 24 42874000 ps
T7 /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/0.flash_ctrl_sw_op.122455886 Sep 09 05:32:50 PM UTC 24 Sep 09 05:33:32 PM UTC 24 26783700 ps
T14 /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/0.flash_ctrl_fetch_code.3199175620 Sep 09 05:32:57 PM UTC 24 Sep 09 05:33:35 PM UTC 24 252939800 ps
T18 /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/0.flash_ctrl_read_word_sweep_derr.398442348 Sep 09 05:33:06 PM UTC 24 Sep 09 05:33:39 PM UTC 24 19049800 ps
T19 /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/0.flash_ctrl_read_word_sweep_serr.4102734495 Sep 09 05:33:02 PM UTC 24 Sep 09 05:33:41 PM UTC 24 42323800 ps
T20 /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/0.flash_ctrl_smoke.4031768799 Sep 09 05:32:47 PM UTC 24 Sep 09 05:33:49 PM UTC 24 36511200 ps
T21 /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/0.flash_ctrl_prog_reset.2313418965 Sep 09 05:33:32 PM UTC 24 Sep 09 05:34:01 PM UTC 24 64454800 ps
T15 /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/0.flash_ctrl_host_dir_rd.3969367004 Sep 09 05:32:50 PM UTC 24 Sep 09 05:34:11 PM UTC 24 39602400 ps
T58 /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/0.flash_ctrl_serr_address.2893528581 Sep 09 05:33:06 PM UTC 24 Sep 09 05:34:15 PM UTC 24 493948600 ps
T8 /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/0.flash_ctrl_disable.518145303 Sep 09 05:33:42 PM UTC 24 Sep 09 05:34:23 PM UTC 24 13139200 ps
T25 /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/0.flash_ctrl_rw_evict.1926195226 Sep 09 05:33:33 PM UTC 24 Sep 09 05:34:31 PM UTC 24 28907600 ps
T26 /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/0.flash_ctrl_re_evict.620289488 Sep 09 05:33:39 PM UTC 24 Sep 09 05:34:31 PM UTC 24 74965200 ps
T27 /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/0.flash_ctrl_rw_evict_all_en.53519437 Sep 09 05:33:36 PM UTC 24 Sep 09 05:34:34 PM UTC 24 118092700 ps
T16 /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/0.flash_ctrl_serr_counter.475596563 Sep 09 05:33:06 PM UTC 24 Sep 09 05:34:37 PM UTC 24 1210019800 ps
T63 /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/0.flash_ctrl_hw_sec_otp.953586226 Sep 09 05:32:52 PM UTC 24 Sep 09 05:34:40 PM UTC 24 1181722000 ps
T4 /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/0.flash_ctrl_connect.3985234731 Sep 09 05:34:16 PM UTC 24 Sep 09 05:34:42 PM UTC 24 16291800 ps
T49 /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/0.flash_ctrl_ro.176654613 Sep 09 05:33:02 PM UTC 24 Sep 09 05:34:45 PM UTC 24 1844459800 ps
T62 /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/0.flash_ctrl_mp_regions.3386694143 Sep 09 05:32:57 PM UTC 24 Sep 09 05:34:47 PM UTC 24 6073274600 ps
T41 /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/0.flash_ctrl_ro_serr.3116835678 Sep 09 05:33:04 PM UTC 24 Sep 09 05:34:49 PM UTC 24 3970824400 ps
T9 /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/0.flash_ctrl_access_after_disable.2227090079 Sep 09 05:34:32 PM UTC 24 Sep 09 05:34:56 PM UTC 24 12724700 ps
T29 /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/0.flash_ctrl_intr_wr.1935464315 Sep 09 05:33:13 PM UTC 24 Sep 09 05:34:56 PM UTC 24 2163487400 ps
T10 /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/0.flash_ctrl_wr_intg.1938708451 Sep 09 05:34:32 PM UTC 24 Sep 09 05:35:00 PM UTC 24 48201800 ps
T71 /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/0.flash_ctrl_invalid_op.2867479541 Sep 09 05:33:00 PM UTC 24 Sep 09 05:35:02 PM UTC 24 14298095100 ps
T50 /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/0.flash_ctrl_mid_op_rst.2130553357 Sep 09 05:33:00 PM UTC 24 Sep 09 05:35:03 PM UTC 24 7495078000 ps
T127 /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/0.flash_ctrl_lcmgr_intg.3327513843 Sep 09 05:34:48 PM UTC 24 Sep 09 05:35:08 PM UTC 24 46510200 ps
T59 /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/0.flash_ctrl_phy_arb_redun.3420118129 Sep 09 05:34:38 PM UTC 24 Sep 09 05:35:09 PM UTC 24 816359600 ps
T56 /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/0.flash_ctrl_phy_host_grant_err.2552572478 Sep 09 05:34:40 PM UTC 24 Sep 09 05:35:11 PM UTC 24 15681600 ps
T42 /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/0.flash_ctrl_rd_intg.2576296948 Sep 09 05:34:24 PM UTC 24 Sep 09 05:35:11 PM UTC 24 68948200 ps
T158 /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/0.flash_ctrl_config_regwen.2237006450 Sep 09 05:34:45 PM UTC 24 Sep 09 05:35:14 PM UTC 24 77240600 ps
T159 /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/0.flash_ctrl_hw_read_seed_err.1813969164 Sep 09 05:34:50 PM UTC 24 Sep 09 05:35:14 PM UTC 24 48987800 ps
T52 /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/0.flash_ctrl_rd_buff_evict.1100043867 Sep 09 05:32:52 PM UTC 24 Sep 09 05:35:14 PM UTC 24 2627612600 ps
T32 /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/0.flash_ctrl_intr_rd.3284738176 Sep 09 05:33:12 PM UTC 24 Sep 09 05:35:15 PM UTC 24 735164000 ps
T112 /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/0.flash_ctrl_phy_ack_consistency.1694877633 Sep 09 05:34:45 PM UTC 24 Sep 09 05:35:16 PM UTC 24 167172200 ps
T98 /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/0.flash_ctrl_alert_test.2906666777 Sep 09 05:35:03 PM UTC 24 Sep 09 05:35:31 PM UTC 24 138513100 ps
T87 /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/0.flash_ctrl_fs_sup.3009267976 Sep 09 05:34:34 PM UTC 24 Sep 09 05:35:32 PM UTC 24 1757609900 ps
T57 /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/0.flash_ctrl_ro_derr.3009225734 Sep 09 05:33:06 PM UTC 24 Sep 09 05:35:33 PM UTC 24 2749574100 ps
T113 /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/0.flash_ctrl_otp_reset.2540871239 Sep 09 05:32:55 PM UTC 24 Sep 09 05:35:34 PM UTC 24 75368100 ps
T33 /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/0.flash_ctrl_sec_info_access.3502968244 Sep 09 05:34:02 PM UTC 24 Sep 09 05:35:36 PM UTC 24 1890281800 ps
T233 /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/1.flash_ctrl_smoke_hw.4159348001 Sep 09 05:35:08 PM UTC 24 Sep 09 05:35:39 PM UTC 24 14680400 ps
T234 /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/1.flash_ctrl_sw_op.2392205847 Sep 09 05:35:11 PM UTC 24 Sep 09 05:35:43 PM UTC 24 24925800 ps
T378 /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/0.flash_ctrl_host_addr_infection.4209868870 Sep 09 05:35:01 PM UTC 24 Sep 09 05:35:51 PM UTC 24 27738300 ps
T51 /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/0.flash_ctrl_oversize_error.2999247206 Sep 09 05:33:09 PM UTC 24 Sep 09 05:36:04 PM UTC 24 6937988600 ps
T228 /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/0.flash_ctrl_rd_ooo.2222212677 Sep 09 05:34:58 PM UTC 24 Sep 09 05:36:18 PM UTC 24 97676400 ps
T46 /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/1.flash_ctrl_fetch_code.865922735 Sep 09 05:35:36 PM UTC 24 Sep 09 05:36:20 PM UTC 24 1104735000 ps
T160 /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/0.flash_ctrl_rw_derr.749817179 Sep 09 05:33:09 PM UTC 24 Sep 09 05:36:25 PM UTC 24 3229933700 ps
T101 /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/0.flash_ctrl_rw_serr.3676583535 Sep 09 05:33:06 PM UTC 24 Sep 09 05:36:28 PM UTC 24 9810457600 ps
T245 /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/1.flash_ctrl_host_dir_rd.4118212858 Sep 09 05:35:12 PM UTC 24 Sep 09 05:36:45 PM UTC 24 42259500 ps
T145 /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/0.flash_ctrl_wo.578038009 Sep 09 05:33:00 PM UTC 24 Sep 09 05:36:57 PM UTC 24 6475262000 ps
T47 /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/1.flash_ctrl_smoke.823098157 Sep 09 05:35:04 PM UTC 24 Sep 09 05:36:58 PM UTC 24 55164900 ps
T83 /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/1.flash_ctrl_invalid_op.9356920 Sep 09 05:36:20 PM UTC 24 Sep 09 05:37:25 PM UTC 24 1748874100 ps
T210 /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/0.flash_ctrl_derr_detect.3379159762 Sep 09 05:33:09 PM UTC 24 Sep 09 05:37:27 PM UTC 24 2700729200 ps
T30 /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/0.flash_ctrl_intr_wr_slow_flash.281289929 Sep 09 05:33:22 PM UTC 24 Sep 09 05:37:36 PM UTC 24 53272834000 ps
T38 /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/0.flash_ctrl_intr_rd_slow_flash.2857095289 Sep 09 05:33:22 PM UTC 24 Sep 09 05:37:37 PM UTC 24 16651596000 ps
T374 /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/1.flash_ctrl_read_word_sweep_serr.3496306376 Sep 09 05:36:58 PM UTC 24 Sep 09 05:37:38 PM UTC 24 111900300 ps
T96 /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/1.flash_ctrl_mid_op_rst.3704917737 Sep 09 05:36:21 PM UTC 24 Sep 09 05:37:39 PM UTC 24 3742333700 ps
T147 /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/0.flash_ctrl_rand_ops.2611036791 Sep 09 05:32:50 PM UTC 24 Sep 09 05:38:18 PM UTC 24 103471800 ps
T381 /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/1.flash_ctrl_read_word_sweep_derr.1283790033 Sep 09 05:37:38 PM UTC 24 Sep 09 05:38:24 PM UTC 24 18535700 ps
T103 /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/1.flash_ctrl_hw_sec_otp.3272686431 Sep 09 05:35:16 PM UTC 24 Sep 09 05:38:26 PM UTC 24 8265872100 ps
T65 /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/1.flash_ctrl_rd_buff_evict.1763793742 Sep 09 05:35:15 PM UTC 24 Sep 09 05:38:34 PM UTC 24 5754409100 ps
T246 /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/1.flash_ctrl_phy_arb.1646147595 Sep 09 05:35:15 PM UTC 24 Sep 09 05:38:36 PM UTC 24 45505200 ps
T205 /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/1.flash_ctrl_ro.3093025309 Sep 09 05:36:29 PM UTC 24 Sep 09 05:38:52 PM UTC 24 944579100 ps
T375 /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/1.flash_ctrl_wo.564847151 Sep 09 05:36:26 PM UTC 24 Sep 09 05:39:04 PM UTC 24 2039451900 ps
T272 /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/1.flash_ctrl_serr_counter.3353137793 Sep 09 05:37:28 PM UTC 24 Sep 09 05:39:05 PM UTC 24 2164500700 ps
T270 /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/1.flash_ctrl_serr_address.1597725250 Sep 09 05:37:37 PM UTC 24 Sep 09 05:39:21 PM UTC 24 7806144700 ps
T69 /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/0.flash_ctrl_phy_arb.625269978 Sep 09 05:32:52 PM UTC 24 Sep 09 05:39:25 PM UTC 24 2821168600 ps
T89 /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/0.flash_ctrl_hw_prog_rma_wipe_err.3205806279 Sep 09 05:34:57 PM UTC 24 Sep 09 05:39:25 PM UTC 24 10012972700 ps
T102 /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/1.flash_ctrl_ro_serr.3667811319 Sep 09 05:36:58 PM UTC 24 Sep 09 05:39:30 PM UTC 24 1617932300 ps
T119 /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/1.flash_ctrl_otp_reset.247990062 Sep 09 05:35:33 PM UTC 24 Sep 09 05:39:31 PM UTC 24 90012000 ps
T380 /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/1.flash_ctrl_prog_reset.185194169 Sep 09 05:39:06 PM UTC 24 Sep 09 05:39:34 PM UTC 24 93162200 ps
T31 /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/1.flash_ctrl_intr_wr.349474850 Sep 09 05:38:37 PM UTC 24 Sep 09 05:39:43 PM UTC 24 1740491800 ps
T77 /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/1.flash_ctrl_disable.390741902 Sep 09 05:39:26 PM UTC 24 Sep 09 05:39:53 PM UTC 24 18367700 ps
T39 /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/1.flash_ctrl_ro_derr.515646628 Sep 09 05:37:39 PM UTC 24 Sep 09 05:39:58 PM UTC 24 2277934200 ps
T28 /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/1.flash_ctrl_rw_evict.1462123476 Sep 09 05:39:06 PM UTC 24 Sep 09 05:40:04 PM UTC 24 43340700 ps
T146 /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/1.flash_ctrl_re_evict.935544876 Sep 09 05:39:26 PM UTC 24 Sep 09 05:40:06 PM UTC 24 722359600 ps
T154 /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/1.flash_ctrl_rw_evict_all_en.2175339349 Sep 09 05:39:22 PM UTC 24 Sep 09 05:40:08 PM UTC 24 41064400 ps
T72 /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/0.flash_ctrl_erase_suspend.3595356841 Sep 09 05:32:54 PM UTC 24 Sep 09 05:40:10 PM UTC 24 1395460500 ps
T5 /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/1.flash_ctrl_connect.2079753966 Sep 09 05:39:43 PM UTC 24 Sep 09 05:40:15 PM UTC 24 15482800 ps
T206 /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/0.flash_ctrl_integrity.2380296237 Sep 09 05:33:11 PM UTC 24 Sep 09 05:40:22 PM UTC 24 3799013200 ps
T11 /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/1.flash_ctrl_wr_intg.4056994345 Sep 09 05:39:59 PM UTC 24 Sep 09 05:40:25 PM UTC 24 163717400 ps
T60 /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/1.flash_ctrl_phy_ack_consistency.1240076788 Sep 09 05:40:11 PM UTC 24 Sep 09 05:40:28 PM UTC 24 15105500 ps
T226 /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/1.flash_ctrl_phy_host_grant_err.2467173467 Sep 09 05:40:10 PM UTC 24 Sep 09 05:40:32 PM UTC 24 45298800 ps
T23 /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/1.flash_ctrl_access_after_disable.1507516686 Sep 09 05:40:05 PM UTC 24 Sep 09 05:40:33 PM UTC 24 22940100 ps
T348 /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/1.flash_ctrl_rd_intg.2351148993 Sep 09 05:39:54 PM UTC 24 Sep 09 05:40:38 PM UTC 24 115806900 ps
T362 /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/1.flash_ctrl_config_regwen.362808816 Sep 09 05:40:15 PM UTC 24 Sep 09 05:40:45 PM UTC 24 56140600 ps
T74 /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/1.flash_ctrl_phy_arb_redun.3804903680 Sep 09 05:40:09 PM UTC 24 Sep 09 05:40:48 PM UTC 24 794071900 ps
T171 /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/1.flash_ctrl_hw_read_seed_err.3849782107 Sep 09 05:40:29 PM UTC 24 Sep 09 05:40:49 PM UTC 24 25937000 ps
T211 /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/1.flash_ctrl_rw_derr.2636250387 Sep 09 05:37:40 PM UTC 24 Sep 09 05:40:51 PM UTC 24 1727867200 ps
T34 /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/1.flash_ctrl_sec_info_access.2625821658 Sep 09 05:39:32 PM UTC 24 Sep 09 05:40:51 PM UTC 24 7228523100 ps
T172 /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/1.flash_ctrl_lcmgr_intg.3230020156 Sep 09 05:40:25 PM UTC 24 Sep 09 05:40:52 PM UTC 24 22174800 ps
T88 /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/1.flash_ctrl_fs_sup.3708602680 Sep 09 05:40:07 PM UTC 24 Sep 09 05:41:01 PM UTC 24 332475400 ps
T99 /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/1.flash_ctrl_alert_test.744134193 Sep 09 05:40:39 PM UTC 24 Sep 09 05:41:01 PM UTC 24 66627000 ps
T216 /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/1.flash_ctrl_rw_serr.2723204012 Sep 09 05:37:26 PM UTC 24 Sep 09 05:41:09 PM UTC 24 4247525100 ps
T212 /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/0.flash_ctrl_rw.4058362743 Sep 09 05:33:02 PM UTC 24 Sep 09 05:41:14 PM UTC 24 3209556200 ps
T442 /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/2.flash_ctrl_smoke_hw.1572623676 Sep 09 05:40:47 PM UTC 24 Sep 09 05:41:24 PM UTC 24 22168700 ps
T384 /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/1.flash_ctrl_host_addr_infection.2146105188 Sep 09 05:40:34 PM UTC 24 Sep 09 05:41:34 PM UTC 24 64320700 ps
T35 /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/1.flash_ctrl_mp_regions.680726535 Sep 09 05:35:34 PM UTC 24 Sep 09 05:41:36 PM UTC 24 30946578800 ps
T122 /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/1.flash_ctrl_hw_prog_rma_wipe_err.3714441726 Sep 09 05:40:32 PM UTC 24 Sep 09 05:41:36 PM UTC 24 10039161300 ps
T139 /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/1.flash_ctrl_oversize_error.536616134 Sep 09 05:38:26 PM UTC 24 Sep 09 05:41:37 PM UTC 24 2479735200 ps
T140 /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/2.flash_ctrl_sw_op.349387670 Sep 09 05:40:50 PM UTC 24 Sep 09 05:41:40 PM UTC 24 43468800 ps
T141 /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/1.flash_ctrl_derr_detect.487065119 Sep 09 05:38:19 PM UTC 24 Sep 09 05:41:41 PM UTC 24 743629900 ps
T142 /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/0.flash_ctrl_stress_all.2322899116 Sep 09 05:34:12 PM UTC 24 Sep 09 05:42:00 PM UTC 24 320242400 ps
T53 /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/2.flash_ctrl_fetch_code.8342506 Sep 09 05:41:32 PM UTC 24 Sep 09 05:42:07 PM UTC 24 10026941900 ps
T143 /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/1.flash_ctrl_stress_all.177448704 Sep 09 05:39:35 PM UTC 24 Sep 09 05:42:32 PM UTC 24 523708500 ps
T144 /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/2.flash_ctrl_host_dir_rd.4064335948 Sep 09 05:40:51 PM UTC 24 Sep 09 05:42:44 PM UTC 24 91033800 ps
T40 /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/1.flash_ctrl_intr_rd.2945997567 Sep 09 05:38:35 PM UTC 24 Sep 09 05:42:46 PM UTC 24 1529512300 ps
T247 /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/2.flash_ctrl_rd_buff_evict.1438490607 Sep 09 05:40:52 PM UTC 24 Sep 09 05:42:55 PM UTC 24 268303900 ps
T373 /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/2.flash_ctrl_read_word_sweep_serr.3747994986 Sep 09 05:42:14 PM UTC 24 Sep 09 05:42:58 PM UTC 24 44300400 ps
T148 /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/2.flash_ctrl_invalid_op.3527823580 Sep 09 05:41:40 PM UTC 24 Sep 09 05:43:04 PM UTC 24 1536205900 ps
T163 /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/1.flash_ctrl_intr_wr_slow_flash.3633403629 Sep 09 05:39:00 PM UTC 24 Sep 09 05:43:18 PM UTC 24 22430875100 ps
T97 /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/2.flash_ctrl_mid_op_rst.453480753 Sep 09 05:41:42 PM UTC 24 Sep 09 05:43:32 PM UTC 24 1402141600 ps
T346 /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/1.flash_ctrl_intr_rd_slow_flash.349308498 Sep 09 05:38:53 PM UTC 24 Sep 09 05:43:39 PM UTC 24 16944272100 ps
T379 /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/2.flash_ctrl_read_word_sweep_derr.2659766682 Sep 09 05:42:56 PM UTC 24 Sep 09 05:43:40 PM UTC 24 26613000 ps
T104 /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/2.flash_ctrl_hw_sec_otp.2718849348 Sep 09 05:41:02 PM UTC 24 Sep 09 05:43:45 PM UTC 24 29819611200 ps
T70 /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/1.flash_ctrl_erase_suspend.3331916889 Sep 09 05:35:16 PM UTC 24 Sep 09 05:43:57 PM UTC 24 2131559600 ps
T215 /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/1.flash_ctrl_rw.312943239 Sep 09 05:36:46 PM UTC 24 Sep 09 05:44:03 PM UTC 24 32748867300 ps
T443 /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/2.flash_ctrl_serr_counter.3059533894 Sep 09 05:42:46 PM UTC 24 Sep 09 05:44:23 PM UTC 24 1441513500 ps
T376 /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/2.flash_ctrl_prog_reset.3004476445 Sep 09 05:43:58 PM UTC 24 Sep 09 05:44:23 PM UTC 24 35798000 ps
T301 /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/2.flash_ctrl_ro.217989448 Sep 09 05:42:01 PM UTC 24 Sep 09 05:44:26 PM UTC 24 1365721400 ps
T120 /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/2.flash_ctrl_otp_reset.517451295 Sep 09 05:41:25 PM UTC 24 Sep 09 05:44:30 PM UTC 24 80202100 ps
T217 /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/2.flash_ctrl_ro_serr.2371403695 Sep 09 05:42:22 PM UTC 24 Sep 09 05:44:38 PM UTC 24 4869533400 ps
T43 /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/2.flash_ctrl_rw_evict.10237805 Sep 09 05:44:04 PM UTC 24 Sep 09 05:44:45 PM UTC 24 28175400 ps
T78 /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/2.flash_ctrl_disable.3817247549 Sep 09 05:44:24 PM UTC 24 Sep 09 05:45:00 PM UTC 24 26795900 ps
T44 /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/2.flash_ctrl_rw_evict_all_en.2182496236 Sep 09 05:44:19 PM UTC 24 Sep 09 05:45:00 PM UTC 24 32418900 ps
T385 /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/2.flash_ctrl_serr_address.1579818407 Sep 09 05:42:47 PM UTC 24 Sep 09 05:45:06 PM UTC 24 4483922600 ps
T382 /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/2.flash_ctrl_wo.1105906448 Sep 09 05:41:42 PM UTC 24 Sep 09 05:45:06 PM UTC 24 2231315000 ps
T377 /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/2.flash_ctrl_intr_wr.2113429812 Sep 09 05:43:40 PM UTC 24 Sep 09 05:45:06 PM UTC 24 2404681200 ps
T6 /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/2.flash_ctrl_connect.4259215925 Sep 09 05:44:46 PM UTC 24 Sep 09 05:45:07 PM UTC 24 56734600 ps
T213 /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/2.flash_ctrl_re_evict.3106270190 Sep 09 05:44:23 PM UTC 24 Sep 09 05:45:12 PM UTC 24 61418800 ps
T22 /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/2.flash_ctrl_wr_intg.3011161323 Sep 09 05:45:01 PM UTC 24 Sep 09 05:45:18 PM UTC 24 43721100 ps
T24 /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/2.flash_ctrl_access_after_disable.4280399723 Sep 09 05:45:07 PM UTC 24 Sep 09 05:45:28 PM UTC 24 22787900 ps
T200 /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/2.flash_ctrl_oversize_error.3950700824 Sep 09 05:43:19 PM UTC 24 Sep 09 05:45:31 PM UTC 24 3771206100 ps
T12 /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/2.flash_ctrl_phy_host_grant_err.2983577582 Sep 09 05:45:09 PM UTC 24 Sep 09 05:45:33 PM UTC 24 15113100 ps
T204 /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/2.flash_ctrl_rd_intg.3436437161 Sep 09 05:45:01 PM UTC 24 Sep 09 05:45:38 PM UTC 24 70916200 ps
T61 /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/2.flash_ctrl_phy_ack_consistency.2160378239 Sep 09 05:45:13 PM UTC 24 Sep 09 05:45:40 PM UTC 24 36525400 ps
T75 /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/2.flash_ctrl_phy_arb_redun.677485512 Sep 09 05:45:07 PM UTC 24 Sep 09 05:45:43 PM UTC 24 865393500 ps
T299 /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/2.flash_ctrl_smoke.668741884 Sep 09 05:40:46 PM UTC 24 Sep 09 05:45:45 PM UTC 24 33871500 ps
T363 /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/2.flash_ctrl_config_regwen.3087455357 Sep 09 05:45:19 PM UTC 24 Sep 09 05:45:47 PM UTC 24 37659600 ps
T173 /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/2.flash_ctrl_lcmgr_intg.3550011449 Sep 09 05:45:33 PM UTC 24 Sep 09 05:45:51 PM UTC 24 29021900 ps
T269 /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/2.flash_ctrl_ro_derr.2607758581 Sep 09 05:42:59 PM UTC 24 Sep 09 05:45:52 PM UTC 24 2494048100 ps
T444 /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/2.flash_ctrl_rw_serr.3332433741 Sep 09 05:42:33 PM UTC 24 Sep 09 05:45:53 PM UTC 24 2116628500 ps
T438 /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/2.flash_ctrl_fs_sup.4065995921 Sep 09 05:45:07 PM UTC 24 Sep 09 05:45:58 PM UTC 24 1304843200 ps
T273 /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/2.flash_ctrl_hw_read_seed_err.3068778074 Sep 09 05:45:33 PM UTC 24 Sep 09 05:46:00 PM UTC 24 206975200 ps
T100 /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/2.flash_ctrl_alert_test.540518097 Sep 09 05:45:46 PM UTC 24 Sep 09 05:46:06 PM UTC 24 118296200 ps
T445 /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/2.flash_ctrl_host_addr_infection.3782333650 Sep 09 05:45:42 PM UTC 24 Sep 09 05:46:15 PM UTC 24 27170600 ps
T149 /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/2.flash_ctrl_mp_regions.3546643645 Sep 09 05:41:31 PM UTC 24 Sep 09 05:46:15 PM UTC 24 26005636200 ps
T446 /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/3.flash_ctrl_sw_op.321912864 Sep 09 05:45:53 PM UTC 24 Sep 09 05:46:26 PM UTC 24 50077500 ps
T447 /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/3.flash_ctrl_smoke_hw.1652896163 Sep 09 05:45:49 PM UTC 24 Sep 09 05:46:32 PM UTC 24 17671200 ps
T161 /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/2.flash_ctrl_rw_derr.2814285857 Sep 09 05:43:05 PM UTC 24 Sep 09 05:46:32 PM UTC 24 5330306200 ps
T224 /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/2.flash_ctrl_sec_info_access.4178193890 Sep 09 05:44:31 PM UTC 24 Sep 09 05:46:39 PM UTC 24 14842000400 ps
T440 /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/1.flash_ctrl_integrity.2252446038 Sep 09 05:38:27 PM UTC 24 Sep 09 05:46:47 PM UTC 24 5454294800 ps
T166 /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/2.flash_ctrl_hw_prog_rma_wipe_err.368733333 Sep 09 05:45:40 PM UTC 24 Sep 09 05:46:50 PM UTC 24 10071181200 ps
T448 /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/3.flash_ctrl_hw_sec_otp.3416719421 Sep 09 05:46:02 PM UTC 24 Sep 09 05:47:13 PM UTC 24 1454861000 ps
T54 /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/3.flash_ctrl_fetch_code.4078620391 Sep 09 05:46:33 PM UTC 24 Sep 09 05:47:14 PM UTC 24 1193010800 ps
T341 /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/2.flash_ctrl_intr_rd_slow_flash.3391729979 Sep 09 05:43:41 PM UTC 24 Sep 09 05:47:31 PM UTC 24 27627393200 ps
T125 /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/1.flash_ctrl_hw_rma_reset.2363643674 Sep 09 05:35:32 PM UTC 24 Sep 09 05:47:55 PM UTC 24 50125545500 ps
T194 /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/2.flash_ctrl_derr_detect.227495958 Sep 09 05:43:18 PM UTC 24 Sep 09 05:47:59 PM UTC 24 3281737100 ps
T195 /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/3.flash_ctrl_smoke.1283717430 Sep 09 05:45:46 PM UTC 24 Sep 09 05:48:01 PM UTC 24 24545200 ps
T196 /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/3.flash_ctrl_phy_arb.1065801612 Sep 09 05:46:01 PM UTC 24 Sep 09 05:48:12 PM UTC 24 123312800 ps
T197 /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/3.flash_ctrl_ro.2839985534 Sep 09 05:48:00 PM UTC 24 Sep 09 05:49:51 PM UTC 24 3400944400 ps
T198 /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/2.flash_ctrl_intr_rd.1727579998 Sep 09 05:43:33 PM UTC 24 Sep 09 05:48:14 PM UTC 24 30201192700 ps
T180 /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/3.flash_ctrl_otp_reset.1217058996 Sep 09 05:46:16 PM UTC 24 Sep 09 05:48:34 PM UTC 24 136717800 ps
T199 /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/2.flash_ctrl_phy_arb.1014943127 Sep 09 05:40:53 PM UTC 24 Sep 09 05:48:48 PM UTC 24 773559100 ps
T155 /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/3.flash_ctrl_invalid_op.2626607101 Sep 09 05:47:15 PM UTC 24 Sep 09 05:48:49 PM UTC 24 5728187100 ps
T121 /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/0.flash_ctrl_hw_rma_reset.1805674723 Sep 09 05:32:55 PM UTC 24 Sep 09 05:48:50 PM UTC 24 40127253400 ps
T449 /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/3.flash_ctrl_read_word_sweep_serr.1763173507 Sep 09 05:48:13 PM UTC 24 Sep 09 05:48:56 PM UTC 24 89935500 ps
T162 /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/3.flash_ctrl_mid_op_rst.2392082646 Sep 09 05:47:32 PM UTC 24 Sep 09 05:49:02 PM UTC 24 1969915100 ps
T271 /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/3.flash_ctrl_host_dir_rd.338966361 Sep 09 05:45:55 PM UTC 24 Sep 09 05:49:06 PM UTC 24 49188500 ps
T79 /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/0.flash_ctrl_rma_err.3264676531 Sep 09 05:34:46 PM UTC 24 Sep 09 05:49:21 PM UTC 24 83106124400 ps
T383 /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/3.flash_ctrl_read_word_sweep_derr.541499722 Sep 09 05:48:50 PM UTC 24 Sep 09 05:49:36 PM UTC 24 61319700 ps
T450 /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/2.flash_ctrl_intr_wr_slow_flash.1244170991 Sep 09 05:43:46 PM UTC 24 Sep 09 05:49:48 PM UTC 24 207721557700 ps
T218 /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/2.flash_ctrl_rw.1348398604 Sep 09 05:42:08 PM UTC 24 Sep 09 05:50:03 PM UTC 24 16923558500 ps
T231 /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/3.flash_ctrl_rd_buff_evict.4053942498 Sep 09 05:45:59 PM UTC 24 Sep 09 05:50:13 PM UTC 24 4932446900 ps
T451 /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/3.flash_ctrl_prog_reset.2176212295 Sep 09 05:49:49 PM UTC 24 Sep 09 05:50:17 PM UTC 24 69355100 ps
T452 /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/3.flash_ctrl_ro_serr.3578211100 Sep 09 05:48:15 PM UTC 24 Sep 09 05:50:20 PM UTC 24 2984150000 ps
T453 /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/3.flash_ctrl_serr_counter.1037467362 Sep 09 05:48:38 PM UTC 24 Sep 09 05:50:35 PM UTC 24 3364709800 ps
T454 /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/3.flash_ctrl_serr_address.4000630452 Sep 09 05:48:49 PM UTC 24 Sep 09 05:50:41 PM UTC 24 1784906800 ps
T455 /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/3.flash_ctrl_intr_wr.628792622 Sep 09 05:49:31 PM UTC 24 Sep 09 05:50:49 PM UTC 24 8271210000 ps
T80 /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/3.flash_ctrl_disable.2579821172 Sep 09 05:50:18 PM UTC 24 Sep 09 05:50:51 PM UTC 24 15326500 ps
T456 /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/3.flash_ctrl_rw_evict.4054567647 Sep 09 05:49:52 PM UTC 24 Sep 09 05:50:52 PM UTC 24 43780900 ps
T441 /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/3.flash_ctrl_rw_serr.1014758437 Sep 09 05:48:35 PM UTC 24 Sep 09 05:50:57 PM UTC 24 2888270300 ps
T457 /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/3.flash_ctrl_rw_evict_all_en.2585055054 Sep 09 05:50:04 PM UTC 24 Sep 09 05:50:58 PM UTC 24 31835000 ps
T421 /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/3.flash_ctrl_re_evict.1032222686 Sep 09 05:50:14 PM UTC 24 Sep 09 05:51:01 PM UTC 24 61875600 ps
T285 /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/0.flash_ctrl_error_prog_win.4081478633 Sep 09 05:32:58 PM UTC 24 Sep 09 05:51:04 PM UTC 24 742991700 ps
T458 /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/3.flash_ctrl_connect.1293842737 Sep 09 05:50:49 PM UTC 24 Sep 09 05:51:11 PM UTC 24 40404300 ps
T326 /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/3.flash_ctrl_phy_host_grant_err.3369721351 Sep 09 05:50:58 PM UTC 24 Sep 09 05:51:23 PM UTC 24 71919600 ps
T280 /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/3.flash_ctrl_lcmgr_intg.291812739 Sep 09 05:51:05 PM UTC 24 Sep 09 05:51:23 PM UTC 24 54223700 ps
T227 /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/3.flash_ctrl_phy_ack_consistency.3759564762 Sep 09 05:51:00 PM UTC 24 Sep 09 05:51:26 PM UTC 24 194684200 ps
T459 /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/3.flash_ctrl_config_regwen.2998106232 Sep 09 05:51:02 PM UTC 24 Sep 09 05:51:28 PM UTC 24 106130100 ps
T76 /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/3.flash_ctrl_phy_arb_redun.53379701 Sep 09 05:50:52 PM UTC 24 Sep 09 05:51:32 PM UTC 24 886537500 ps
T416 /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/3.flash_ctrl_fs_sup.3121562705 Sep 09 05:50:51 PM UTC 24 Sep 09 05:51:39 PM UTC 24 710711800 ps
T274 /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/3.flash_ctrl_hw_read_seed_err.673942228 Sep 09 05:51:12 PM UTC 24 Sep 09 05:51:39 PM UTC 24 18510000 ps
T36 /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/3.flash_ctrl_intr_rd.3008472121 Sep 09 05:49:30 PM UTC 24 Sep 09 05:51:46 PM UTC 24 1627924300 ps
T367 /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/3.flash_ctrl_sec_info_access.2005359666 Sep 09 05:50:35 PM UTC 24 Sep 09 05:51:46 PM UTC 24 2911828400 ps
T460 /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/3.flash_ctrl_rw_derr.1257503785 Sep 09 05:48:57 PM UTC 24 Sep 09 05:51:47 PM UTC 24 14919659400 ps
T461 /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/3.flash_ctrl_ro_derr.771905865 Sep 09 05:48:51 PM UTC 24 Sep 09 05:51:48 PM UTC 24 1673499700 ps
T439 /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/3.flash_ctrl_oversize_error.344542370 Sep 09 05:49:08 PM UTC 24 Sep 09 05:51:51 PM UTC 24 2245534600 ps
T462 /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/3.flash_ctrl_alert_test.1081145347 Sep 09 05:51:24 PM UTC 24 Sep 09 05:51:52 PM UTC 24 101946100 ps
T230 /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/2.flash_ctrl_erase_suspend.980328821 Sep 09 05:41:02 PM UTC 24 Sep 09 05:51:56 PM UTC 24 5504250900 ps
T463 /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/3.flash_ctrl_intr_rd_slow_flash.1916443870 Sep 09 05:49:36 PM UTC 24 Sep 09 05:52:01 PM UTC 24 23780243900 ps
T464 /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/4.flash_ctrl_sw_op.3737825439 Sep 09 05:51:33 PM UTC 24 Sep 09 05:52:07 PM UTC 24 39300000 ps
T465 /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/4.flash_ctrl_smoke_hw.2464421339 Sep 09 05:51:26 PM UTC 24 Sep 09 05:52:12 PM UTC 24 17858000 ps
T300 /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/3.flash_ctrl_wo.1762558815 Sep 09 05:47:55 PM UTC 24 Sep 09 05:52:18 PM UTC 24 26735453100 ps
T309 /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/3.flash_ctrl_intr_wr_slow_flash.1495899356 Sep 09 05:49:47 PM UTC 24 Sep 09 05:52:24 PM UTC 24 28781705900 ps
T306 /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/4.flash_ctrl_fetch_code.3589540089 Sep 09 05:52:01 PM UTC 24 Sep 09 05:52:31 PM UTC 24 231238100 ps
T165 /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/3.flash_ctrl_derr_detect.1473911461 Sep 09 05:49:03 PM UTC 24 Sep 09 05:52:42 PM UTC 24 645139600 ps
T276 /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/3.flash_ctrl_hw_prog_rma_wipe_err.1108597414 Sep 09 05:51:23 PM UTC 24 Sep 09 05:52:42 PM UTC 24 10039609700 ps
T232 /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/3.flash_ctrl_erase_suspend.2731133218 Sep 09 05:46:07 PM UTC 24 Sep 09 05:52:46 PM UTC 24 3205277300 ps
T286 /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/1.flash_ctrl_error_prog_win.31844294 Sep 09 05:35:52 PM UTC 24 Sep 09 05:53:08 PM UTC 24 571705200 ps
T466 /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/2.flash_ctrl_integrity.525307942 Sep 09 05:43:23 PM UTC 24 Sep 09 05:53:35 PM UTC 24 16333814500 ps
T467 /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/4.flash_ctrl_read_word_sweep_serr.3286964051 Sep 09 05:53:00 PM UTC 24 Sep 09 05:53:40 PM UTC 24 161147600 ps
T468 /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/4.flash_ctrl_smoke.1053056019 Sep 09 05:51:24 PM UTC 24 Sep 09 05:53:43 PM UTC 24 34009300 ps
T156 /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/4.flash_ctrl_invalid_op.3602010185 Sep 09 05:52:32 PM UTC 24 Sep 09 05:53:51 PM UTC 24 6097648900 ps
T126 /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/2.flash_ctrl_hw_rma_reset.3315702952 Sep 09 05:41:15 PM UTC 24 Sep 09 05:53:52 PM UTC 24 40120284400 ps
T81 /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/1.flash_ctrl_rma_err.3875281456 Sep 09 05:40:23 PM UTC 24 Sep 09 05:54:15 PM UTC 24 41784884200 ps
T469 /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/4.flash_ctrl_read_word_sweep_derr.2348473879 Sep 09 05:53:41 PM UTC 24 Sep 09 05:54:16 PM UTC 24 31629800 ps
T470 /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/4.flash_ctrl_hw_sec_otp.1357294376 Sep 09 05:51:47 PM UTC 24 Sep 09 05:54:16 PM UTC 24 1431501100 ps
T471 /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/4.flash_ctrl_rd_buff_evict.3464724584 Sep 09 05:51:41 PM UTC 24 Sep 09 05:54:18 PM UTC 24 763830800 ps
T157 /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/2.flash_ctrl_rand_ops.1774167167 Sep 09 05:40:49 PM UTC 24 Sep 09 05:54:34 PM UTC 24 266259600 ps
T164 /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/4.flash_ctrl_mid_op_rst.3077782859 Sep 09 05:52:43 PM UTC 24 Sep 09 05:54:40 PM UTC 24 922857900 ps
T472 /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/4.flash_ctrl_serr_address.2798136090 Sep 09 05:53:40 PM UTC 24 Sep 09 05:54:43 PM UTC 24 434068000 ps
T473 /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/4.flash_ctrl_host_dir_rd.1592321932 Sep 09 05:51:40 PM UTC 24 Sep 09 05:54:57 PM UTC 24 74125300 ps
T474 /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/4.flash_ctrl_wo.2612911905 Sep 09 05:52:43 PM UTC 24 Sep 09 05:55:07 PM UTC 24 2600581700 ps
T475 /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/4.flash_ctrl_phy_arb.2349152661 Sep 09 05:51:47 PM UTC 24 Sep 09 05:55:11 PM UTC 24 136738300 ps
T307 /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/4.flash_ctrl_otp_reset.1820466398 Sep 09 05:51:52 PM UTC 24 Sep 09 05:55:15 PM UTC 24 88671000 ps
T476 /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/4.flash_ctrl_serr_counter.1956957297 Sep 09 05:53:36 PM UTC 24 Sep 09 05:55:17 PM UTC 24 1024455400 ps
T477 /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/4.flash_ctrl_ro.469065461 Sep 09 05:52:47 PM UTC 24 Sep 09 05:55:21 PM UTC 24 1131055100 ps
T478 /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/4.flash_ctrl_intr_wr.1378388805 Sep 09 05:54:19 PM UTC 24 Sep 09 05:55:31 PM UTC 24 2669184500 ps
T229 /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/4.flash_ctrl_mp_regions.1295260571 Sep 09 05:51:57 PM UTC 24 Sep 09 05:55:33 PM UTC 24 3845873000 ps
T433 /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/4.flash_ctrl_rw_evict.302281389 Sep 09 05:54:44 PM UTC 24 Sep 09 05:55:38 PM UTC 24 69012800 ps
T479 /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/4.flash_ctrl_connect.1772479535 Sep 09 05:55:17 PM UTC 24 Sep 09 05:55:43 PM UTC 24 13725500 ps
T480 /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/4.flash_ctrl_ro_serr.3161976382 Sep 09 05:53:02 PM UTC 24 Sep 09 05:55:45 PM UTC 24 2615828900 ps
T308 /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/4.flash_ctrl_rw_evict_all_en.558607476 Sep 09 05:54:58 PM UTC 24 Sep 09 05:55:47 PM UTC 24 42704600 ps
T105 /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/4.flash_ctrl_disable.3999616267 Sep 09 05:55:07 PM UTC 24 Sep 09 05:55:48 PM UTC 24 10705200 ps
T73 /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/4.flash_ctrl_phy_arb_redun.1210476561 Sep 09 05:55:31 PM UTC 24 Sep 09 05:55:51 PM UTC 24 894006600 ps
T481 /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/4.flash_ctrl_config_regwen.1214474081 Sep 09 05:55:43 PM UTC 24 Sep 09 05:56:01 PM UTC 24 71973300 ps
T13 /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/4.flash_ctrl_phy_host_grant_err.1097048969 Sep 09 05:55:35 PM UTC 24 Sep 09 05:56:02 PM UTC 24 37476400 ps
T482 /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/3.flash_ctrl_rw.4115529894 Sep 09 05:48:02 PM UTC 24 Sep 09 05:56:02 PM UTC 24 4142696500 ps
T417 /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/4.flash_ctrl_fs_sup.1768169245 Sep 09 05:55:22 PM UTC 24 Sep 09 05:56:07 PM UTC 24 462703400 ps
T483 /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/4.flash_ctrl_lcmgr_intg.2586007530 Sep 09 05:55:45 PM UTC 24 Sep 09 05:56:10 PM UTC 24 15315500 ps
T484 /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/4.flash_ctrl_re_evict.1303969858 Sep 09 05:55:07 PM UTC 24 Sep 09 05:56:10 PM UTC 24 63881400 ps
T485 /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/4.flash_ctrl_alert_test.2713898568 Sep 09 05:55:52 PM UTC 24 Sep 09 05:56:13 PM UTC 24 154779700 ps
T349 /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/4.flash_ctrl_hw_read_seed_err.1222620753 Sep 09 05:55:48 PM UTC 24 Sep 09 05:56:14 PM UTC 24 46330300 ps
T225 /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/4.flash_ctrl_sec_info_access.469469252 Sep 09 05:55:12 PM UTC 24 Sep 09 05:56:31 PM UTC 24 886478700 ps
T209 /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/4.flash_ctrl_oversize_error.807383684 Sep 09 05:54:16 PM UTC 24 Sep 09 05:56:37 PM UTC 24 954730000 ps
T486 /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/1.flash_ctrl_rand_ops.3730941250 Sep 09 05:35:09 PM UTC 24 Sep 09 05:56:39 PM UTC 24 451648900 ps
T64 /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/5.flash_ctrl_fetch_code.1519313067 Sep 09 05:56:13 PM UTC 24 Sep 09 05:56:39 PM UTC 24 309906100 ps
T37 /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/4.flash_ctrl_intr_rd.4166578093 Sep 09 05:54:17 PM UTC 24 Sep 09 05:56:50 PM UTC 24 5725894200 ps
T203 /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/4.flash_ctrl_ro_derr.1309816142 Sep 09 05:53:44 PM UTC 24 Sep 09 05:57:07 PM UTC 24 11761225600 ps
0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%