Unified Coverage Report :: Group :: cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=5}

Group : cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=5}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
88.24	1	100	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

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Summary for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=5}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	10	0	10	100.00
Crosses	24	4	20	83.33

Variables for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=5}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	6	0	6	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=5}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_cg_cc	24	4	20	83.33	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	6	0	6	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	347397	1		T1	2		T2	1		T3	2
all_values[1]	347397	1		T1	2		T2	1		T3	2
all_values[2]	347397	1		T1	2		T2	1		T3	2
all_values[3]	347397	1		T1	2		T2	1		T3	2
all_values[4]	347397	1		T1	2		T2	1		T3	2
all_values[5]	347397	1		T1	2		T2	1		T3	2

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Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	701102	1		T1	12		T2	6		T3	12
auto[1]	1383280	1		T29	6200		T32	4560		T30	5920

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Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	1019753	1		T1	7		T2	4		T3	7
auto[1]	1064629	1		T1	5		T2	2		T3	5

---

Summary for Cross intr_cg_cc

Samples crossed: cp_intr cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	24	4	20	83.33	4

Automatically Generated Cross Bins for intr_cg_cc

Element holes

cp_intr	cp_intr_en	cp_intr_state	COUNT	AT LEAST	NUMBER
[all_values[0] , all_values[1]]	*	[auto[0]]	--	--	4

Covered bins

cp_intr	cp_intr_en	cp_intr_state	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[1]	347249	1		T1	2		T2	1		T3	2
all_values[0]	auto[1]	auto[1]	148	1		T251	5		T252	3		T328	1
all_values[1]	auto[0]	auto[1]	347225	1		T1	2		T2	1		T3	2
all_values[1]	auto[1]	auto[1]	172	1		T251	4		T328	5		T329	4
all_values[2]	auto[0]	auto[0]	1598	1		T1	2		T2	1		T3	2
all_values[2]	auto[0]	auto[1]	45	1		T331	1		T330	2		T332	1
all_values[2]	auto[1]	auto[0]	345689	1		T29	1550		T32	1140		T30	1480
all_values[2]	auto[1]	auto[1]	65	1		T251	1		T252	1		T328	2
all_values[3]	auto[0]	auto[0]	1608	1		T1	2		T2	1		T3	2
all_values[3]	auto[0]	auto[1]	46	1		T252	2		T328	1		T329	2
all_values[3]	auto[1]	auto[0]	78675	1		T29	1550		T32	570		T30	1480
all_values[3]	auto[1]	auto[1]	267068	1		T32	570		T38	1055		T40	1417
all_values[4]	auto[0]	auto[0]	1153	1		T1	1		T2	1		T3	1
all_values[4]	auto[0]	auto[1]	528	1		T1	1		T3	1		T7	1
all_values[4]	auto[1]	auto[0]	243804	1		T29	1		T32	570		T30	1
all_values[4]	auto[1]	auto[1]	101912	1		T29	1549		T32	570		T30	1479
all_values[5]	auto[0]	auto[0]	1551	1		T1	2		T2	1		T3	2
all_values[5]	auto[0]	auto[1]	99	1		T16	1		T41	1		T87	1
all_values[5]	auto[1]	auto[0]	345675	1		T29	1550		T32	1140		T30	1480
all_values[5]	auto[1]	auto[1]	72	1		T252	1		T328	3		T329	3