Unified Coverage Report :: Group :: flash_ctrl_env_pkg::flash_ctrl_env_cov::control_cg

Group : flash_ctrl_env_pkg::flash_ctrl_env_cov::control_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/default/sim-vcs/../src/lowrisc_dv_flash_ctrl_env_0.1/flash_ctrl_env_cov.sv

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Summary for Group flash_ctrl_env_pkg::flash_ctrl_env_cov::control_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	15	0	15	100.00
Crosses	16	0	16	100.00

Variables for Group flash_ctrl_env_pkg::flash_ctrl_env_cov::control_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
erase_cp	2	0	2	100.00	100	1	1	0
op_cp	4	0	4	100.00	100	1	1	0
op_evict_cp	5	0	5	100.00	100	1	1	0
part_cp	4	0	4	100.00	100	1	1	0

Crosses for Group flash_ctrl_env_pkg::flash_ctrl_env_cov::control_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
op_part_cross	16	0	16	100.00	100	1	1	0

Summary for Variable erase_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for erase_cp

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[FlashErasePage]	231385	1		T3	14		T7	4		T14	41
auto[FlashEraseBank]	259946	1		T1	20		T14	9		T19	20

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Summary for Variable op_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for op_cp

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[FlashOpRead]	254607	1		T1	20		T7	2		T14	50
auto[FlashOpProgram]	216856	1		T3	14		T7	1		T21	1
auto[FlashOpErase]	15868	1		T7	1		T8	1		T26	15
auto[FlashOpInvalid]	4000	1		T71	200		T83	200		T148	200

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Summary for Variable op_evict_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	5	0	5	100.00

User Defined Bins for op_evict_cp

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
op[FlashOpRead]	254607	1		T1	20		T7	2		T14	50
op[FlashOpProgram]	216856	1		T3	14		T7	1		T21	1
op[FlashOpErase]	15868	1		T7	1		T8	1		T26	15
read_erase_read	559	1		T26	15		T62	7		T52	2
read_prog_read	804	1		T15	4		T58	4		T25	1

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Summary for Variable part_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for part_cp

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[FlashPartData]	343203	1		T1	20		T3	14		T7	4
auto[FlashPartInfo]	140693	1		T58	119		T8	1		T25	6
auto[FlashPartInfo1]	2138	1		T49	2		T62	1		T41	2
auto[FlashPartInfo2]	5297	1		T58	5		T25	1		T26	5

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Summary for Cross op_part_cross

Samples crossed: part_cp op_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for op_part_cross

Bins

part_cp	op_cp	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[FlashPartData]	auto[FlashOpRead]	178890	1		T1	20		T7	2		T14	50
auto[FlashPartData]	auto[FlashOpProgram]	159648	1		T3	14		T7	1		T21	1
auto[FlashPartData]	auto[FlashOpErase]	2681	1		T7	1		T26	2		T62	29
auto[FlashPartData]	auto[FlashOpInvalid]	1984	1		T71	110		T83	92		T148	94
auto[FlashPartInfo]	auto[FlashOpRead]	71943	1		T58	89		T25	6		T26	31
auto[FlashPartInfo]	auto[FlashOpProgram]	55263	1		T58	30		T27	1		T16	47
auto[FlashPartInfo]	auto[FlashOpErase]	12817	1		T8	1		T26	11		T63	136
auto[FlashPartInfo]	auto[FlashOpInvalid]	670	1		T71	34		T83	18		T148	30
auto[FlashPartInfo1]	auto[FlashOpRead]	1293	1		T49	2		T41	2		T71	32
auto[FlashPartInfo1]	auto[FlashOpProgram]	162	1		T151	32		T131	1		T135	32
auto[FlashPartInfo1]	auto[FlashOpErase]	3	1		T62	1		T414	1		T415	1
auto[FlashPartInfo1]	auto[FlashOpInvalid]	680	1		T71	32		T83	38		T148	40
auto[FlashPartInfo2]	auto[FlashOpRead]	2481	1		T58	2		T25	1		T26	3
auto[FlashPartInfo2]	auto[FlashOpProgram]	1783	1		T58	3		T16	3		T29	27
auto[FlashPartInfo2]	auto[FlashOpErase]	367	1		T26	2		T71	12		T83	26
auto[FlashPartInfo2]	auto[FlashOpInvalid]	666	1		T71	24		T83	52		T148	36