Unified Coverage Report :: Group :: flash_ctrl_env_pkg::flash_ctrl_env_cov::eviction_cg

Group : flash_ctrl_env_pkg::flash_ctrl_env_cov::eviction_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/default/sim-vcs/../src/lowrisc_dv_flash_ctrl_env_0.1/flash_ctrl_env_cov.sv

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Summary for Group flash_ctrl_env_pkg::flash_ctrl_env_cov::eviction_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	10	0	10	100.00
Crosses	32	0	32	100.00

Variables for Group flash_ctrl_env_pkg::flash_ctrl_env_cov::eviction_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
evic_cfg_cp	4	0	4	100.00	100	1	1	4
evic_idx_cp	4	0	4	100.00	100	1	1	0
evic_op_cp	2	0	2	100.00	100	1	1	0

Crosses for Group flash_ctrl_env_pkg::flash_ctrl_env_cov::eviction_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
evic_all_cross	32	0	32	100.00	100	1	1	0

Summary for Variable evic_cfg_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for evic_cfg_cp

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	30671	1		T7	4		T15	20		T63	272
auto[1]	39	1		T26	3		T416	1		T417	4
auto[2]	49	1		T26	5		T146	6		T70	12
auto[3]	215	1		T25	1		T26	4		T27	1

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Summary for Variable evic_idx_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for evic_idx_cp

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
evic_idx[0]	7747	1		T7	1		T15	5		T26	1
evic_idx[1]	7740	1		T7	1		T15	5		T26	3
evic_idx[2]	7753	1		T7	1		T15	5		T25	1
evic_idx[3]	7734	1		T7	1		T15	5		T26	3

---

Summary for Variable evic_op_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for evic_op_cp

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
evic_op[1]	29980	1		T7	4		T26	12		T63	272
evic_op[2]	320	1		T15	20		T25	1		T27	1

---

Summary for Cross evic_all_cross

Samples crossed: evic_idx_cp evic_op_cp evic_cfg_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	32	0	32	100.00

Automatically Generated Cross Bins for evic_all_cross

Bins

evic_idx_cp	evic_op_cp	evic_cfg_cp	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
evic_idx[0]	evic_op[1]	auto[0]	7442	1		T7	1		T63	68		T71	84
evic_idx[0]	evic_op[1]	auto[1]	5	1		T418	1		T419	4		-	-
evic_idx[0]	evic_op[1]	auto[2]	5	1		T146	1		T420	1		T418	1
evic_idx[0]	evic_op[1]	auto[3]	40	1		T26	1		T146	3		T421	3
evic_idx[0]	evic_op[2]	auto[0]	66	1		T15	5		T52	4		T245	5
evic_idx[0]	evic_op[2]	auto[1]	2	1		T417	1		T422	1		-	-
evic_idx[0]	evic_op[2]	auto[2]	2	1		T423	1		T424	1		-	-
evic_idx[0]	evic_op[2]	auto[3]	15	1		T27	1		T212	1		T43	1
evic_idx[1]	evic_op[1]	auto[0]	7439	1		T7	1		T63	68		T71	84
evic_idx[1]	evic_op[1]	auto[1]	6	1		T418	1		T425	2		T419	3
evic_idx[1]	evic_op[1]	auto[2]	6	1		T26	2		T146	1		T420	1
evic_idx[1]	evic_op[1]	auto[3]	43	1		T26	1		T146	3		T213	1
evic_idx[1]	evic_op[2]	auto[0]	61	1		T15	5		T52	4		T245	5
evic_idx[1]	evic_op[2]	auto[1]	2	1		T417	1		T426	1		-	-
evic_idx[1]	evic_op[2]	auto[2]	3	1		T427	1		T424	1		T422	1
evic_idx[1]	evic_op[2]	auto[3]	12	1		T212	1		T428	1		T429	1
evic_idx[2]	evic_op[1]	auto[0]	7440	1		T7	1		T63	68		T71	84
evic_idx[2]	evic_op[1]	auto[1]	9	1		T26	2		T425	3		T419	4
evic_idx[2]	evic_op[1]	auto[2]	6	1		T26	2		T146	1		T420	1
evic_idx[2]	evic_op[1]	auto[3]	49	1		T26	1		T146	4		T213	1
evic_idx[2]	evic_op[2]	auto[0]	63	1		T15	5		T52	4		T245	5
evic_idx[2]	evic_op[2]	auto[1]	4	1		T416	1		T417	1		T430	1
evic_idx[2]	evic_op[2]	auto[2]	2	1		T431	1		T432	1		-	-
evic_idx[2]	evic_op[2]	auto[3]	12	1		T25	1		T212	1		T433	1
evic_idx[3]	evic_op[1]	auto[0]	7438	1		T7	1		T63	68		T71	84
evic_idx[3]	evic_op[1]	auto[1]	9	1		T26	1		T434	2		T425	3
evic_idx[3]	evic_op[1]	auto[2]	8	1		T26	1		T146	3		T420	1
evic_idx[3]	evic_op[1]	auto[3]	35	1		T26	1		T146	2		T421	2
evic_idx[3]	evic_op[2]	auto[0]	64	1		T15	5		T52	4		T245	5
evic_idx[3]	evic_op[2]	auto[1]	2	1		T417	1		T435	1		-	-
evic_idx[3]	evic_op[2]	auto[2]	1	1		T431	1		-	-		-	-
evic_idx[3]	evic_op[2]	auto[3]	9	1		T212	1		T436	1		T437	1