Unified Coverage Report :: Group :: flash_ctrl_env_pkg::flash_ctrl_env_cov::msgfifo_level_cg

Group : flash_ctrl_env_pkg::flash_ctrl_env_cov::msgfifo_level_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
83.33	1	100	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/default/sim-vcs/../src/lowrisc_dv_flash_ctrl_env_0.1/flash_ctrl_env_cov.sv

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Summary for Group flash_ctrl_env_pkg::flash_ctrl_env_cov::msgfifo_level_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	18	3	15	83.33

Variables for Group flash_ctrl_env_pkg::flash_ctrl_env_cov::msgfifo_level_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
prog_lvl_cp	3	3	0	0.00	100	1	1	0
rd_lvl_cp	15	0	15	100.00	100	1	1	0

Summary for Variable prog_lvl_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	3	0	0.00

User Defined Bins for prog_lvl_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER
prog_lvl[1]	0	1	1
prog_lvl[2]	0	1	1
prog_lvl[3]	0	1	1

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Summary for Variable rd_lvl_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	15	0	15	100.00

User Defined Bins for rd_lvl_cp

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
rd_lvl[1]	35064	1		T198	2555		T338	15349		T95	14700
rd_lvl[2]	47178	1		T198	2652		T339	1281		T340	2663
rd_lvl[3]	14700	1		T341	280		T198	1594		T339	700
rd_lvl[4]	25749	1		T341	80		T198	1614		T339	117
rd_lvl[5]	19306	1		T198	1458		T339	399		T340	1770
rd_lvl[6]	16684	1		T198	31		T339	373		T342	3067
rd_lvl[7]	13411	1		T198	1436		T343	101		T339	61
rd_lvl[8]	22136	1		T198	1430		T343	29		T339	62
rd_lvl[9]	7141	1		T32	170		T40	450		T198	1709
rd_lvl[10]	7843	1		T32	398		T40	967		T198	1172
rd_lvl[11]	3420	1		T198	42		T344	230		T345	88
rd_lvl[12]	6280	1		T32	2		T38	954		T339	57
rd_lvl[13]	2990	1		T38	101		T36	297		T37	312
rd_lvl[14]	8233	1		T346	1410		T36	159		T37	140
rd_lvl[15]	1194	1		T346	334		T37	2		T347	152