Unified Coverage Report :: Group :: cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=5}

Group : cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=5}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

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Summary for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=5}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	10	0	10	100.00
Crosses	24	0	24	100.00

Variables for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=5}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr_pin	6	0	6	100.00	100	1	1	0
cp_intr_pin_value	4	0	4	100.00	100	1	1	0

Crosses for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=5}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_intr_pins_all_values	24	0	24	100.00	100	1	1	0

Summary for Variable cp_intr_pin

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	6	0	6	100.00

User Defined Bins for cp_intr_pin

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	347397	1		T1	2		T2	1		T3	2
all_pins[1]	347397	1		T1	2		T2	1		T3	2
all_pins[2]	347397	1		T1	2		T2	1		T3	2
all_pins[3]	347397	1		T1	2		T2	1		T3	2
all_pins[4]	347397	1		T1	2		T2	1		T3	2
all_pins[5]	347397	1		T1	2		T2	1		T3	2

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Summary for Variable cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for cp_intr_pin_value

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x0]	1743658	1		T1	12		T2	6		T3	12
values[0x1]	340724	1		T29	1549		T32	1140		T30	1479
transitions[0x0=>0x1]	311117	1		T29	1549		T32	1140		T30	1479
transitions[0x1=>0x0]	311104	1		T29	1549		T32	1140		T30	1479

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Summary for Cross cp_intr_pins_all_values

Samples crossed: cp_intr_pin cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	24	0	24	100.00

Automatically Generated Cross Bins for cp_intr_pins_all_values

Bins

cp_intr_pin	cp_intr_pin_value	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	values[0x0]	347249	1		T1	2		T2	1		T3	2
all_pins[0]	values[0x1]	148	1		T251	5		T252	3		T328	1
all_pins[0]	transitions[0x0=>0x1]	74	1		T251	2		T252	3		T329	1
all_pins[0]	transitions[0x1=>0x0]	98	1		T251	1		T328	4		T329	3
all_pins[1]	values[0x0]	347225	1		T1	2		T2	1		T3	2
all_pins[1]	values[0x1]	172	1		T251	4		T328	5		T329	4
all_pins[1]	transitions[0x0=>0x1]	136	1		T251	3		T328	3		T329	2
all_pins[1]	transitions[0x1=>0x0]	423	1		T347	394		T252	1		T330	1
all_pins[2]	values[0x0]	346938	1		T1	2		T2	1		T3	2
all_pins[2]	values[0x1]	459	1		T347	394		T251	1		T252	1
all_pins[2]	transitions[0x0=>0x1]	48	1		T252	1		T328	2		T329	1
all_pins[2]	transitions[0x1=>0x0]	231586	1		T32	570		T38	1055		T40	1417
all_pins[3]	values[0x0]	115400	1		T1	2		T2	1		T3	2
all_pins[3]	values[0x1]	231997	1		T32	570		T38	1055		T40	1417
all_pins[3]	transitions[0x0=>0x1]	202967	1		T32	570		T38	1055		T40	1417
all_pins[3]	transitions[0x1=>0x0]	78846	1		T29	1549		T32	570		T30	1479
all_pins[4]	values[0x0]	239521	1		T1	2		T2	1		T3	2
all_pins[4]	values[0x1]	107876	1		T29	1549		T32	570		T30	1479
all_pins[4]	transitions[0x0=>0x1]	107861	1		T29	1549		T32	570		T30	1479
all_pins[4]	transitions[0x1=>0x0]	57	1		T252	1		T328	3		T329	3
all_pins[5]	values[0x0]	347325	1		T1	2		T2	1		T3	2
all_pins[5]	values[0x1]	72	1		T252	1		T328	3		T329	3
all_pins[5]	transitions[0x0=>0x1]	31	1		T252	1		T328	1		T329	1
all_pins[5]	transitions[0x1=>0x0]	94	1		T251	4		T252	2		T330	4