Unified Coverage Report :: Group :: cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=5}

Group : cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=5}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
83.33	1	100	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=5}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	12	0	12	100.00
Crosses	36	8	28	77.78

Variables for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=5}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	6	0	6	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2
cp_intr_test	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=5}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_test_cg_cc	36	8	28	77.78	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	6	0	6	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	272	1		T251	7		T252	4		T328	4
all_values[1]	272	1		T251	7		T252	4		T328	4
all_values[2]	272	1		T251	7		T252	4		T328	4
all_values[3]	272	1		T251	7		T252	4		T328	4
all_values[4]	272	1		T251	7		T252	4		T328	4
all_values[5]	272	1		T251	7		T252	4		T328	4

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	903	1		T251	20		T252	16		T328	8
auto[1]	729	1		T251	22		T252	8		T328	16

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	563	1		T251	17		T252	10		T328	5
auto[1]	1069	1		T251	25		T252	14		T328	19

---

Summary for Variable cp_intr_test

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_test

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	988	1		T251	28		T252	15		T328	11
auto[1]	644	1		T251	14		T252	9		T328	13

---

Summary for Cross intr_test_cg_cc

Samples crossed: cp_intr cp_intr_test cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	36	8	28	77.78	8
Automatically Generated Cross Bins	36	8	28	77.78	8
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for intr_test_cg_cc

Element holes

cp_intr	cp_intr_test	cp_intr_en	cp_intr_state	COUNT	AT LEAST	NUMBER
[all_values[0] , all_values[1]]	[auto[0]]	*	[auto[0]]	--	--	4
[all_values[2] , all_values[3]]	[auto[0]]	*	[auto[1]]	--	--	4

Covered bins

cp_intr	cp_intr_test	cp_intr_en	cp_intr_state	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	auto[1]	98	1		T251	2		T252	1		T328	2
all_values[0]	auto[0]	auto[1]	auto[1]	70	1		T251	4		T252	2		T329	1
all_values[0]	auto[1]	auto[0]	auto[1]	57	1		T251	1		T252	1		T328	1
all_values[0]	auto[1]	auto[1]	auto[1]	47	1		T328	1		T329	1		T330	1
all_values[1]	auto[0]	auto[0]	auto[1]	77	1		T251	3		T252	1		T330	6
all_values[1]	auto[0]	auto[1]	auto[1]	84	1		T251	1		T328	2		T329	3
all_values[1]	auto[1]	auto[0]	auto[1]	61	1		T251	1		T252	3		T331	1
all_values[1]	auto[1]	auto[1]	auto[1]	50	1		T251	2		T328	2		T329	1
all_values[2]	auto[0]	auto[0]	auto[0]	88	1		T251	2		T252	1		T331	3
all_values[2]	auto[0]	auto[1]	auto[0]	74	1		T251	4		T252	2		T328	2
all_values[2]	auto[1]	auto[0]	auto[1]	50	1		T331	1		T330	3		T332	2
all_values[2]	auto[1]	auto[1]	auto[1]	60	1		T251	1		T252	1		T328	2
all_values[3]	auto[0]	auto[0]	auto[0]	104	1		T251	2		T252	2		T331	2
all_values[3]	auto[0]	auto[1]	auto[0]	71	1		T251	2		T328	3		T329	1
all_values[3]	auto[1]	auto[0]	auto[1]	53	1		T251	1		T252	2		T328	1
all_values[3]	auto[1]	auto[1]	auto[1]	44	1		T251	2		T329	1		T330	1
all_values[4]	auto[0]	auto[0]	auto[0]	85	1		T251	2		T252	3		T329	2
all_values[4]	auto[0]	auto[0]	auto[1]	26	1		T251	1		T328	1		T333	2
all_values[4]	auto[0]	auto[1]	auto[0]	40	1		T251	2		T329	1		T332	1
all_values[4]	auto[0]	auto[1]	auto[1]	15	1		T330	1		T334	1		T335	1
all_values[4]	auto[1]	auto[0]	auto[1]	60	1		T251	1		T328	3		T330	4
all_values[4]	auto[1]	auto[1]	auto[1]	46	1		T251	1		T252	1		T329	1
all_values[5]	auto[0]	auto[0]	auto[0]	53	1		T251	1		T332	3		T336	1
all_values[5]	auto[0]	auto[0]	auto[1]	30	1		T252	1		T331	1		T330	3
all_values[5]	auto[0]	auto[1]	auto[0]	48	1		T251	2		T252	2		T329	1
all_values[5]	auto[0]	auto[1]	auto[1]	25	1		T328	1		T329	1		T337	1
all_values[5]	auto[1]	auto[0]	auto[1]	61	1		T251	3		T252	1		T331	1
all_values[5]	auto[1]	auto[1]	auto[1]	55	1		T251	1		T328	3		T329	2

User Defined Cross Bins for intr_test_cg_cc

Excluded/Illegal bins

NAME	COUNT	STATUS
test_1_state_0	0	Illegal