Unified Coverage Report :: Group :: cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

Group : cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

2 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_intg_err_mem_subword_cgs_wrap[flash_ctrl_core_reg_block]	100.00	1	100	1	64	64
tl_intg_err_mem_subword_cgs_wrap[flash_ctrl_eflash_reg_block]	100.00	1	100	1	64	64

---

Group Instance : tl_intg_err_mem_subword_cgs_wrap[flash_ctrl_core_reg_block]

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_intg_err_mem_subword_cgs_wrap[flash_ctrl_core_reg_block]

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tl_intg_err_mem_subword_cgs_wrap[flash_ctrl_core_reg_block]

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_num_enable_bytes	2	0	2	100.00	100	1	1	0
cp_tl_intg_err_type	4	0	4	100.00	100	1	1	0
cp_write	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tl_intg_err_mem_subword_cgs_wrap[flash_ctrl_core_reg_block]

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	16	0	16	100.00	100	1	1	0

---

Group Instance : tl_intg_err_mem_subword_cgs_wrap[flash_ctrl_eflash_reg_block]

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_intg_err_mem_subword_cgs_wrap[flash_ctrl_eflash_reg_block]

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tl_intg_err_mem_subword_cgs_wrap[flash_ctrl_eflash_reg_block]

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_num_enable_bytes	2	0	2	100.00	100	1	1	0
cp_tl_intg_err_type	4	0	4	100.00	100	1	1	0
cp_write	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tl_intg_err_mem_subword_cgs_wrap[flash_ctrl_eflash_reg_block]

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	16	0	16	100.00	100	1	1	0

Summary for Variable cp_num_num_enable_bytes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_num_enable_bytes

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
partial	29125767	1		T1	288		T2	1137		T3	292
full_word	7453598	1		T1	238		T2	161		T3	245

---

Summary for Variable cp_tl_intg_err_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_tl_intg_err_type

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	36579085	1		T1	526		T2	1298		T3	537
auto[TlIntgErrCmd]	100	1		T263	5		T264	4		T265	4
auto[TlIntgErrData]	80	1		T263	3		T264	2		T265	2
auto[TlIntgErrBoth]	100	1		T263	2		T264	4		T265	4

---

Summary for Variable cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_write

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	32318603	1		T1	420		T2	1132		T3	431
auto[1]	4260762	1		T1	106		T2	166		T3	106

---

Summary for Cross cr_all

Samples crossed: cp_tl_intg_err_type cp_num_num_enable_bytes cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_tl_intg_err_type	cp_num_num_enable_bytes	cp_write	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	partial	auto[0]	28458673	1		T1	262		T2	1122		T3	272
auto[TlIntgErrNone]	partial	auto[1]	666844	1		T1	26		T2	15		T3	20
auto[TlIntgErrNone]	full_word	auto[0]	3859803	1		T1	158		T2	10		T3	159
auto[TlIntgErrNone]	full_word	auto[1]	3593765	1		T1	80		T2	151		T3	86
auto[TlIntgErrCmd]	partial	auto[0]	30	1		T265	1		T375	3		T376	2
auto[TlIntgErrCmd]	partial	auto[1]	58	1		T263	5		T264	4		T265	2
auto[TlIntgErrCmd]	full_word	auto[0]	7	1		T265	1		T375	1		T383	2
auto[TlIntgErrCmd]	full_word	auto[1]	5	1		T379	1		T373	1		T384	1
auto[TlIntgErrData]	partial	auto[0]	36	1		T263	1		T265	2		T375	2
auto[TlIntgErrData]	partial	auto[1]	36	1		T263	1		T264	1		T375	1
auto[TlIntgErrData]	full_word	auto[0]	4	1		T263	1		T264	1		T377	1
auto[TlIntgErrData]	full_word	auto[1]	4	1		T378	1		T374	1		T385	1
auto[TlIntgErrBoth]	partial	auto[0]	46	1		T264	2		T265	1		T375	1
auto[TlIntgErrBoth]	partial	auto[1]	44	1		T263	2		T264	2		T265	2
auto[TlIntgErrBoth]	full_word	auto[0]	4	1		T265	1		T377	1		T380	1
auto[TlIntgErrBoth]	full_word	auto[1]	6	1		T374	1		T380	1		T386	1

Summary for Variable cp_num_num_enable_bytes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_num_enable_bytes

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
partial	20307	1		T134	517		T135	164		T138	1380
full_word	3730774	1		T5	8		T8	392		T9	10

---

Summary for Variable cp_tl_intg_err_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_tl_intg_err_type

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	3750830	1		T5	8		T8	392		T9	10
auto[TlIntgErrCmd]	82	1		T263	1		T265	1		T375	2
auto[TlIntgErrData]	86	1		T263	6		T264	5		T265	4
auto[TlIntgErrBoth]	83	1		T263	3		T264	4		T265	4

---

Summary for Variable cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_write

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	3725211	1		T5	8		T8	392		T9	10
auto[1]	25870	1		T134	731		T135	194		T138	1579

---

Summary for Cross cr_all

Samples crossed: cp_tl_intg_err_type cp_num_num_enable_bytes cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_tl_intg_err_type	cp_num_num_enable_bytes	cp_write	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	partial	auto[0]	1447	1		T134	59		T135	10		T138	134
auto[TlIntgErrNone]	partial	auto[1]	18636	1		T134	458		T135	154		T138	1246
auto[TlIntgErrNone]	full_word	auto[0]	3723666	1		T5	8		T8	392		T9	10
auto[TlIntgErrNone]	full_word	auto[1]	7081	1		T134	273		T135	40		T138	333
auto[TlIntgErrCmd]	partial	auto[0]	26	1		T265	1		T375	1		T376	2
auto[TlIntgErrCmd]	partial	auto[1]	48	1		T263	1		T375	1		T376	3
auto[TlIntgErrCmd]	full_word	auto[0]	3	1		T380	2		T387	1		-	-
auto[TlIntgErrCmd]	full_word	auto[1]	5	1		T378	1		T379	1		T384	1
auto[TlIntgErrData]	partial	auto[0]	40	1		T263	1		T264	2		T265	2
auto[TlIntgErrData]	partial	auto[1]	37	1		T263	3		T264	2		T265	2
auto[TlIntgErrData]	full_word	auto[0]	3	1		T264	1		T375	1		T383	1
auto[TlIntgErrData]	full_word	auto[1]	6	1		T263	2		T376	1		T378	1
auto[TlIntgErrBoth]	partial	auto[0]	23	1		T263	1		T264	2		T265	1
auto[TlIntgErrBoth]	partial	auto[1]	50	1		T263	2		T264	2		T265	2
auto[TlIntgErrBoth]	full_word	auto[0]	3	1		T265	1		T377	1		T382	1
auto[TlIntgErrBoth]	full_word	auto[1]	7	1		T379	1		T380	1		T383	3