Unified Coverage Report :: Module :: prim_arbiter_tree

Module : prim_arbiter_tree

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.96	96.15	97.92			100.00	93.75

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_tree.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_eflash.gen_flash_cores[0].u_core.u_rd.u_valid_random	92.50	92.31	97.69			100.00	80.00
tb.dut.u_eflash.gen_flash_cores[1].u_core.u_rd.u_valid_random	92.50	92.31	97.69			100.00	80.00
tb.dut.u_eflash.u_scramble.u_prim_arbiter_tree_op.gen_input_bufs[0].gen_rr_arbiter.u_arb	95.50	100.00	88.24			100.00	93.75
tb.dut.u_eflash.u_scramble.u_prim_arbiter_tree_op.gen_input_bufs[1].gen_rr_arbiter.u_arb	97.46	100.00	96.08			100.00	93.75
tb.dut.u_eflash.u_scramble.u_prim_arbiter_tree_calc.gen_input_bufs[1].gen_rr_arbiter.u_arb	97.86	100.00	97.67			100.00	93.75
tb.dut.u_eflash.u_scramble.u_prim_arbiter_tree_calc.gen_input_bufs[0].gen_rr_arbiter.u_arb	98.44	100.00	100.00			100.00	93.75

---

Module Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_rd.u_valid_random

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
92.50	92.31	97.69			100.00	80.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
92.50	92.31	97.69			100.00	80.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
97.82	100.00	91.27			100.00	100.00	u_rd

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_rd.u_valid_random

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
92.50	92.31	97.69			100.00	80.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
92.50	92.31	97.69			100.00	80.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
97.82	100.00	91.27			100.00	100.00	u_rd

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_eflash.u_scramble.u_prim_arbiter_tree_op.gen_input_bufs[0].gen_rr_arbiter.u_arb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
95.50	100.00	88.24			100.00	93.75

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
95.50	100.00	88.24			100.00	93.75

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00			100.00		u_prim_arbiter_tree_op

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_eflash.u_scramble.u_prim_arbiter_tree_op.gen_input_bufs[1].gen_rr_arbiter.u_arb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.46	100.00	96.08			100.00	93.75

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.46	100.00	96.08			100.00	93.75

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00			100.00		u_prim_arbiter_tree_op

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_eflash.u_scramble.u_prim_arbiter_tree_calc.gen_input_bufs[1].gen_rr_arbiter.u_arb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.86	100.00	97.67			100.00	93.75

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.86	100.00	97.67			100.00	93.75

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00			100.00		u_prim_arbiter_tree_calc

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_eflash.u_scramble.u_prim_arbiter_tree_calc.gen_input_bufs[0].gen_rr_arbiter.u_arb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.44	100.00	100.00			100.00	93.75

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.44	100.00	100.00			100.00	93.75

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00			100.00		u_prim_arbiter_tree_calc

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Module : prim_arbiter_tree ( parameter N=4,DW=2,EnDataPort=0,IdxW=2,gen_normal_case.gen_tree[0].gen_level[0].Pa=0,gen_normal_case.gen_tree[0].gen_level[0].C0=1,gen_normal_case.gen_tree[0].gen_level[0].C1=2,gen_normal_case.gen_tree[1].gen_level[0].Pa=1,gen_normal_case.gen_tree[1].gen_level[0].C0=3,gen_normal_case.gen_tree[1].gen_level[0].C1=4,gen_normal_case.gen_tree[1].gen_level[1].Pa=2,gen_normal_case.gen_tree[1].gen_level[1].C0=5,gen_normal_case.gen_tree[1].gen_level[1].C1=6,gen_normal_case.gen_tree[2].gen_level[0].Pa=3,gen_normal_case.gen_tree[2].gen_level[0].C0=7,gen_normal_case.gen_tree[2].gen_level[0].C1=8,gen_normal_case.gen_tree[2].gen_level[1].Pa=4,gen_normal_case.gen_tree[2].gen_level[1].C0=9,gen_normal_case.gen_tree[2].gen_level[1].C1=10,gen_normal_case.gen_tree[2].gen_level[2].Pa=5,gen_normal_case.gen_tree[2].gen_level[2].C0=11,gen_normal_case.gen_tree[2].gen_level[2].C1=12,gen_normal_case.gen_tree[2].gen_level[3].Pa=6,gen_normal_case.gen_tree[2].gen_level[3].C0=13,gen_normal_case.gen_tree[2].gen_level[3].C1=14 )
Line Coverage for Module self-instances :

SCORE	LINE
92.50	92.31

tb.dut.u_eflash.gen_flash_cores[0].u_core.u_rd.u_valid_random

SCORE	LINE
92.50	92.31

tb.dut.u_eflash.gen_flash_cores[1].u_core.u_rd.u_valid_random

	Line No.	Total	Covered	Percent
TOTAL		52	48	92.31
CONT_ASSIGN	62	0	0
CONT_ASSIGN	112	1	1	100.00
CONT_ASSIGN	112	1	1	100.00
CONT_ASSIGN	112	1	1	100.00
CONT_ASSIGN	112	1	1	100.00
CONT_ASSIGN	118	1	1	100.00
CONT_ASSIGN	118	1	1	100.00
CONT_ASSIGN	118	1	1	100.00
CONT_ASSIGN	118	1	1	100.00
CONT_ASSIGN	122	1	0	0.00
CONT_ASSIGN	122	1	0	0.00
CONT_ASSIGN	122	1	0	0.00
CONT_ASSIGN	122	1	0	0.00
CONT_ASSIGN	126	1	1	100.00
CONT_ASSIGN	126	1	1	100.00
CONT_ASSIGN	126	1	1	100.00
CONT_ASSIGN	126	1	1	100.00
CONT_ASSIGN	128	1	1	100.00
CONT_ASSIGN	128	1	1	100.00
CONT_ASSIGN	128	1	1	100.00
CONT_ASSIGN	128	1	1	100.00
CONT_ASSIGN	148	1	1	100.00
CONT_ASSIGN	148	1	1	100.00
CONT_ASSIGN	148	1	1	100.00
CONT_ASSIGN	150	1	1	100.00
CONT_ASSIGN	150	1	1	100.00
CONT_ASSIGN	150	1	1	100.00
CONT_ASSIGN	151	1	1	100.00
CONT_ASSIGN	151	1	1	100.00
CONT_ASSIGN	151	1	1	100.00
CONT_ASSIGN	155	1	1	100.00
CONT_ASSIGN	155	1	1	100.00
CONT_ASSIGN	155	1	1	100.00
CONT_ASSIGN	156	1	1	100.00
CONT_ASSIGN	156	1	1	100.00
CONT_ASSIGN	156	1	1	100.00
CONT_ASSIGN	160	1	1	100.00
CONT_ASSIGN	160	1	1	100.00
CONT_ASSIGN	160	1	1	100.00
CONT_ASSIGN	161	1	1	100.00
CONT_ASSIGN	161	1	1	100.00
CONT_ASSIGN	161	1	1	100.00
CONT_ASSIGN	163	0	0
CONT_ASSIGN	163	0	0
CONT_ASSIGN	163	1	1	100.00
CONT_ASSIGN	164	1	1	100.00
CONT_ASSIGN	164	1	1	100.00
CONT_ASSIGN	164	1	1	100.00
CONT_ASSIGN	174	1	1	100.00
CONT_ASSIGN	180	1	1	100.00
CONT_ASSIGN	182	1	1	100.00
CONT_ASSIGN	183	1	1	100.00
ALWAYS	191	3	3	100.00

61                        logic unused_req_chk;
62         unreachable    assign unused_req_chk = req_chk_i;
63                      
64                        `ASSERT_INIT(CheckNGreaterZero_A, N > 0)
65                      
66                        // this case is basically just a bypass
67                        if (N == 1) begin : gen_degenerate_case
68                      
69                          assign valid_o  = req_i[0];
70                          assign data_o   = data_i[0];
71                          assign gnt_o[0] = valid_o & ready_i;
72                          assign idx_o    = '0;
73                      
74                        end else begin : gen_normal_case
75                      
76                          // align to powers of 2 for simplicity
77                          // a full binary tree with N levels has 2**N + 2**N-1 nodes
78                          logic [2**(IdxW+1)-2:0]           req_tree;
79                          logic [2**(IdxW+1)-2:0]           prio_tree;
80                          logic [2**(IdxW+1)-2:0]           sel_tree;
81                          logic [2**(IdxW+1)-2:0]           mask_tree;
82                          logic [2**(IdxW+1)-2:0][IdxW-1:0] idx_tree;
83                          logic [2**(IdxW+1)-2:0][DW-1:0]   data_tree;
84                          logic [N-1:0]                     prio_mask_d, prio_mask_q;
85                      
86                          for (genvar level = 0; level < IdxW+1; level++) begin : gen_tree
87                            //
88                            // level+1   C0   C1   <- "Base1" points to the first node on "level+1",
89                            //            \  /         these nodes are the children of the nodes one level below
90                            // level       Pa      <- "Base0", points to the first node on "level",
91                            //                         these nodes are the parents of the nodes one level above
92                            //
93                            // hence we have the following indices for the Pa, C0, C1 nodes:
94                            // Pa = 2**level     - 1 + offset       = Base0 + offset
95                            // C0 = 2**(level+1) - 1 + 2*offset     = Base1 + 2*offset
96                            // C1 = 2**(level+1) - 1 + 2*offset + 1 = Base1 + 2*offset + 1
97                            //
98                            localparam int Base0 = (2**level)-1;
99                            localparam int Base1 = (2**(level+1))-1;
100                     
101                           for (genvar offset = 0; offset < 2**level; offset++) begin : gen_level
102                             localparam int Pa = Base0 + offset;
103                             localparam int C0 = Base1 + 2*offset;
104                             localparam int C1 = Base1 + 2*offset + 1;
105                     
106                             // this assigns the gated interrupt source signals, their
107                             // corresponding IDs and priorities to the tree leafs
108                             if (level == IdxW) begin : gen_leafs
109                               if (offset < N) begin : gen_assign
110                                 // forward path (requests and data)
111                                 // all requests inputs are assigned to the request tree
112        4/4                      assign req_tree[Pa]      = req_i[offset];
           Tests:       T1 T2 T3  | T1 T2 T3  | T1 T2 T3  | T1 T2 T3 
113                                 // we basically split the incoming request vector into two halves with the following
114                                 // priority assignment. the prio_mask_q register contains a prefix sum that has been
115                                 // computed using the last winning index, and hence masks out all requests at offsets
116                                 // lower or equal the previously granted index. hence, all higher indices are considered
117                                 // first in the arbitration tree nodes below, before considering the lower indices.
118        4/4                      assign prio_tree[Pa]     = req_i[offset] & prio_mask_q[offset];
           Tests:       T1 T2 T3  | T1 T2 T3  | T1 T2 T3  | T1 T2 T3 
119                                 // input for the index muxes (used to compute the winner index)
120                                 assign idx_tree[Pa]      = offset;
121                                 // input for the data muxes
122        0/4     ==>              assign data_tree[Pa]     = data_i[offset];
123                     
124                                 // backward path (grants and prefix sum)
125                                 // grant if selected, ready and request asserted
126        4/4                      assign gnt_o[offset]       = req_i[offset] & sel_tree[Pa] & ready_i;
           Tests:       T1 T2 T3  | T1 T2 T3  | T1 T2 T3  | T1 T2 T3 
127                                 // only update mask if there is a valid request
128        4/4                      assign prio_mask_d[offset] = (|req_i) ?
           Tests:       T1 T2 T3  | T1 T2 T3  | T1 T2 T3  | T1 T2 T3 
129                                                              mask_tree[Pa] | sel_tree[Pa] & ~ready_i :
130                                                              prio_mask_q[offset];
131                               end else begin : gen_tie_off
132                                 // forward path
133                                 assign req_tree[Pa]  = '0;
134                                 assign prio_tree[Pa] = '0;
135                                 assign idx_tree[Pa]  = '0;
136                                 assign data_tree[Pa] = '0;
137                                 logic unused_sigs;
138                                 assign unused_sigs = ^{mask_tree[Pa],
139                                                        sel_tree[Pa]};
140                               end
141                             // this creates the node assignments
142                             end else begin : gen_nodes
143                               // local helper variable
144                               logic sel;
145                     
146                               // forward path (requests and data)
147                               // each node looks at its two children, and selects the one with higher priority
148        3/3                    assign sel = ~req_tree[C0] | ~prio_tree[C0] & prio_tree[C1];
           Tests:       T1 T2 T3  | T1 T2 T3  | T1 T2 T3 
149                               // propagate requests
150        3/3                    assign req_tree[Pa]  = req_tree[C0] | req_tree[C1];
           Tests:       T1 T2 T3  | T1 T2 T3  | T1 T2 T3 
151        3/3                    assign prio_tree[Pa] = prio_tree[C1] | prio_tree[C0];
           Tests:       T1 T2 T3  | T1 T2 T3  | T1 T2 T3 
152                               // data and index muxes
153                               // Note: these ternaries have triggered a synthesis bug in Vivado versions older
154                               // than 2020.2. If the problem resurfaces again, have a look at issue #1408.
155        3/3                    assign idx_tree[Pa]  = (sel) ? idx_tree[C1]  : idx_tree[C0];
           Tests:       T1 T2 T3  | T1 T2 T3  | T1 T2 T3 
156        3/3                    assign data_tree[Pa] = (sel) ? data_tree[C1] : data_tree[C0];
           Tests:       T1 T2 T3  | T1 T2 T3  | T1 T2 T3 
157                     
158                               // backward path (grants and prefix sum)
159                               // this propagates the selction index back and computes a hot one mask
160        3/3                    assign sel_tree[C0] = sel_tree[Pa] & ~sel;
           Tests:       T1 T2 T3  | T1 T2 T3  | T1 T2 T3 
161        3/3                    assign sel_tree[C1] = sel_tree[Pa] &  sel;
           Tests:       T1 T2 T3  | T1 T2 T3  | T1 T2 T3 
162                               // this performs a prefix sum for masking the input requests in the next cycle
163        1/1(2 unreachable)            assign mask_tree[C0] = mask_tree[Pa];
           Tests:       T1 T2 T3 
164        3/3                    assign mask_tree[C1] = mask_tree[Pa] | sel_tree[C0];
           Tests:       T1 T2 T3  | T1 T2 T3  | T1 T2 T3 
165                             end
166                           end : gen_level
167                         end : gen_tree
168                     
169                         // the results can be found at the tree root
170                         if (EnDataPort) begin : gen_data_port
171                           assign data_o      = data_tree[0];
172                         end else begin : gen_no_dataport
173                           logic [DW-1:0] unused_data;
174        1/1                assign unused_data = data_tree[0];
           Tests:       T1 T2 T3 
175                           assign data_o = '1;
176                         end
177                     
178                         // This index is unused.
179                         logic unused_prio_tree;
180        1/1              assign unused_prio_tree = prio_tree[0];
           Tests:       T1 T2 T3 
181                     
182        1/1              assign idx_o       = idx_tree[0];
           Tests:       T1 T2 T3 
183        1/1              assign valid_o     = req_tree[0];
           Tests:       T1 T2 T3 
184                     
185                         // the select tree computes a hot one signal that indicates which request is currently selected
186                         assign sel_tree[0] = 1'b1;
187                         // the mask tree is basically a prefix sum of the hot one select signal computed above
188                         assign mask_tree[0] = 1'b0;
189                     
190                         always_ff @(posedge clk_i or negedge rst_ni) begin : p_mask_reg
191        1/1                if (!rst_ni) begin
           Tests:       T1 T2 T3 
192        1/1                  prio_mask_q <= '0;
           Tests:       T1 T2 T3 
193                           end else begin
194        1/1                  prio_mask_q <= prio_mask_d;
           Tests:       T1 T2 T3 

---

Line Coverage for Module : prim_arbiter_tree ( parameter N=2,DW=16,EnDataPort=1,IdxW=1,gen_normal_case.gen_tree[0].gen_level[0].Pa=0,gen_normal_case.gen_tree[0].gen_level[0].C0=1,gen_normal_case.gen_tree[0].gen_level[0].C1=2,gen_normal_case.gen_tree[1].gen_level[0].Pa=1,gen_normal_case.gen_tree[1].gen_level[0].C0=3,gen_normal_case.gen_tree[1].gen_level[0].C1=4,gen_normal_case.gen_tree[1].gen_level[1].Pa=2,gen_normal_case.gen_tree[1].gen_level[1].C0=5,gen_normal_case.gen_tree[1].gen_level[1].C1=6 + N=2,DW=129,EnDataPort=1,IdxW=1,gen_normal_case.gen_tree[0].gen_level[0].Pa=0,gen_normal_case.gen_tree[0].gen_level[0].C0=1,gen_normal_case.gen_tree[0].gen_level[0].C1=2,gen_normal_case.gen_tree[1].gen_level[0].Pa=1,gen_normal_case.gen_tree[1].gen_level[0].C0=3,gen_normal_case.gen_tree[1].gen_level[0].C1=4,gen_normal_case.gen_tree[1].gen_level[1].Pa=2,gen_normal_case.gen_tree[1].gen_level[1].C0=5,gen_normal_case.gen_tree[1].gen_level[1].C1=6 )
Line Coverage for Module self-instances :

SCORE	LINE
98.44	100.00

tb.dut.u_eflash.u_scramble.u_prim_arbiter_tree_calc.gen_input_bufs[0].gen_rr_arbiter.u_arb

SCORE	LINE
97.86	100.00

tb.dut.u_eflash.u_scramble.u_prim_arbiter_tree_calc.gen_input_bufs[1].gen_rr_arbiter.u_arb

SCORE	LINE
95.50	100.00

tb.dut.u_eflash.u_scramble.u_prim_arbiter_tree_op.gen_input_bufs[0].gen_rr_arbiter.u_arb

SCORE	LINE
97.46	100.00

tb.dut.u_eflash.u_scramble.u_prim_arbiter_tree_op.gen_input_bufs[1].gen_rr_arbiter.u_arb

	Line No.	Total	Covered	Percent
TOTAL		25	25	100.00
CONT_ASSIGN	62	0	0
CONT_ASSIGN	112	1	1	100.00
CONT_ASSIGN	112	1	1	100.00
CONT_ASSIGN	118	1	1	100.00
CONT_ASSIGN	118	1	1	100.00
CONT_ASSIGN	122	1	1	100.00
CONT_ASSIGN	122	1	1	100.00
CONT_ASSIGN	126	1	1	100.00
CONT_ASSIGN	126	1	1	100.00
CONT_ASSIGN	128	1	1	100.00
CONT_ASSIGN	128	1	1	100.00
CONT_ASSIGN	148	1	1	100.00
CONT_ASSIGN	150	1	1	100.00
CONT_ASSIGN	151	1	1	100.00
CONT_ASSIGN	155	1	1	100.00
CONT_ASSIGN	156	1	1	100.00
CONT_ASSIGN	160	1	1	100.00
CONT_ASSIGN	161	1	1	100.00
CONT_ASSIGN	163	0	0
CONT_ASSIGN	164	1	1	100.00
CONT_ASSIGN	171	1	1	100.00
CONT_ASSIGN	180	1	1	100.00
CONT_ASSIGN	182	1	1	100.00
CONT_ASSIGN	183	1	1	100.00
ALWAYS	191	3	3	100.00

61                        logic unused_req_chk;
62         unreachable    assign unused_req_chk = req_chk_i;
63                      
64                        `ASSERT_INIT(CheckNGreaterZero_A, N > 0)
65                      
66                        // this case is basically just a bypass
67                        if (N == 1) begin : gen_degenerate_case
68                      
69                          assign valid_o  = req_i[0];
70                          assign data_o   = data_i[0];
71                          assign gnt_o[0] = valid_o & ready_i;
72                          assign idx_o    = '0;
73                      
74                        end else begin : gen_normal_case
75                      
76                          // align to powers of 2 for simplicity
77                          // a full binary tree with N levels has 2**N + 2**N-1 nodes
78                          logic [2**(IdxW+1)-2:0]           req_tree;
79                          logic [2**(IdxW+1)-2:0]           prio_tree;
80                          logic [2**(IdxW+1)-2:0]           sel_tree;
81                          logic [2**(IdxW+1)-2:0]           mask_tree;
82                          logic [2**(IdxW+1)-2:0][IdxW-1:0] idx_tree;
83                          logic [2**(IdxW+1)-2:0][DW-1:0]   data_tree;
84                          logic [N-1:0]                     prio_mask_d, prio_mask_q;
85                      
86                          for (genvar level = 0; level < IdxW+1; level++) begin : gen_tree
87                            //
88                            // level+1   C0   C1   <- "Base1" points to the first node on "level+1",
89                            //            \  /         these nodes are the children of the nodes one level below
90                            // level       Pa      <- "Base0", points to the first node on "level",
91                            //                         these nodes are the parents of the nodes one level above
92                            //
93                            // hence we have the following indices for the Pa, C0, C1 nodes:
94                            // Pa = 2**level     - 1 + offset       = Base0 + offset
95                            // C0 = 2**(level+1) - 1 + 2*offset     = Base1 + 2*offset
96                            // C1 = 2**(level+1) - 1 + 2*offset + 1 = Base1 + 2*offset + 1
97                            //
98                            localparam int Base0 = (2**level)-1;
99                            localparam int Base1 = (2**(level+1))-1;
100                     
101                           for (genvar offset = 0; offset < 2**level; offset++) begin : gen_level
102                             localparam int Pa = Base0 + offset;
103                             localparam int C0 = Base1 + 2*offset;
104                             localparam int C1 = Base1 + 2*offset + 1;
105                     
106                             // this assigns the gated interrupt source signals, their
107                             // corresponding IDs and priorities to the tree leafs
108                             if (level == IdxW) begin : gen_leafs
109                               if (offset < N) begin : gen_assign
110                                 // forward path (requests and data)
111                                 // all requests inputs are assigned to the request tree
112        2/2                      assign req_tree[Pa]      = req_i[offset];
           Tests:       T1 T2 T3  | T1 T2 T3 
113                                 // we basically split the incoming request vector into two halves with the following
114                                 // priority assignment. the prio_mask_q register contains a prefix sum that has been
115                                 // computed using the last winning index, and hence masks out all requests at offsets
116                                 // lower or equal the previously granted index. hence, all higher indices are considered
117                                 // first in the arbitration tree nodes below, before considering the lower indices.
118        2/2                      assign prio_tree[Pa]     = req_i[offset] & prio_mask_q[offset];
           Tests:       T1 T2 T3  | T1 T2 T3 
119                                 // input for the index muxes (used to compute the winner index)
120                                 assign idx_tree[Pa]      = offset;
121                                 // input for the data muxes
122        2/2                      assign data_tree[Pa]     = data_i[offset];
           Tests:       T1 T2 T3  | T1 T2 T3 
123                     
124                                 // backward path (grants and prefix sum)
125                                 // grant if selected, ready and request asserted
126        2/2                      assign gnt_o[offset]       = req_i[offset] & sel_tree[Pa] & ready_i;
           Tests:       T1 T2 T3  | T1 T2 T3 
127                                 // only update mask if there is a valid request
128        2/2                      assign prio_mask_d[offset] = (|req_i) ?
           Tests:       T1 T2 T3  | T1 T2 T3 
129                                                              mask_tree[Pa] | sel_tree[Pa] & ~ready_i :
130                                                              prio_mask_q[offset];
131                               end else begin : gen_tie_off
132                                 // forward path
133                                 assign req_tree[Pa]  = '0;
134                                 assign prio_tree[Pa] = '0;
135                                 assign idx_tree[Pa]  = '0;
136                                 assign data_tree[Pa] = '0;
137                                 logic unused_sigs;
138                                 assign unused_sigs = ^{mask_tree[Pa],
139                                                        sel_tree[Pa]};
140                               end
141                             // this creates the node assignments
142                             end else begin : gen_nodes
143                               // local helper variable
144                               logic sel;
145                     
146                               // forward path (requests and data)
147                               // each node looks at its two children, and selects the one with higher priority
148        1/1                    assign sel = ~req_tree[C0] | ~prio_tree[C0] & prio_tree[C1];
           Tests:       T1 T2 T3 
149                               // propagate requests
150        1/1                    assign req_tree[Pa]  = req_tree[C0] | req_tree[C1];
           Tests:       T1 T2 T3 
151        1/1                    assign prio_tree[Pa] = prio_tree[C1] | prio_tree[C0];
           Tests:       T1 T2 T3 
152                               // data and index muxes
153                               // Note: these ternaries have triggered a synthesis bug in Vivado versions older
154                               // than 2020.2. If the problem resurfaces again, have a look at issue #1408.
155        1/1                    assign idx_tree[Pa]  = (sel) ? idx_tree[C1]  : idx_tree[C0];
           Tests:       T1 T2 T3 
156        1/1                    assign data_tree[Pa] = (sel) ? data_tree[C1] : data_tree[C0];
           Tests:       T1 T2 T3 
157                     
158                               // backward path (grants and prefix sum)
159                               // this propagates the selction index back and computes a hot one mask
160        1/1                    assign sel_tree[C0] = sel_tree[Pa] & ~sel;
           Tests:       T1 T2 T3 
161        1/1                    assign sel_tree[C1] = sel_tree[Pa] &  sel;
           Tests:       T1 T2 T3 
162                               // this performs a prefix sum for masking the input requests in the next cycle
163        unreachable            assign mask_tree[C0] = mask_tree[Pa];
164        1/1                    assign mask_tree[C1] = mask_tree[Pa] | sel_tree[C0];
           Tests:       T1 T2 T3 
165                             end
166                           end : gen_level
167                         end : gen_tree
168                     
169                         // the results can be found at the tree root
170                         if (EnDataPort) begin : gen_data_port
171        1/1                assign data_o      = data_tree[0];
           Tests:       T1 T2 T3 
172                         end else begin : gen_no_dataport
173                           logic [DW-1:0] unused_data;
174                           assign unused_data = data_tree[0];
175                           assign data_o = '1;
176                         end
177                     
178                         // This index is unused.
179                         logic unused_prio_tree;
180        1/1              assign unused_prio_tree = prio_tree[0];
           Tests:       T1 T2 T3 
181                     
182        1/1              assign idx_o       = idx_tree[0];
           Tests:       T1 T2 T3 
183        1/1              assign valid_o     = req_tree[0];
           Tests:       T1 T2 T3 
184                     
185                         // the select tree computes a hot one signal that indicates which request is currently selected
186                         assign sel_tree[0] = 1'b1;
187                         // the mask tree is basically a prefix sum of the hot one select signal computed above
188                         assign mask_tree[0] = 1'b0;
189                     
190                         always_ff @(posedge clk_i or negedge rst_ni) begin : p_mask_reg
191        1/1                if (!rst_ni) begin
           Tests:       T1 T2 T3 
192        1/1                  prio_mask_q <= '0;
           Tests:       T1 T2 T3 
193                           end else begin
194        1/1                  prio_mask_q <= prio_mask_d;
           Tests:       T1 T2 T3 

---

Cond Coverage for Module : prim_arbiter_tree ( parameter N=2,DW=16,EnDataPort=1,IdxW=1,gen_normal_case.gen_tree[0].gen_level[0].Pa=0,gen_normal_case.gen_tree[0].gen_level[0].C0=1,gen_normal_case.gen_tree[0].gen_level[0].C1=2,gen_normal_case.gen_tree[1].gen_level[0].Pa=1,gen_normal_case.gen_tree[1].gen_level[0].C0=3,gen_normal_case.gen_tree[1].gen_level[0].C1=4,gen_normal_case.gen_tree[1].gen_level[1].Pa=2,gen_normal_case.gen_tree[1].gen_level[1].C0=5,gen_normal_case.gen_tree[1].gen_level[1].C1=6 )
Cond Coverage for Module self-instances :

SCORE	COND
98.44	100.00

tb.dut.u_eflash.u_scramble.u_prim_arbiter_tree_calc.gen_input_bufs[0].gen_rr_arbiter.u_arb

SCORE	COND
97.86	97.67

tb.dut.u_eflash.u_scramble.u_prim_arbiter_tree_calc.gen_input_bufs[1].gen_rr_arbiter.u_arb

	Total	Covered	Percent
Conditions	43	43	100.00
Logical	43	43	100.00
Non-Logical	0	0
Event	0	0

 LINE       118
 EXPRESSION (req_i[0] & gen_normal_case.prio_mask_q[0])
             ----1---   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T99
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       118
 EXPRESSION (req_i[1] & gen_normal_case.prio_mask_q[1])
             ----1---   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T6,T25,T11
1	1	Covered	T4,T6,T31

 LINE       126
 EXPRESSION (req_i[0] & gen_normal_case.sel_tree[gen_normal_case.gen_tree[1].gen_level[0].Pa] & ready_i)
             ----1---   ----------------------------------2----------------------------------   ---3---

-1-	-2-	-3-	Status	Tests
0	1	1	Unreachable
1	0	1	Unreachable	T11,T61,T68
1	1	0	Covered	T1,T2,T3
1	1	1	Unreachable	T1,T2,T3

 LINE       126
 EXPRESSION (req_i[1] & gen_normal_case.sel_tree[gen_normal_case.gen_tree[1].gen_level[1].Pa] & ready_i)
             ----1---   ----------------------------------2----------------------------------   ---3---

-1-	-2-	-3-	Status	Tests
0	1	1	Unreachable	T99,T100
1	0	1	Unreachable	T11,T61,T68
1	1	0	Covered	T4,T6,T31
1	1	1	Unreachable	T4,T6,T31

 LINE       128
 EXPRESSION 
 Number  Term
      1  ((|req_i)) ? (gen_normal_case.mask_tree[gen_normal_case.gen_tree[1].gen_level[0].Pa] | (gen_normal_case.sel_tree[gen_normal_case.gen_tree[1].gen_level[0].Pa] & ((~ready_i)))) : gen_normal_case.prio_mask_q[0])

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       128
 SUB-EXPRESSION 
 Number  Term
      1  gen_normal_case.mask_tree[gen_normal_case.gen_tree[1].gen_level[0].Pa] | 
      2  (gen_normal_case.sel_tree[gen_normal_case.gen_tree[1].gen_level[0].Pa] & ((~ready_i))))

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Unreachable

 LINE       128
 SUB-EXPRESSION (gen_normal_case.sel_tree[gen_normal_case.gen_tree[1].gen_level[0].Pa] & ((~ready_i)))
                 ----------------------------------1----------------------------------   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T4,T6,T31
1	0	Unreachable	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       128
 EXPRESSION 
 Number  Term
      1  ((|req_i)) ? (gen_normal_case.mask_tree[gen_normal_case.gen_tree[1].gen_level[1].Pa] | (gen_normal_case.sel_tree[gen_normal_case.gen_tree[1].gen_level[1].Pa] & ((~ready_i)))) : gen_normal_case.prio_mask_q[1])

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       128
 SUB-EXPRESSION 
 Number  Term
      1  gen_normal_case.mask_tree[gen_normal_case.gen_tree[1].gen_level[1].Pa] | 
      2  (gen_normal_case.sel_tree[gen_normal_case.gen_tree[1].gen_level[1].Pa] & ((~ready_i))))

-1-	-2-	Status	Tests
0	0	Covered	T4,T6,T31
0	1	Covered	T4,T6,T31
1	0	Covered	T1,T2,T3

 LINE       128
 SUB-EXPRESSION (gen_normal_case.sel_tree[gen_normal_case.gen_tree[1].gen_level[1].Pa] & ((~ready_i)))
                 ----------------------------------1----------------------------------   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Unreachable	T4,T6,T31
1	1	Covered	T4,T6,T31

 LINE       148
 EXPRESSION 
 Number  Term
      1  ((~gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])) | 
      2  (((~gen_normal_case.prio_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])) & gen_normal_case.prio_tree[gen_normal_case.gen_tree[0].gen_level[0].C1]))

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T11,T61,T68
1	0	Covered	T1,T2,T3

 LINE       148
 SUB-EXPRESSION 
 Number  Term
      1  ((~gen_normal_case.prio_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])) & 
      2  gen_normal_case.prio_tree[gen_normal_case.gen_tree[0].gen_level[0].C1])

-1-	-2-	Status	Tests
0	1	Covered	T11,T61,T68
1	0	Covered	T1,T2,T3
1	1	Covered	T4,T6,T31

 LINE       150
 EXPRESSION (gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C0] | gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C1])
             ----------------------------------1----------------------------------   ----------------------------------2----------------------------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T4,T6,T31
1	0	Covered	T1,T2,T3

 LINE       151
 EXPRESSION (gen_normal_case.prio_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] | gen_normal_case.prio_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])
             -----------------------------------1----------------------------------   -----------------------------------2----------------------------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T4,T6,T31

 LINE       155
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       156
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       160
 EXPRESSION (gen_normal_case.sel_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & ((~gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)))
             ----------------------------------1----------------------------------   -----------------------------2-----------------------------

-1-	-2-	Status	Tests
0	1	Unreachable
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       161
 EXPRESSION (gen_normal_case.sel_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)
             ----------------------------------1----------------------------------   ---------------------------2--------------------------

-1-	-2-	Status	Tests
0	1	Unreachable
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       164
 EXPRESSION (gen_normal_case.mask_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] | gen_normal_case.sel_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])
             -----------------------------------1----------------------------------   ----------------------------------2----------------------------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Unreachable

---

Cond Coverage for Module : prim_arbiter_tree ( parameter N=2,DW=129,EnDataPort=1,IdxW=1,gen_normal_case.gen_tree[0].gen_level[0].Pa=0,gen_normal_case.gen_tree[0].gen_level[0].C0=1,gen_normal_case.gen_tree[0].gen_level[0].C1=2,gen_normal_case.gen_tree[1].gen_level[0].Pa=1,gen_normal_case.gen_tree[1].gen_level[0].C0=3,gen_normal_case.gen_tree[1].gen_level[0].C1=4,gen_normal_case.gen_tree[1].gen_level[1].Pa=2,gen_normal_case.gen_tree[1].gen_level[1].C0=5,gen_normal_case.gen_tree[1].gen_level[1].C1=6 )
Cond Coverage for Module self-instances :

SCORE	COND
95.50	88.24

tb.dut.u_eflash.u_scramble.u_prim_arbiter_tree_op.gen_input_bufs[0].gen_rr_arbiter.u_arb

SCORE	COND
97.46	96.08

tb.dut.u_eflash.u_scramble.u_prim_arbiter_tree_op.gen_input_bufs[1].gen_rr_arbiter.u_arb

	Total	Covered	Percent
Conditions	51	49	96.08
Logical	51	49	96.08
Non-Logical	0	0
Event	0	0

 LINE       118
 EXPRESSION (req_i[0] & gen_normal_case.prio_mask_q[0])
             ----1---   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       118
 EXPRESSION (req_i[1] & gen_normal_case.prio_mask_q[1])
             ----1---   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T6,T25,T22
1	1	Covered	T4,T6,T31

 LINE       126
 EXPRESSION (req_i[0] & gen_normal_case.sel_tree[gen_normal_case.gen_tree[1].gen_level[0].Pa] & ready_i)
             ----1---   ----------------------------------2----------------------------------   ---3---

-1-	-2-	-3-	Status	Tests
0	1	1	Not Covered
1	0	1	Covered	T12
1	1	0	Covered	T1,T2,T3
1	1	1	Covered	T1,T2,T3

 LINE       126
 EXPRESSION (req_i[1] & gen_normal_case.sel_tree[gen_normal_case.gen_tree[1].gen_level[1].Pa] & ready_i)
             ----1---   ----------------------------------2----------------------------------   ---3---

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T12
1	0	1	Covered	T12
1	1	0	Covered	T4,T6,T31
1	1	1	Covered	T4,T6,T31

 LINE       128
 EXPRESSION 
 Number  Term
      1  ((|req_i)) ? (gen_normal_case.mask_tree[gen_normal_case.gen_tree[1].gen_level[0].Pa] | (gen_normal_case.sel_tree[gen_normal_case.gen_tree[1].gen_level[0].Pa] & ((~ready_i)))) : gen_normal_case.prio_mask_q[0])

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       128
 SUB-EXPRESSION 
 Number  Term
      1  gen_normal_case.mask_tree[gen_normal_case.gen_tree[1].gen_level[0].Pa] | 
      2  (gen_normal_case.sel_tree[gen_normal_case.gen_tree[1].gen_level[0].Pa] & ((~ready_i))))

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Unreachable

 LINE       128
 SUB-EXPRESSION (gen_normal_case.sel_tree[gen_normal_case.gen_tree[1].gen_level[0].Pa] & ((~ready_i)))
                 ----------------------------------1----------------------------------   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T4,T6,T31
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       128
 EXPRESSION 
 Number  Term
      1  ((|req_i)) ? (gen_normal_case.mask_tree[gen_normal_case.gen_tree[1].gen_level[1].Pa] | (gen_normal_case.sel_tree[gen_normal_case.gen_tree[1].gen_level[1].Pa] & ((~ready_i)))) : gen_normal_case.prio_mask_q[1])

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       128
 SUB-EXPRESSION 
 Number  Term
      1  gen_normal_case.mask_tree[gen_normal_case.gen_tree[1].gen_level[1].Pa] | 
      2  (gen_normal_case.sel_tree[gen_normal_case.gen_tree[1].gen_level[1].Pa] & ((~ready_i))))

-1-	-2-	Status	Tests
0	0	Covered	T4,T6,T31
0	1	Covered	T4,T6,T31
1	0	Covered	T1,T2,T3

 LINE       128
 SUB-EXPRESSION (gen_normal_case.sel_tree[gen_normal_case.gen_tree[1].gen_level[1].Pa] & ((~ready_i)))
                 ----------------------------------1----------------------------------   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T4,T6,T31
1	1	Covered	T4,T6,T31

 LINE       148
 EXPRESSION 
 Number  Term
      1  ((~gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])) | 
      2  (((~gen_normal_case.prio_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])) & gen_normal_case.prio_tree[gen_normal_case.gen_tree[0].gen_level[0].C1]))

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T12
1	0	Covered	T1,T2,T3

 LINE       148
 SUB-EXPRESSION 
 Number  Term
      1  ((~gen_normal_case.prio_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])) & 
      2  gen_normal_case.prio_tree[gen_normal_case.gen_tree[0].gen_level[0].C1])

-1-	-2-	Status	Tests
0	1	Covered	T12
1	0	Covered	T1,T2,T3
1	1	Covered	T4,T6,T31

 LINE       150
 EXPRESSION (gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C0] | gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C1])
             ----------------------------------1----------------------------------   ----------------------------------2----------------------------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T4,T6,T31
1	0	Covered	T1,T2,T3

 LINE       151
 EXPRESSION (gen_normal_case.prio_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] | gen_normal_case.prio_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])
             -----------------------------------1----------------------------------   -----------------------------------2----------------------------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T4,T6,T31

 LINE       155
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       156
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       160
 EXPRESSION (gen_normal_case.sel_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & ((~gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)))
             ----------------------------------1----------------------------------   -----------------------------2-----------------------------

-1-	-2-	Status	Tests
0	1	Unreachable
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       161
 EXPRESSION (gen_normal_case.sel_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)
             ----------------------------------1----------------------------------   ---------------------------2--------------------------

-1-	-2-	Status	Tests
0	1	Unreachable
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       164
 EXPRESSION (gen_normal_case.mask_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] | gen_normal_case.sel_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])
             -----------------------------------1----------------------------------   ----------------------------------2----------------------------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Unreachable

---

Cond Coverage for Module : prim_arbiter_tree ( parameter N=4,DW=2,EnDataPort=0,IdxW=2,gen_normal_case.gen_tree[0].gen_level[0].Pa=0,gen_normal_case.gen_tree[0].gen_level[0].C0=1,gen_normal_case.gen_tree[0].gen_level[0].C1=2,gen_normal_case.gen_tree[1].gen_level[0].Pa=1,gen_normal_case.gen_tree[1].gen_level[0].C0=3,gen_normal_case.gen_tree[1].gen_level[0].C1=4,gen_normal_case.gen_tree[1].gen_level[1].Pa=2,gen_normal_case.gen_tree[1].gen_level[1].C0=5,gen_normal_case.gen_tree[1].gen_level[1].C1=6,gen_normal_case.gen_tree[2].gen_level[0].Pa=3,gen_normal_case.gen_tree[2].gen_level[0].C0=7,gen_normal_case.gen_tree[2].gen_level[0].C1=8,gen_normal_case.gen_tree[2].gen_level[1].Pa=4,gen_normal_case.gen_tree[2].gen_level[1].C0=9,gen_normal_case.gen_tree[2].gen_level[1].C1=10,gen_normal_case.gen_tree[2].gen_level[2].Pa=5,gen_normal_case.gen_tree[2].gen_level[2].C0=11,gen_normal_case.gen_tree[2].gen_level[2].C1=12,gen_normal_case.gen_tree[2].gen_level[3].Pa=6,gen_normal_case.gen_tree[2].gen_level[3].C0=13,gen_normal_case.gen_tree[2].gen_level[3].C1=14 )
Cond Coverage for Module self-instances :

SCORE	COND
92.50	97.69

tb.dut.u_eflash.gen_flash_cores[0].u_core.u_rd.u_valid_random

SCORE	COND
92.50	97.69

tb.dut.u_eflash.gen_flash_cores[1].u_core.u_rd.u_valid_random

	Total	Covered	Percent
Conditions	130	127	97.69
Logical	130	127	97.69
Non-Logical	0	0
Event	0	0

 LINE       118
 EXPRESSION (req_i[0] & gen_normal_case.prio_mask_q[0])
             ----1---   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T25,T22
1	0	Covered	T1,T3,T5
1	1	Covered	T1,T3,T5

 LINE       118
 EXPRESSION (req_i[1] & gen_normal_case.prio_mask_q[1])
             ----1---   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T5,T10
1	0	Covered	T1,T3,T5
1	1	Covered	T1,T3,T5

 LINE       118
 EXPRESSION (req_i[2] & gen_normal_case.prio_mask_q[2])
             ----1---   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T5,T10
1	0	Covered	T1,T3,T5
1	1	Covered	T1,T3,T5

 LINE       118
 EXPRESSION (req_i[3] & gen_normal_case.prio_mask_q[3])
             ----1---   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T3,T5
1	0	Covered	T59,T60,T211
1	1	Covered	T1,T3,T5

 LINE       126
 EXPRESSION (req_i[0] & gen_normal_case.sel_tree[gen_normal_case.gen_tree[2].gen_level[0].Pa] & ready_i)
             ----1---   ----------------------------------2----------------------------------   ---3---

-1-	-2-	-3-	Status	Tests
0	1	1	Not Covered
1	0	1	Covered	T1,T3,T8
1	1	0	Covered	T1,T3,T5
1	1	1	Covered	T1,T3,T5

 LINE       126
 EXPRESSION (req_i[1] & gen_normal_case.sel_tree[gen_normal_case.gen_tree[2].gen_level[1].Pa] & ready_i)
             ----1---   ----------------------------------2----------------------------------   ---3---

-1-	-2-	-3-	Status	Tests
0	1	1	Not Covered
1	0	1	Covered	T1,T3,T5
1	1	0	Covered	T1,T3,T5
1	1	1	Covered	T1,T3,T8

 LINE       126
 EXPRESSION (req_i[2] & gen_normal_case.sel_tree[gen_normal_case.gen_tree[2].gen_level[2].Pa] & ready_i)
             ----1---   ----------------------------------2----------------------------------   ---3---

-1-	-2-	-3-	Status	Tests
0	1	1	Not Covered
1	0	1	Covered	T1,T3,T5
1	1	0	Covered	T1,T3,T8
1	1	1	Covered	T1,T3,T8

 LINE       126
 EXPRESSION (req_i[3] & gen_normal_case.sel_tree[gen_normal_case.gen_tree[2].gen_level[3].Pa] & ready_i)
             ----1---   ----------------------------------2----------------------------------   ---3---

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T1,T3,T5
1	1	0	Covered	T1,T3,T8
1	1	1	Covered	T1,T3,T8

 LINE       128
 EXPRESSION 
 Number  Term
      1  ((|req_i)) ? (gen_normal_case.mask_tree[gen_normal_case.gen_tree[2].gen_level[0].Pa] | (gen_normal_case.sel_tree[gen_normal_case.gen_tree[2].gen_level[0].Pa] & ((~ready_i)))) : gen_normal_case.prio_mask_q[0])

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T3,T5

 LINE       128
 SUB-EXPRESSION 
 Number  Term
      1  gen_normal_case.mask_tree[gen_normal_case.gen_tree[2].gen_level[0].Pa] | 
      2  (gen_normal_case.sel_tree[gen_normal_case.gen_tree[2].gen_level[0].Pa] & ((~ready_i))))

-1-	-2-	Status	Tests
0	0	Covered	T1,T3,T5
0	1	Covered	T1,T3,T5
1	0	Unreachable

 LINE       128
 SUB-EXPRESSION (gen_normal_case.sel_tree[gen_normal_case.gen_tree[2].gen_level[0].Pa] & ((~ready_i)))
                 ----------------------------------1----------------------------------   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T3,T5
1	0	Covered	T1,T3,T5
1	1	Covered	T1,T3,T5

 LINE       128
 EXPRESSION 
 Number  Term
      1  ((|req_i)) ? (gen_normal_case.mask_tree[gen_normal_case.gen_tree[2].gen_level[1].Pa] | (gen_normal_case.sel_tree[gen_normal_case.gen_tree[2].gen_level[1].Pa] & ((~ready_i)))) : gen_normal_case.prio_mask_q[1])

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T3,T5

 LINE       128
 SUB-EXPRESSION 
 Number  Term
      1  gen_normal_case.mask_tree[gen_normal_case.gen_tree[2].gen_level[1].Pa] | 
      2  (gen_normal_case.sel_tree[gen_normal_case.gen_tree[2].gen_level[1].Pa] & ((~ready_i))))

-1-	-2-	Status	Tests
0	0	Covered	T1,T3,T8
0	1	Covered	T1,T3,T5
1	0	Covered	T1,T3,T5

 LINE       128
 SUB-EXPRESSION (gen_normal_case.sel_tree[gen_normal_case.gen_tree[2].gen_level[1].Pa] & ((~ready_i)))
                 ----------------------------------1----------------------------------   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T3,T5
1	0	Covered	T1,T3,T8
1	1	Covered	T1,T3,T5

 LINE       128
 EXPRESSION 
 Number  Term
      1  ((|req_i)) ? (gen_normal_case.mask_tree[gen_normal_case.gen_tree[2].gen_level[2].Pa] | (gen_normal_case.sel_tree[gen_normal_case.gen_tree[2].gen_level[2].Pa] & ((~ready_i)))) : gen_normal_case.prio_mask_q[2])

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T3,T5

 LINE       128
 SUB-EXPRESSION 
 Number  Term
      1  gen_normal_case.mask_tree[gen_normal_case.gen_tree[2].gen_level[2].Pa] | 
      2  (gen_normal_case.sel_tree[gen_normal_case.gen_tree[2].gen_level[2].Pa] & ((~ready_i))))

-1-	-2-	Status	Tests
0	0	Covered	T1,T3,T8
0	1	Covered	T1,T3,T8
1	0	Covered	T1,T3,T5

 LINE       128
 SUB-EXPRESSION (gen_normal_case.sel_tree[gen_normal_case.gen_tree[2].gen_level[2].Pa] & ((~ready_i)))
                 ----------------------------------1----------------------------------   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T3,T5
1	0	Covered	T1,T3,T8
1	1	Covered	T1,T3,T8

 LINE       128
 EXPRESSION 
 Number  Term
      1  ((|req_i)) ? (gen_normal_case.mask_tree[gen_normal_case.gen_tree[2].gen_level[3].Pa] | (gen_normal_case.sel_tree[gen_normal_case.gen_tree[2].gen_level[3].Pa] & ((~ready_i)))) : gen_normal_case.prio_mask_q[3])

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T3,T5

 LINE       128
 SUB-EXPRESSION 
 Number  Term
      1  gen_normal_case.mask_tree[gen_normal_case.gen_tree[2].gen_level[3].Pa] | 
      2  (gen_normal_case.sel_tree[gen_normal_case.gen_tree[2].gen_level[3].Pa] & ((~ready_i))))

-1-	-2-	Status	Tests
0	0	Covered	T1,T3,T8
0	1	Covered	T1,T3,T8
1	0	Covered	T1,T3,T5

 LINE       128
 SUB-EXPRESSION (gen_normal_case.sel_tree[gen_normal_case.gen_tree[2].gen_level[3].Pa] & ((~ready_i)))
                 ----------------------------------1----------------------------------   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T3,T5
1	0	Covered	T1,T3,T8
1	1	Covered	T1,T3,T8

 LINE       148
 EXPRESSION 
 Number  Term
      1  ((~gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])) | 
      2  (((~gen_normal_case.prio_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])) & gen_normal_case.prio_tree[gen_normal_case.gen_tree[0].gen_level[0].C1]))

-1-	-2-	Status	Tests
0	0	Covered	T1,T3,T5
0	1	Covered	T1,T3,T8
1	0	Covered	T1,T2,T3

 LINE       148
 SUB-EXPRESSION 
 Number  Term
      1  ((~gen_normal_case.prio_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])) & 
      2  gen_normal_case.prio_tree[gen_normal_case.gen_tree[0].gen_level[0].C1])

-1-	-2-	Status	Tests
0	1	Covered	T1,T3,T5
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T3,T8

 LINE       148
 EXPRESSION 
 Number  Term
      1  ((~gen_normal_case.req_tree[gen_normal_case.gen_tree[1].gen_level[0].C0])) | 
      2  (((~gen_normal_case.prio_tree[gen_normal_case.gen_tree[1].gen_level[0].C0])) & gen_normal_case.prio_tree[gen_normal_case.gen_tree[1].gen_level[0].C1]))

-1-	-2-	Status	Tests
0	0	Covered	T1,T3,T5
0	1	Covered	T1,T3,T5
1	0	Covered	T1,T2,T3

 LINE       148
 SUB-EXPRESSION 
 Number  Term
      1  ((~gen_normal_case.prio_tree[gen_normal_case.gen_tree[1].gen_level[0].C0])) & 
      2  gen_normal_case.prio_tree[gen_normal_case.gen_tree[1].gen_level[0].C1])

-1-	-2-	Status	Tests
0	1	Covered	T1,T3,T5
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T3,T5

 LINE       148
 EXPRESSION 
 Number  Term
      1  ((~gen_normal_case.req_tree[gen_normal_case.gen_tree[1].gen_level[1].C0])) | 
      2  (((~gen_normal_case.prio_tree[gen_normal_case.gen_tree[1].gen_level[1].C0])) & gen_normal_case.prio_tree[gen_normal_case.gen_tree[1].gen_level[1].C1]))

-1-	-2-	Status	Tests
0	0	Covered	T1,T3,T5
0	1	Covered	T1,T3,T8
1	0	Covered	T1,T2,T3

 LINE       148
 SUB-EXPRESSION 
 Number  Term
      1  ((~gen_normal_case.prio_tree[gen_normal_case.gen_tree[1].gen_level[1].C0])) & 
      2  gen_normal_case.prio_tree[gen_normal_case.gen_tree[1].gen_level[1].C1])

-1-	-2-	Status	Tests
0	1	Covered	T1,T3,T5
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T3,T8

 LINE       150
 EXPRESSION (gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C0] | gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C1])
             ----------------------------------1----------------------------------   ----------------------------------2----------------------------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T12,T103,T104
1	0	Covered	T12,T103,T104

 LINE       150
 EXPRESSION (gen_normal_case.req_tree[gen_normal_case.gen_tree[1].gen_level[0].C0] | gen_normal_case.req_tree[gen_normal_case.gen_tree[1].gen_level[0].C1])
             ----------------------------------1----------------------------------   ----------------------------------2----------------------------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T3,T5
1	0	Covered	T1,T3,T8

 LINE       150
 EXPRESSION (gen_normal_case.req_tree[gen_normal_case.gen_tree[1].gen_level[1].C0] | gen_normal_case.req_tree[gen_normal_case.gen_tree[1].gen_level[1].C1])
             ----------------------------------1----------------------------------   ----------------------------------2----------------------------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T3,T8
1	0	Covered	T1,T3,T5

 LINE       151
 EXPRESSION (gen_normal_case.prio_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] | gen_normal_case.prio_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])
             -----------------------------------1----------------------------------   -----------------------------------2----------------------------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T12,T103,T104
1	0	Covered	T1,T3,T8

 LINE       151
 EXPRESSION (gen_normal_case.prio_tree[gen_normal_case.gen_tree[1].gen_level[0].C1] | gen_normal_case.prio_tree[gen_normal_case.gen_tree[1].gen_level[0].C0])
             -----------------------------------1----------------------------------   -----------------------------------2----------------------------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T12,T30,T103
1	0	Covered	T1,T3,T5

 LINE       151
 EXPRESSION (gen_normal_case.prio_tree[gen_normal_case.gen_tree[1].gen_level[1].C1] | gen_normal_case.prio_tree[gen_normal_case.gen_tree[1].gen_level[1].C0])
             -----------------------------------1----------------------------------   -----------------------------------2----------------------------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T3,T5
1	0	Covered	T1,T3,T8

 LINE       155
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])

-1-	Status	Tests
0	Covered	T1,T3,T5
1	Covered	T1,T2,T3

 LINE       155
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[1].gen_level[0].gen_nodes.sel ? gen_normal_case.idx_tree[gen_normal_case.gen_tree[1].gen_level[0].C1] : gen_normal_case.idx_tree[gen_normal_case.gen_tree[1].gen_level[0].C0])

-1-	Status	Tests
0	Covered	T1,T3,T5
1	Covered	T1,T2,T3

 LINE       155
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[1].gen_level[1].gen_nodes.sel ? gen_normal_case.idx_tree[gen_normal_case.gen_tree[1].gen_level[1].C1] : gen_normal_case.idx_tree[gen_normal_case.gen_tree[1].gen_level[1].C0])

-1-	Status	Tests
0	Covered	T1,T3,T5
1	Covered	T1,T2,T3

 LINE       156
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])

-1-	Status	Tests
0	Covered	T1,T3,T5
1	Covered	T1,T2,T3

 LINE       156
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[1].gen_level[0].gen_nodes.sel ? gen_normal_case.data_tree[gen_normal_case.gen_tree[1].gen_level[0].C1] : gen_normal_case.data_tree[gen_normal_case.gen_tree[1].gen_level[0].C0])

-1-	Status	Tests
0	Covered	T1,T3,T5
1	Covered	T1,T2,T3

 LINE       156
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[1].gen_level[1].gen_nodes.sel ? gen_normal_case.data_tree[gen_normal_case.gen_tree[1].gen_level[1].C1] : gen_normal_case.data_tree[gen_normal_case.gen_tree[1].gen_level[1].C0])

-1-	Status	Tests
0	Covered	T1,T3,T5
1	Covered	T1,T2,T3

 LINE       160
 EXPRESSION (gen_normal_case.sel_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & ((~gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)))
             ----------------------------------1----------------------------------   -----------------------------2-----------------------------

-1-	-2-	Status	Tests
0	1	Unreachable
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T3,T5

 LINE       160
 EXPRESSION (gen_normal_case.sel_tree[gen_normal_case.gen_tree[1].gen_level[0].Pa] & ((~gen_normal_case.gen_tree[1].gen_level[0].gen_nodes.sel)))
             ----------------------------------1----------------------------------   -----------------------------2-----------------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T3,T8
1	0	Covered	T1,T3,T5
1	1	Covered	T1,T3,T5

 LINE       160
 EXPRESSION (gen_normal_case.sel_tree[gen_normal_case.gen_tree[1].gen_level[1].Pa] & ((~gen_normal_case.gen_tree[1].gen_level[1].gen_nodes.sel)))
             ----------------------------------1----------------------------------   -----------------------------2-----------------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T3,T5
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T3,T8

 LINE       161
 EXPRESSION (gen_normal_case.sel_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)
             ----------------------------------1----------------------------------   ---------------------------2--------------------------

-1-	-2-	Status	Tests
0	1	Unreachable
1	0	Covered	T1,T3,T5
1	1	Covered	T1,T2,T3

 LINE       161
 EXPRESSION (gen_normal_case.sel_tree[gen_normal_case.gen_tree[1].gen_level[0].Pa] & gen_normal_case.gen_tree[1].gen_level[0].gen_nodes.sel)
             ----------------------------------1----------------------------------   ---------------------------2--------------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T3,T5
1	1	Covered	T1,T3,T5

 LINE       161
 EXPRESSION (gen_normal_case.sel_tree[gen_normal_case.gen_tree[1].gen_level[1].Pa] & gen_normal_case.gen_tree[1].gen_level[1].gen_nodes.sel)
             ----------------------------------1----------------------------------   ---------------------------2--------------------------

-1-	-2-	Status	Tests
0	1	Covered	T31,T25,T12
1	0	Covered	T1,T3,T8
1	1	Covered	T1,T2,T3

 LINE       164
 EXPRESSION (gen_normal_case.mask_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] | gen_normal_case.sel_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])
             -----------------------------------1----------------------------------   ----------------------------------2----------------------------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T3,T5
1	0	Unreachable

 LINE       164
 EXPRESSION (gen_normal_case.mask_tree[gen_normal_case.gen_tree[1].gen_level[0].Pa] | gen_normal_case.sel_tree[gen_normal_case.gen_tree[1].gen_level[0].C0])
             -----------------------------------1----------------------------------   ----------------------------------2----------------------------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T3,T5
1	0	Unreachable

 LINE       164
 EXPRESSION (gen_normal_case.mask_tree[gen_normal_case.gen_tree[1].gen_level[1].Pa] | gen_normal_case.sel_tree[gen_normal_case.gen_tree[1].gen_level[1].C0])
             -----------------------------------1----------------------------------   ----------------------------------2----------------------------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T3,T8
1	0	Covered	T1,T3,T5

---

Branch Coverage for Module : prim_arbiter_tree ( parameter N=4,DW=2,EnDataPort=0,IdxW=2,gen_normal_case.gen_tree[0].gen_level[0].Pa=0,gen_normal_case.gen_tree[0].gen_level[0].C0=1,gen_normal_case.gen_tree[0].gen_level[0].C1=2,gen_normal_case.gen_tree[1].gen_level[0].Pa=1,gen_normal_case.gen_tree[1].gen_level[0].C0=3,gen_normal_case.gen_tree[1].gen_level[0].C1=4,gen_normal_case.gen_tree[1].gen_level[1].Pa=2,gen_normal_case.gen_tree[1].gen_level[1].C0=5,gen_normal_case.gen_tree[1].gen_level[1].C1=6,gen_normal_case.gen_tree[2].gen_level[0].Pa=3,gen_normal_case.gen_tree[2].gen_level[0].C0=7,gen_normal_case.gen_tree[2].gen_level[0].C1=8,gen_normal_case.gen_tree[2].gen_level[1].Pa=4,gen_normal_case.gen_tree[2].gen_level[1].C0=9,gen_normal_case.gen_tree[2].gen_level[1].C1=10,gen_normal_case.gen_tree[2].gen_level[2].Pa=5,gen_normal_case.gen_tree[2].gen_level[2].C0=11,gen_normal_case.gen_tree[2].gen_level[2].C1=12,gen_normal_case.gen_tree[2].gen_level[3].Pa=6,gen_normal_case.gen_tree[2].gen_level[3].C0=13,gen_normal_case.gen_tree[2].gen_level[3].C1=14 )
Branch Coverage for Module self-instances :

SCORE	BRANCH
92.50	100.00

tb.dut.u_eflash.gen_flash_cores[0].u_core.u_rd.u_valid_random

SCORE	BRANCH
92.50	100.00

tb.dut.u_eflash.gen_flash_cores[1].u_core.u_rd.u_valid_random

	Line No.	Total	Covered	Percent
Branches		22	22	100.00
TERNARY	155	2	2	100.00
TERNARY	156	2	2	100.00
TERNARY	155	2	2	100.00
TERNARY	156	2	2	100.00
TERNARY	155	2	2	100.00
TERNARY	156	2	2	100.00
TERNARY	128	2	2	100.00
TERNARY	128	2	2	100.00
TERNARY	128	2	2	100.00
TERNARY	128	2	2	100.00
IF	191	2	2	100.00

155                  assign idx_tree[Pa]  = (sel) ? idx_tree[C1]  : idx_tree[C0];
                                                  -1-  
                                                  ==>  
                                                  ==>  

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T3,T5

156                  assign data_tree[Pa] = (sel) ? data_tree[C1] : data_tree[C0];
                                                  -1-  
                                                  ==>  
                                                  ==>  

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T3,T5

155                  assign idx_tree[Pa]  = (sel) ? idx_tree[C1]  : idx_tree[C0];
                                                  -1-  
                                                  ==>  
                                                  ==>  

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T3,T5

156                  assign data_tree[Pa] = (sel) ? data_tree[C1] : data_tree[C0];
                                                  -1-  
                                                  ==>  
                                                  ==>  

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T3,T5

155                  assign idx_tree[Pa]  = (sel) ? idx_tree[C1]  : idx_tree[C0];
                                                  -1-  
                                                  ==>  
                                                  ==>  

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T3,T5

156                  assign data_tree[Pa] = (sel) ? data_tree[C1] : data_tree[C0];
                                                  -1-  
                                                  ==>  
                                                  ==>  

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T3,T5

128                    assign prio_mask_d[offset] = (|req_i) ?
                                                             -1-  
                                                             ==>  
                                                             ==>  

Branches:

-1-	Status	Tests
1	Covered	T1,T3,T5
0	Covered	T1,T2,T3

128                    assign prio_mask_d[offset] = (|req_i) ?
                                                             -1-  
                                                             ==>  
                                                             ==>  

Branches:

-1-	Status	Tests
1	Covered	T1,T3,T5
0	Covered	T1,T2,T3

128                    assign prio_mask_d[offset] = (|req_i) ?
                                                             -1-  
                                                             ==>  
                                                             ==>  

Branches:

-1-	Status	Tests
1	Covered	T1,T3,T5
0	Covered	T1,T2,T3

128                    assign prio_mask_d[offset] = (|req_i) ?
                                                             -1-  
                                                             ==>  
                                                             ==>  

Branches:

-1-	Status	Tests
1	Covered	T1,T3,T5
0	Covered	T1,T2,T3

191              if (!rst_ni) begin
                 -1-  
192                prio_mask_q <= '0;
                   ==>
193              end else begin
194                prio_mask_q <= prio_mask_d;
                   ==>

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Branch Coverage for Module : prim_arbiter_tree ( parameter N=2,DW=16,EnDataPort=1,IdxW=1,gen_normal_case.gen_tree[0].gen_level[0].Pa=0,gen_normal_case.gen_tree[0].gen_level[0].C0=1,gen_normal_case.gen_tree[0].gen_level[0].C1=2,gen_normal_case.gen_tree[1].gen_level[0].Pa=1,gen_normal_case.gen_tree[1].gen_level[0].C0=3,gen_normal_case.gen_tree[1].gen_level[0].C1=4,gen_normal_case.gen_tree[1].gen_level[1].Pa=2,gen_normal_case.gen_tree[1].gen_level[1].C0=5,gen_normal_case.gen_tree[1].gen_level[1].C1=6 + N=2,DW=129,EnDataPort=1,IdxW=1,gen_normal_case.gen_tree[0].gen_level[0].Pa=0,gen_normal_case.gen_tree[0].gen_level[0].C0=1,gen_normal_case.gen_tree[0].gen_level[0].C1=2,gen_normal_case.gen_tree[1].gen_level[0].Pa=1,gen_normal_case.gen_tree[1].gen_level[0].C0=3,gen_normal_case.gen_tree[1].gen_level[0].C1=4,gen_normal_case.gen_tree[1].gen_level[1].Pa=2,gen_normal_case.gen_tree[1].gen_level[1].C0=5,gen_normal_case.gen_tree[1].gen_level[1].C1=6 )
Branch Coverage for Module self-instances :

SCORE	BRANCH
98.44	100.00

tb.dut.u_eflash.u_scramble.u_prim_arbiter_tree_calc.gen_input_bufs[0].gen_rr_arbiter.u_arb

SCORE	BRANCH
97.86	100.00

tb.dut.u_eflash.u_scramble.u_prim_arbiter_tree_calc.gen_input_bufs[1].gen_rr_arbiter.u_arb

SCORE	BRANCH
95.50	100.00

tb.dut.u_eflash.u_scramble.u_prim_arbiter_tree_op.gen_input_bufs[0].gen_rr_arbiter.u_arb

SCORE	BRANCH
97.46	100.00

tb.dut.u_eflash.u_scramble.u_prim_arbiter_tree_op.gen_input_bufs[1].gen_rr_arbiter.u_arb

	Line No.	Total	Covered	Percent
Branches		10	10	100.00
TERNARY	155	2	2	100.00
TERNARY	156	2	2	100.00
TERNARY	128	2	2	100.00
TERNARY	128	2	2	100.00
IF	191	2	2	100.00

155                  assign idx_tree[Pa]  = (sel) ? idx_tree[C1]  : idx_tree[C0];
                                                  -1-  
                                                  ==>  
                                                  ==>  

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

156                  assign data_tree[Pa] = (sel) ? data_tree[C1] : data_tree[C0];
                                                  -1-  
                                                  ==>  
                                                  ==>  

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

128                    assign prio_mask_d[offset] = (|req_i) ?
                                                             -1-  
                                                             ==>  
                                                             ==>  

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

128                    assign prio_mask_d[offset] = (|req_i) ?
                                                             -1-  
                                                             ==>  
                                                             ==>  

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

191              if (!rst_ni) begin
                 -1-  
192                prio_mask_q <= '0;
                   ==>
193              end else begin
194                prio_mask_q <= prio_mask_d;
                   ==>

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Module : prim_arbiter_tree

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	15	93.75
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	15	93.75

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	2147483647	2147483647	0	0
CheckNGreaterZero_A	6306	6306	0	0
GntImpliesReady_A	2147483647	69362661	0	0
GntImpliesValid_A	2147483647	69362661	0	0
GrantKnown_A	2147483647	2147483647	0	0
IdxKnown_A	2147483647	2147483647	0	0
IndexIsCorrect_A	2147483647	69362661	0	0
LockArbDecision_A	2147483647	64495358	0	0
NoReadyValidNoGrant_A	2147483647	1979822284	0	0
ReadyAndValidImplyGrant_A	2147483647	69362661	0	0
ReqAndReadyImplyGrant_A	2147483647	69362661	0	0
ReqImpliesValid_A	2147483647	352296584	0	0
ReqStaysHighUntilGranted0_M	2147483647	64494918	0	0
RoundRobin_A	2147483647	0	0	6282
ValidKnown_A	2147483647	2147483647	0	0
gen_data_port_assertion.DataFlow_A	1564706768	64495646	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	12420	11820	0	0
T2	20880	20286	0	0
T3	11322	10932	0	0
T4	26220	23472	0	0
T5	4062	3474	0	0
T8	271278	270906	0	0
T9	8436	7908	0	0
T10	12744	12276	0	0
T16	9246	8826	0	0
T17	9750	9252	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6306	6306	0	0
T1	6	6	0	0
T2	6	6	0	0
T3	6	6	0	0
T4	6	6	0	0
T5	6	6	0	0
T8	6	6	0	0
T9	6	6	0	0
T10	6	6	0	0
T16	6	6	0	0
T17	6	6	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	69362661	0	0
T1	10350	178	0	0
T2	17400	128	0	0
T3	9435	489	0	0
T4	21850	792	0	0
T5	3385	149	0	0
T6	1297	0	0	0
T8	271278	636	0	0
T9	8436	129	0	0
T10	12744	130	0	0
T11	493	2	0	0
T12	0	30	0	0
T16	9246	128	0	0
T17	9750	128	0	0
T22	0	48	0	0
T25	5313	99	0	0
T30	0	269	0	0
T31	1776	31	0	0
T32	0	510	0	0
T48	0	122	0	0
T61	0	2	0	0
T62	1074	0	0	0
T67	0	460	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	69362661	0	0
T1	10350	178	0	0
T2	17400	128	0	0
T3	9435	489	0	0
T4	21850	792	0	0
T5	3385	149	0	0
T6	1297	0	0	0
T8	271278	636	0	0
T9	8436	129	0	0
T10	12744	130	0	0
T11	493	2	0	0
T12	0	30	0	0
T16	9246	128	0	0
T17	9750	128	0	0
T22	0	48	0	0
T25	5313	99	0	0
T30	0	269	0	0
T31	1776	31	0	0
T32	0	510	0	0
T48	0	122	0	0
T61	0	2	0	0
T62	1074	0	0	0
T67	0	460	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	12420	11820	0	0
T2	20880	20286	0	0
T3	11322	10932	0	0
T4	26220	23472	0	0
T5	4062	3474	0	0
T8	271278	270906	0	0
T9	8436	7908	0	0
T10	12744	12276	0	0
T16	9246	8826	0	0
T17	9750	9252	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	12420	11820	0	0
T2	20880	20286	0	0
T3	11322	10932	0	0
T4	26220	23472	0	0
T5	4062	3474	0	0
T8	271278	270906	0	0
T9	8436	7908	0	0
T10	12744	12276	0	0
T16	9246	8826	0	0
T17	9750	9252	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	69362661	0	0
T1	10350	178	0	0
T2	17400	128	0	0
T3	9435	489	0	0
T4	21850	792	0	0
T5	3385	149	0	0
T6	1297	0	0	0
T8	271278	636	0	0
T9	8436	129	0	0
T10	12744	130	0	0
T11	493	2	0	0
T12	0	30	0	0
T16	9246	128	0	0
T17	9750	128	0	0
T22	0	48	0	0
T25	5313	99	0	0
T30	0	269	0	0
T31	1776	31	0	0
T32	0	510	0	0
T48	0	122	0	0
T61	0	2	0	0
T62	1074	0	0	0
T67	0	460	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	64495358	0	0
T1	8280	128	0	0
T2	13920	128	0	0
T3	7548	420	0	0
T4	17480	792	0	0
T5	2708	148	0	0
T8	180852	128	0	0
T9	5624	128	0	0
T10	8496	128	0	0
T16	6164	128	0	0
T17	6500	128	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1979822284	0	0
T1	12420	10124	0	0
T2	20880	19998	0	0
T3	11322	8689	0	0
T4	26220	21696	0	0
T5	4062	3126	0	0
T8	271278	182966	0	0
T9	8436	6620	0	0
T10	12744	11011	0	0
T16	9246	8538	0	0
T17	9750	8964	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	69362661	0	0
T1	10350	178	0	0
T2	17400	128	0	0
T3	9435	489	0	0
T4	21850	792	0	0
T5	3385	149	0	0
T6	1297	0	0	0
T8	271278	636	0	0
T9	8436	129	0	0
T10	12744	130	0	0
T11	493	2	0	0
T12	0	30	0	0
T16	9246	128	0	0
T17	9750	128	0	0
T22	0	48	0	0
T25	5313	99	0	0
T30	0	269	0	0
T31	1776	31	0	0
T32	0	510	0	0
T48	0	122	0	0
T61	0	2	0	0
T62	1074	0	0	0
T67	0	460	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	69362661	0	0
T1	10350	178	0	0
T2	17400	128	0	0
T3	9435	489	0	0
T4	21850	792	0	0
T5	3385	149	0	0
T6	1297	0	0	0
T8	271278	636	0	0
T9	8436	129	0	0
T10	12744	130	0	0
T11	493	2	0	0
T12	0	30	0	0
T16	9246	128	0	0
T17	9750	128	0	0
T22	0	48	0	0
T25	5313	99	0	0
T30	0	269	0	0
T31	1776	31	0	0
T32	0	510	0	0
T48	0	122	0	0
T61	0	2	0	0
T62	1074	0	0	0
T67	0	460	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	352296584	0	0
T1	10350	1660	0	0
T2	17400	256	0	0
T3	9435	2207	0	0
T4	21850	1584	0	0
T5	3385	312	0	0
T6	1297	0	0	0
T8	271278	87900	0	0
T9	8436	1252	0	0
T10	12744	1225	0	0
T11	493	11	0	0
T12	0	41845	0	0
T16	9246	256	0	0
T17	9750	256	0	0
T22	0	1294	0	0
T25	5313	6973	0	0
T30	0	40355	0	0
T31	1776	973	0	0
T48	0	11834	0	0
T61	0	175	0	0
T62	1074	0	0	0
T67	0	41852	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	64494918	0	0
T1	8280	128	0	0
T2	13920	128	0	0
T3	7548	420	0	0
T4	17480	792	0	0
T5	2708	148	0	0
T8	180852	128	0	0
T9	5624	128	0	0
T10	8496	128	0	0
T16	6164	128	0	0
T17	6500	128	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	0	0	6282

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	12420	11820	0	0
T2	20880	20286	0	0
T3	11322	10932	0	0
T4	26220	23472	0	0
T5	4062	3474	0	0
T8	271278	270906	0	0
T9	8436	7908	0	0
T10	12744	12276	0	0
T16	9246	8826	0	0
T17	9750	9252	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1564706768	64495646	0	0
T1	8280	128	0	0
T2	13920	128	0	0
T3	7548	420	0	0
T4	17480	792	0	0
T5	2708	148	0	0
T8	180852	128	0	0
T9	5624	128	0	0
T10	8496	128	0	0
T16	6164	128	0	0
T17	6500	128	0	0

Line Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_rd.u_valid_random

	Line No.	Total	Covered	Percent
TOTAL		52	48	92.31
CONT_ASSIGN	62	0	0
CONT_ASSIGN	112	1	1	100.00
CONT_ASSIGN	112	1	1	100.00
CONT_ASSIGN	112	1	1	100.00
CONT_ASSIGN	112	1	1	100.00
CONT_ASSIGN	118	1	1	100.00
CONT_ASSIGN	118	1	1	100.00
CONT_ASSIGN	118	1	1	100.00
CONT_ASSIGN	118	1	1	100.00
CONT_ASSIGN	122	1	0	0.00
CONT_ASSIGN	122	1	0	0.00
CONT_ASSIGN	122	1	0	0.00
CONT_ASSIGN	122	1	0	0.00
CONT_ASSIGN	126	1	1	100.00
CONT_ASSIGN	126	1	1	100.00
CONT_ASSIGN	126	1	1	100.00
CONT_ASSIGN	126	1	1	100.00
CONT_ASSIGN	128	1	1	100.00
CONT_ASSIGN	128	1	1	100.00
CONT_ASSIGN	128	1	1	100.00
CONT_ASSIGN	128	1	1	100.00
CONT_ASSIGN	148	1	1	100.00
CONT_ASSIGN	148	1	1	100.00
CONT_ASSIGN	148	1	1	100.00
CONT_ASSIGN	150	1	1	100.00
CONT_ASSIGN	150	1	1	100.00
CONT_ASSIGN	150	1	1	100.00
CONT_ASSIGN	151	1	1	100.00
CONT_ASSIGN	151	1	1	100.00
CONT_ASSIGN	151	1	1	100.00
CONT_ASSIGN	155	1	1	100.00
CONT_ASSIGN	155	1	1	100.00
CONT_ASSIGN	155	1	1	100.00
CONT_ASSIGN	156	1	1	100.00
CONT_ASSIGN	156	1	1	100.00
CONT_ASSIGN	156	1	1	100.00
CONT_ASSIGN	160	1	1	100.00
CONT_ASSIGN	160	1	1	100.00
CONT_ASSIGN	160	1	1	100.00
CONT_ASSIGN	161	1	1	100.00
CONT_ASSIGN	161	1	1	100.00
CONT_ASSIGN	161	1	1	100.00
CONT_ASSIGN	163	0	0
CONT_ASSIGN	163	0	0
CONT_ASSIGN	163	1	1	100.00
CONT_ASSIGN	164	1	1	100.00
CONT_ASSIGN	164	1	1	100.00
CONT_ASSIGN	164	1	1	100.00
CONT_ASSIGN	174	1	1	100.00
CONT_ASSIGN	180	1	1	100.00
CONT_ASSIGN	182	1	1	100.00
CONT_ASSIGN	183	1	1	100.00
ALWAYS	191	3	3	100.00

61                        logic unused_req_chk;
62         unreachable    assign unused_req_chk = req_chk_i;
63                      
64                        `ASSERT_INIT(CheckNGreaterZero_A, N > 0)
65                      
66                        // this case is basically just a bypass
67                        if (N == 1) begin : gen_degenerate_case
68                      
69                          assign valid_o  = req_i[0];
70                          assign data_o   = data_i[0];
71                          assign gnt_o[0] = valid_o & ready_i;
72                          assign idx_o    = '0;
73                      
74                        end else begin : gen_normal_case
75                      
76                          // align to powers of 2 for simplicity
77                          // a full binary tree with N levels has 2**N + 2**N-1 nodes
78                          logic [2**(IdxW+1)-2:0]           req_tree;
79                          logic [2**(IdxW+1)-2:0]           prio_tree;
80                          logic [2**(IdxW+1)-2:0]           sel_tree;
81                          logic [2**(IdxW+1)-2:0]           mask_tree;
82                          logic [2**(IdxW+1)-2:0][IdxW-1:0] idx_tree;
83                          logic [2**(IdxW+1)-2:0][DW-1:0]   data_tree;
84                          logic [N-1:0]                     prio_mask_d, prio_mask_q;
85                      
86                          for (genvar level = 0; level < IdxW+1; level++) begin : gen_tree
87                            //
88                            // level+1   C0   C1   <- "Base1" points to the first node on "level+1",
89                            //            \  /         these nodes are the children of the nodes one level below
90                            // level       Pa      <- "Base0", points to the first node on "level",
91                            //                         these nodes are the parents of the nodes one level above
92                            //
93                            // hence we have the following indices for the Pa, C0, C1 nodes:
94                            // Pa = 2**level     - 1 + offset       = Base0 + offset
95                            // C0 = 2**(level+1) - 1 + 2*offset     = Base1 + 2*offset
96                            // C1 = 2**(level+1) - 1 + 2*offset + 1 = Base1 + 2*offset + 1
97                            //
98                            localparam int Base0 = (2**level)-1;
99                            localparam int Base1 = (2**(level+1))-1;
100                     
101                           for (genvar offset = 0; offset < 2**level; offset++) begin : gen_level
102                             localparam int Pa = Base0 + offset;
103                             localparam int C0 = Base1 + 2*offset;
104                             localparam int C1 = Base1 + 2*offset + 1;
105                     
106                             // this assigns the gated interrupt source signals, their
107                             // corresponding IDs and priorities to the tree leafs
108                             if (level == IdxW) begin : gen_leafs
109                               if (offset < N) begin : gen_assign
110                                 // forward path (requests and data)
111                                 // all requests inputs are assigned to the request tree
112        4/4                      assign req_tree[Pa]      = req_i[offset];
           Tests:       T1 T2 T3  | T1 T2 T3  | T1 T2 T3  | T1 T2 T3 
113                                 // we basically split the incoming request vector into two halves with the following
114                                 // priority assignment. the prio_mask_q register contains a prefix sum that has been
115                                 // computed using the last winning index, and hence masks out all requests at offsets
116                                 // lower or equal the previously granted index. hence, all higher indices are considered
117                                 // first in the arbitration tree nodes below, before considering the lower indices.
118        4/4                      assign prio_tree[Pa]     = req_i[offset] & prio_mask_q[offset];
           Tests:       T1 T2 T3  | T1 T2 T3  | T1 T2 T3  | T1 T2 T3 
119                                 // input for the index muxes (used to compute the winner index)
120                                 assign idx_tree[Pa]      = offset;
121                                 // input for the data muxes
122        0/4     ==>              assign data_tree[Pa]     = data_i[offset];
123                     
124                                 // backward path (grants and prefix sum)
125                                 // grant if selected, ready and request asserted
126        4/4                      assign gnt_o[offset]       = req_i[offset] & sel_tree[Pa] & ready_i;
           Tests:       T1 T2 T3  | T1 T2 T3  | T1 T2 T3  | T1 T2 T3 
127                                 // only update mask if there is a valid request
128        4/4                      assign prio_mask_d[offset] = (|req_i) ?
           Tests:       T1 T2 T3  | T1 T2 T3  | T1 T2 T3  | T1 T2 T3 
129                                                              mask_tree[Pa] | sel_tree[Pa] & ~ready_i :
130                                                              prio_mask_q[offset];
131                               end else begin : gen_tie_off
132                                 // forward path
133                                 assign req_tree[Pa]  = '0;
134                                 assign prio_tree[Pa] = '0;
135                                 assign idx_tree[Pa]  = '0;
136                                 assign data_tree[Pa] = '0;
137                                 logic unused_sigs;
138                                 assign unused_sigs = ^{mask_tree[Pa],
139                                                        sel_tree[Pa]};
140                               end
141                             // this creates the node assignments
142                             end else begin : gen_nodes
143                               // local helper variable
144                               logic sel;
145                     
146                               // forward path (requests and data)
147                               // each node looks at its two children, and selects the one with higher priority
148        3/3                    assign sel = ~req_tree[C0] | ~prio_tree[C0] & prio_tree[C1];
           Tests:       T1 T2 T3  | T1 T2 T3  | T1 T2 T3 
149                               // propagate requests
150        3/3                    assign req_tree[Pa]  = req_tree[C0] | req_tree[C1];
           Tests:       T1 T2 T3  | T1 T2 T3  | T1 T2 T3 
151        3/3                    assign prio_tree[Pa] = prio_tree[C1] | prio_tree[C0];
           Tests:       T1 T2 T3  | T1 T2 T3  | T1 T2 T3 
152                               // data and index muxes
153                               // Note: these ternaries have triggered a synthesis bug in Vivado versions older
154                               // than 2020.2. If the problem resurfaces again, have a look at issue #1408.
155        3/3                    assign idx_tree[Pa]  = (sel) ? idx_tree[C1]  : idx_tree[C0];
           Tests:       T1 T2 T3  | T1 T2 T3  | T1 T2 T3 
156        3/3                    assign data_tree[Pa] = (sel) ? data_tree[C1] : data_tree[C0];
           Tests:       T1 T2 T3  | T1 T2 T3  | T1 T2 T3 
157                     
158                               // backward path (grants and prefix sum)
159                               // this propagates the selction index back and computes a hot one mask
160        3/3                    assign sel_tree[C0] = sel_tree[Pa] & ~sel;
           Tests:       T1 T2 T3  | T1 T2 T3  | T1 T2 T3 
161        3/3                    assign sel_tree[C1] = sel_tree[Pa] &  sel;
           Tests:       T1 T2 T3  | T1 T2 T3  | T1 T2 T3 
162                               // this performs a prefix sum for masking the input requests in the next cycle
163        1/1(2 unreachable)            assign mask_tree[C0] = mask_tree[Pa];
           Tests:       T1 T2 T3 
164        3/3                    assign mask_tree[C1] = mask_tree[Pa] | sel_tree[C0];
           Tests:       T1 T2 T3  | T1 T2 T3  | T1 T2 T3 
165                             end
166                           end : gen_level
167                         end : gen_tree
168                     
169                         // the results can be found at the tree root
170                         if (EnDataPort) begin : gen_data_port
171                           assign data_o      = data_tree[0];
172                         end else begin : gen_no_dataport
173                           logic [DW-1:0] unused_data;
174        1/1                assign unused_data = data_tree[0];
           Tests:       T1 T2 T3 
175                           assign data_o = '1;
176                         end
177                     
178                         // This index is unused.
179                         logic unused_prio_tree;
180        1/1              assign unused_prio_tree = prio_tree[0];
           Tests:       T1 T2 T3 
181                     
182        1/1              assign idx_o       = idx_tree[0];
           Tests:       T1 T2 T3 
183        1/1              assign valid_o     = req_tree[0];
           Tests:       T1 T2 T3 
184                     
185                         // the select tree computes a hot one signal that indicates which request is currently selected
186                         assign sel_tree[0] = 1'b1;
187                         // the mask tree is basically a prefix sum of the hot one select signal computed above
188                         assign mask_tree[0] = 1'b0;
189                     
190                         always_ff @(posedge clk_i or negedge rst_ni) begin : p_mask_reg
191        1/1                if (!rst_ni) begin
           Tests:       T1 T2 T3 
192        1/1                  prio_mask_q <= '0;
           Tests:       T1 T2 T3 
193                           end else begin
194        1/1                  prio_mask_q <= prio_mask_d;
           Tests:       T1 T2 T3 

---

Cond Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_rd.u_valid_random

	Total	Covered	Percent
Conditions	130	127	97.69
Logical	130	127	97.69
Non-Logical	0	0
Event	0	0

 LINE       118
 EXPRESSION (req_i[0] & gen_normal_case.prio_mask_q[0])
             ----1---   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T25,T22
1	0	Covered	T1,T3,T5
1	1	Covered	T1,T3,T5

 LINE       118
 EXPRESSION (req_i[1] & gen_normal_case.prio_mask_q[1])
             ----1---   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T5,T10
1	0	Covered	T1,T3,T5
1	1	Covered	T1,T3,T5

 LINE       118
 EXPRESSION (req_i[2] & gen_normal_case.prio_mask_q[2])
             ----1---   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T5,T10
1	0	Covered	T1,T3,T5
1	1	Covered	T1,T3,T5

 LINE       118
 EXPRESSION (req_i[3] & gen_normal_case.prio_mask_q[3])
             ----1---   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T3,T5
1	0	Covered	T59,T60,T211
1	1	Covered	T1,T3,T5

 LINE       126
 EXPRESSION (req_i[0] & gen_normal_case.sel_tree[gen_normal_case.gen_tree[2].gen_level[0].Pa] & ready_i)
             ----1---   ----------------------------------2----------------------------------   ---3---

-1-	-2-	-3-	Status	Tests
0	1	1	Not Covered
1	0	1	Covered	T1,T3,T8
1	1	0	Covered	T1,T3,T5
1	1	1	Covered	T1,T3,T5

 LINE       126
 EXPRESSION (req_i[1] & gen_normal_case.sel_tree[gen_normal_case.gen_tree[2].gen_level[1].Pa] & ready_i)
             ----1---   ----------------------------------2----------------------------------   ---3---

-1-	-2-	-3-	Status	Tests
0	1	1	Not Covered
1	0	1	Covered	T1,T3,T5
1	1	0	Covered	T1,T3,T5
1	1	1	Covered	T1,T3,T8

 LINE       126
 EXPRESSION (req_i[2] & gen_normal_case.sel_tree[gen_normal_case.gen_tree[2].gen_level[2].Pa] & ready_i)
             ----1---   ----------------------------------2----------------------------------   ---3---

-1-	-2-	-3-	Status	Tests
0	1	1	Not Covered
1	0	1	Covered	T1,T3,T5
1	1	0	Covered	T1,T3,T8
1	1	1	Covered	T1,T3,T8

 LINE       126
 EXPRESSION (req_i[3] & gen_normal_case.sel_tree[gen_normal_case.gen_tree[2].gen_level[3].Pa] & ready_i)
             ----1---   ----------------------------------2----------------------------------   ---3---

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T1,T3,T5
1	1	0	Covered	T1,T3,T8
1	1	1	Covered	T1,T3,T8

 LINE       128
 EXPRESSION 
 Number  Term
      1  ((|req_i)) ? (gen_normal_case.mask_tree[gen_normal_case.gen_tree[2].gen_level[0].Pa] | (gen_normal_case.sel_tree[gen_normal_case.gen_tree[2].gen_level[0].Pa] & ((~ready_i)))) : gen_normal_case.prio_mask_q[0])

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T3,T5

 LINE       128
 SUB-EXPRESSION 
 Number  Term
      1  gen_normal_case.mask_tree[gen_normal_case.gen_tree[2].gen_level[0].Pa] | 
      2  (gen_normal_case.sel_tree[gen_normal_case.gen_tree[2].gen_level[0].Pa] & ((~ready_i))))

-1-	-2-	Status	Tests
0	0	Covered	T1,T3,T5
0	1	Covered	T1,T3,T5
1	0	Unreachable

 LINE       128
 SUB-EXPRESSION (gen_normal_case.sel_tree[gen_normal_case.gen_tree[2].gen_level[0].Pa] & ((~ready_i)))
                 ----------------------------------1----------------------------------   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T3,T5
1	0	Covered	T1,T3,T5
1	1	Covered	T1,T3,T5

 LINE       128
 EXPRESSION 
 Number  Term
      1  ((|req_i)) ? (gen_normal_case.mask_tree[gen_normal_case.gen_tree[2].gen_level[1].Pa] | (gen_normal_case.sel_tree[gen_normal_case.gen_tree[2].gen_level[1].Pa] & ((~ready_i)))) : gen_normal_case.prio_mask_q[1])

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T3,T5

 LINE       128
 SUB-EXPRESSION 
 Number  Term
      1  gen_normal_case.mask_tree[gen_normal_case.gen_tree[2].gen_level[1].Pa] | 
      2  (gen_normal_case.sel_tree[gen_normal_case.gen_tree[2].gen_level[1].Pa] & ((~ready_i))))

-1-	-2-	Status	Tests
0	0	Covered	T1,T3,T8
0	1	Covered	T1,T3,T5
1	0	Covered	T1,T3,T5

 LINE       128
 SUB-EXPRESSION (gen_normal_case.sel_tree[gen_normal_case.gen_tree[2].gen_level[1].Pa] & ((~ready_i)))
                 ----------------------------------1----------------------------------   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T3,T5
1	0	Covered	T1,T3,T8
1	1	Covered	T1,T3,T5

 LINE       128
 EXPRESSION 
 Number  Term
      1  ((|req_i)) ? (gen_normal_case.mask_tree[gen_normal_case.gen_tree[2].gen_level[2].Pa] | (gen_normal_case.sel_tree[gen_normal_case.gen_tree[2].gen_level[2].Pa] & ((~ready_i)))) : gen_normal_case.prio_mask_q[2])

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T3,T5

 LINE       128
 SUB-EXPRESSION 
 Number  Term
      1  gen_normal_case.mask_tree[gen_normal_case.gen_tree[2].gen_level[2].Pa] | 
      2  (gen_normal_case.sel_tree[gen_normal_case.gen_tree[2].gen_level[2].Pa] & ((~ready_i))))

-1-	-2-	Status	Tests
0	0	Covered	T1,T3,T8
0	1	Covered	T1,T3,T8
1	0	Covered	T1,T3,T5

 LINE       128
 SUB-EXPRESSION (gen_normal_case.sel_tree[gen_normal_case.gen_tree[2].gen_level[2].Pa] & ((~ready_i)))
                 ----------------------------------1----------------------------------   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T3,T5
1	0	Covered	T1,T3,T8
1	1	Covered	T1,T3,T8

 LINE       128
 EXPRESSION 
 Number  Term
      1  ((|req_i)) ? (gen_normal_case.mask_tree[gen_normal_case.gen_tree[2].gen_level[3].Pa] | (gen_normal_case.sel_tree[gen_normal_case.gen_tree[2].gen_level[3].Pa] & ((~ready_i)))) : gen_normal_case.prio_mask_q[3])

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T3,T5

 LINE       128
 SUB-EXPRESSION 
 Number  Term
      1  gen_normal_case.mask_tree[gen_normal_case.gen_tree[2].gen_level[3].Pa] | 
      2  (gen_normal_case.sel_tree[gen_normal_case.gen_tree[2].gen_level[3].Pa] & ((~ready_i))))

-1-	-2-	Status	Tests
0	0	Covered	T1,T3,T8
0	1	Covered	T1,T3,T8
1	0	Covered	T1,T3,T5

 LINE       128
 SUB-EXPRESSION (gen_normal_case.sel_tree[gen_normal_case.gen_tree[2].gen_level[3].Pa] & ((~ready_i)))
                 ----------------------------------1----------------------------------   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T3,T5
1	0	Covered	T1,T3,T8
1	1	Covered	T1,T3,T8

 LINE       148
 EXPRESSION 
 Number  Term
      1  ((~gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])) | 
      2  (((~gen_normal_case.prio_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])) & gen_normal_case.prio_tree[gen_normal_case.gen_tree[0].gen_level[0].C1]))

-1-	-2-	Status	Tests
0	0	Covered	T1,T3,T5
0	1	Covered	T1,T3,T8
1	0	Covered	T1,T2,T3

 LINE       148
 SUB-EXPRESSION 
 Number  Term
      1  ((~gen_normal_case.prio_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])) & 
      2  gen_normal_case.prio_tree[gen_normal_case.gen_tree[0].gen_level[0].C1])

-1-	-2-	Status	Tests
0	1	Covered	T1,T3,T5
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T3,T8

 LINE       148
 EXPRESSION 
 Number  Term
      1  ((~gen_normal_case.req_tree[gen_normal_case.gen_tree[1].gen_level[0].C0])) | 
      2  (((~gen_normal_case.prio_tree[gen_normal_case.gen_tree[1].gen_level[0].C0])) & gen_normal_case.prio_tree[gen_normal_case.gen_tree[1].gen_level[0].C1]))

-1-	-2-	Status	Tests
0	0	Covered	T1,T3,T5
0	1	Covered	T1,T3,T5
1	0	Covered	T1,T2,T3

 LINE       148
 SUB-EXPRESSION 
 Number  Term
      1  ((~gen_normal_case.prio_tree[gen_normal_case.gen_tree[1].gen_level[0].C0])) & 
      2  gen_normal_case.prio_tree[gen_normal_case.gen_tree[1].gen_level[0].C1])

-1-	-2-	Status	Tests
0	1	Covered	T1,T3,T5
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T3,T5

 LINE       148
 EXPRESSION 
 Number  Term
      1  ((~gen_normal_case.req_tree[gen_normal_case.gen_tree[1].gen_level[1].C0])) | 
      2  (((~gen_normal_case.prio_tree[gen_normal_case.gen_tree[1].gen_level[1].C0])) & gen_normal_case.prio_tree[gen_normal_case.gen_tree[1].gen_level[1].C1]))

-1-	-2-	Status	Tests
0	0	Covered	T1,T3,T5
0	1	Covered	T1,T3,T8
1	0	Covered	T1,T2,T3

 LINE       148
 SUB-EXPRESSION 
 Number  Term
      1  ((~gen_normal_case.prio_tree[gen_normal_case.gen_tree[1].gen_level[1].C0])) & 
      2  gen_normal_case.prio_tree[gen_normal_case.gen_tree[1].gen_level[1].C1])

-1-	-2-	Status	Tests
0	1	Covered	T1,T3,T5
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T3,T8

 LINE       150
 EXPRESSION (gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C0] | gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C1])
             ----------------------------------1----------------------------------   ----------------------------------2----------------------------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T12,T103,T104
1	0	Covered	T12,T103,T104

 LINE       150
 EXPRESSION (gen_normal_case.req_tree[gen_normal_case.gen_tree[1].gen_level[0].C0] | gen_normal_case.req_tree[gen_normal_case.gen_tree[1].gen_level[0].C1])
             ----------------------------------1----------------------------------   ----------------------------------2----------------------------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T3,T5
1	0	Covered	T1,T3,T8

 LINE       150
 EXPRESSION (gen_normal_case.req_tree[gen_normal_case.gen_tree[1].gen_level[1].C0] | gen_normal_case.req_tree[gen_normal_case.gen_tree[1].gen_level[1].C1])
             ----------------------------------1----------------------------------   ----------------------------------2----------------------------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T3,T8
1	0	Covered	T1,T3,T5

 LINE       151
 EXPRESSION (gen_normal_case.prio_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] | gen_normal_case.prio_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])
             -----------------------------------1----------------------------------   -----------------------------------2----------------------------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T12,T103,T104
1	0	Covered	T1,T3,T8

 LINE       151
 EXPRESSION (gen_normal_case.prio_tree[gen_normal_case.gen_tree[1].gen_level[0].C1] | gen_normal_case.prio_tree[gen_normal_case.gen_tree[1].gen_level[0].C0])
             -----------------------------------1----------------------------------   -----------------------------------2----------------------------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T30,T103,T104
1	0	Covered	T1,T3,T5

 LINE       151
 EXPRESSION (gen_normal_case.prio_tree[gen_normal_case.gen_tree[1].gen_level[1].C1] | gen_normal_case.prio_tree[gen_normal_case.gen_tree[1].gen_level[1].C0])
             -----------------------------------1----------------------------------   -----------------------------------2----------------------------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T3,T5
1	0	Covered	T1,T3,T8

 LINE       155
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])

-1-	Status	Tests
0	Covered	T1,T3,T5
1	Covered	T1,T2,T3

 LINE       155
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[1].gen_level[0].gen_nodes.sel ? gen_normal_case.idx_tree[gen_normal_case.gen_tree[1].gen_level[0].C1] : gen_normal_case.idx_tree[gen_normal_case.gen_tree[1].gen_level[0].C0])

-1-	Status	Tests
0	Covered	T1,T3,T5
1	Covered	T1,T2,T3

 LINE       155
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[1].gen_level[1].gen_nodes.sel ? gen_normal_case.idx_tree[gen_normal_case.gen_tree[1].gen_level[1].C1] : gen_normal_case.idx_tree[gen_normal_case.gen_tree[1].gen_level[1].C0])

-1-	Status	Tests
0	Covered	T1,T3,T5
1	Covered	T1,T2,T3

 LINE       156
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])

-1-	Status	Tests
0	Covered	T1,T3,T5
1	Covered	T1,T2,T3

 LINE       156
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[1].gen_level[0].gen_nodes.sel ? gen_normal_case.data_tree[gen_normal_case.gen_tree[1].gen_level[0].C1] : gen_normal_case.data_tree[gen_normal_case.gen_tree[1].gen_level[0].C0])

-1-	Status	Tests
0	Covered	T1,T3,T5
1	Covered	T1,T2,T3

 LINE       156
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[1].gen_level[1].gen_nodes.sel ? gen_normal_case.data_tree[gen_normal_case.gen_tree[1].gen_level[1].C1] : gen_normal_case.data_tree[gen_normal_case.gen_tree[1].gen_level[1].C0])

-1-	Status	Tests
0	Covered	T1,T3,T5
1	Covered	T1,T2,T3

 LINE       160
 EXPRESSION (gen_normal_case.sel_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & ((~gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)))
             ----------------------------------1----------------------------------   -----------------------------2-----------------------------

-1-	-2-	Status	Tests
0	1	Unreachable
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T3,T5

 LINE       160
 EXPRESSION (gen_normal_case.sel_tree[gen_normal_case.gen_tree[1].gen_level[0].Pa] & ((~gen_normal_case.gen_tree[1].gen_level[0].gen_nodes.sel)))
             ----------------------------------1----------------------------------   -----------------------------2-----------------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T3,T8
1	0	Covered	T1,T3,T5
1	1	Covered	T1,T3,T5

 LINE       160
 EXPRESSION (gen_normal_case.sel_tree[gen_normal_case.gen_tree[1].gen_level[1].Pa] & ((~gen_normal_case.gen_tree[1].gen_level[1].gen_nodes.sel)))
             ----------------------------------1----------------------------------   -----------------------------2-----------------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T3,T5
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T3,T8

 LINE       161
 EXPRESSION (gen_normal_case.sel_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)
             ----------------------------------1----------------------------------   ---------------------------2--------------------------

-1-	-2-	Status	Tests
0	1	Unreachable
1	0	Covered	T1,T3,T5
1	1	Covered	T1,T2,T3

 LINE       161
 EXPRESSION (gen_normal_case.sel_tree[gen_normal_case.gen_tree[1].gen_level[0].Pa] & gen_normal_case.gen_tree[1].gen_level[0].gen_nodes.sel)
             ----------------------------------1----------------------------------   ---------------------------2--------------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T3,T5
1	1	Covered	T1,T3,T5

 LINE       161
 EXPRESSION (gen_normal_case.sel_tree[gen_normal_case.gen_tree[1].gen_level[1].Pa] & gen_normal_case.gen_tree[1].gen_level[1].gen_nodes.sel)
             ----------------------------------1----------------------------------   ---------------------------2--------------------------

-1-	-2-	Status	Tests
0	1	Covered	T31,T25,T12
1	0	Covered	T1,T3,T8
1	1	Covered	T1,T2,T3

 LINE       164
 EXPRESSION (gen_normal_case.mask_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] | gen_normal_case.sel_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])
             -----------------------------------1----------------------------------   ----------------------------------2----------------------------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T3,T5
1	0	Unreachable

 LINE       164
 EXPRESSION (gen_normal_case.mask_tree[gen_normal_case.gen_tree[1].gen_level[0].Pa] | gen_normal_case.sel_tree[gen_normal_case.gen_tree[1].gen_level[0].C0])
             -----------------------------------1----------------------------------   ----------------------------------2----------------------------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T3,T5
1	0	Unreachable

 LINE       164
 EXPRESSION (gen_normal_case.mask_tree[gen_normal_case.gen_tree[1].gen_level[1].Pa] | gen_normal_case.sel_tree[gen_normal_case.gen_tree[1].gen_level[1].C0])
             -----------------------------------1----------------------------------   ----------------------------------2----------------------------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T3,T8
1	0	Covered	T1,T3,T5

---

Branch Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_rd.u_valid_random

	Line No.	Total	Covered	Percent
Branches		22	22	100.00
TERNARY	155	2	2	100.00
TERNARY	156	2	2	100.00
TERNARY	155	2	2	100.00
TERNARY	156	2	2	100.00
TERNARY	155	2	2	100.00
TERNARY	156	2	2	100.00
TERNARY	128	2	2	100.00
TERNARY	128	2	2	100.00
TERNARY	128	2	2	100.00
TERNARY	128	2	2	100.00
IF	191	2	2	100.00

155                  assign idx_tree[Pa]  = (sel) ? idx_tree[C1]  : idx_tree[C0];
                                                  -1-  
                                                  ==>  
                                                  ==>  

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T3,T5

156                  assign data_tree[Pa] = (sel) ? data_tree[C1] : data_tree[C0];
                                                  -1-  
                                                  ==>  
                                                  ==>  

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T3,T5

155                  assign idx_tree[Pa]  = (sel) ? idx_tree[C1]  : idx_tree[C0];
                                                  -1-  
                                                  ==>  
                                                  ==>  

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T3,T5

156                  assign data_tree[Pa] = (sel) ? data_tree[C1] : data_tree[C0];
                                                  -1-  
                                                  ==>  
                                                  ==>  

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T3,T5

155                  assign idx_tree[Pa]  = (sel) ? idx_tree[C1]  : idx_tree[C0];
                                                  -1-  
                                                  ==>  
                                                  ==>  

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T3,T5

156                  assign data_tree[Pa] = (sel) ? data_tree[C1] : data_tree[C0];
                                                  -1-  
                                                  ==>  
                                                  ==>  

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T3,T5

128                    assign prio_mask_d[offset] = (|req_i) ?
                                                             -1-  
                                                             ==>  
                                                             ==>  

Branches:

-1-	Status	Tests
1	Covered	T1,T3,T5
0	Covered	T1,T2,T3

128                    assign prio_mask_d[offset] = (|req_i) ?
                                                             -1-  
                                                             ==>  
                                                             ==>  

Branches:

-1-	Status	Tests
1	Covered	T1,T3,T5
0	Covered	T1,T2,T3

128                    assign prio_mask_d[offset] = (|req_i) ?
                                                             -1-  
                                                             ==>  
                                                             ==>  

Branches:

-1-	Status	Tests
1	Covered	T1,T3,T5
0	Covered	T1,T2,T3

128                    assign prio_mask_d[offset] = (|req_i) ?
                                                             -1-  
                                                             ==>  
                                                             ==>  

Branches:

-1-	Status	Tests
1	Covered	T1,T3,T5
0	Covered	T1,T2,T3

191              if (!rst_ni) begin
                 -1-  
192                prio_mask_q <= '0;
                   ==>
193              end else begin
194                prio_mask_q <= prio_mask_d;
                   ==>

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_rd.u_valid_random

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	15	15	100.00	12	80.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	15	15	100.00	12	80.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	391176692	390364170	0	0
CheckNGreaterZero_A	1051	1051	0	0
GntImpliesReady_A	391176692	2579774	0	0
GntImpliesValid_A	391176692	2579774	0	0
GrantKnown_A	391176692	390364170	0	0
IdxKnown_A	391176692	390364170	0	0
IndexIsCorrect_A	391176692	2579774	0	0
LockArbDecision_A	391176692	0	0	0
NoReadyValidNoGrant_A	391176692	269714767	0	0
ReadyAndValidImplyGrant_A	391176692	2579774	0	0
ReqAndReadyImplyGrant_A	391176692	2579774	0	0
ReqImpliesValid_A	391176692	115185371	0	0
ReqStaysHighUntilGranted0_M	391176692	0	0	0
RoundRobin_A	391176692	0	0	1047
ValidKnown_A	391176692	390364170	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	391176692	390364170	0	0
T1	2070	1970	0	0
T2	3480	3381	0	0
T3	1887	1822	0	0
T4	4370	3912	0	0
T5	677	579	0	0
T8	45213	45151	0	0
T9	1406	1318	0	0
T10	2124	2046	0	0
T16	1541	1471	0	0
T17	1625	1542	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1051	1051	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	391176692	2579774	0	0
T1	2070	50	0	0
T2	3480	0	0	0
T3	1887	69	0	0
T4	4370	0	0	0
T5	677	1	0	0
T8	45213	297	0	0
T9	1406	1	0	0
T10	2124	2	0	0
T11	0	2	0	0
T16	1541	0	0	0
T17	1625	0	0	0
T22	0	24	0	0
T25	0	81	0	0
T31	0	29	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	391176692	2579774	0	0
T1	2070	50	0	0
T2	3480	0	0	0
T3	1887	69	0	0
T4	4370	0	0	0
T5	677	1	0	0
T8	45213	297	0	0
T9	1406	1	0	0
T10	2124	2	0	0
T11	0	2	0	0
T16	1541	0	0	0
T17	1625	0	0	0
T22	0	24	0	0
T25	0	81	0	0
T31	0	29	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	391176692	390364170	0	0
T1	2070	1970	0	0
T2	3480	3381	0	0
T3	1887	1822	0	0
T4	4370	3912	0	0
T5	677	579	0	0
T8	45213	45151	0	0
T9	1406	1318	0	0
T10	2124	2046	0	0
T16	1541	1471	0	0
T17	1625	1542	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	391176692	390364170	0	0
T1	2070	1970	0	0
T2	3480	3381	0	0
T3	1887	1822	0	0
T4	4370	3912	0	0
T5	677	579	0	0
T8	45213	45151	0	0
T9	1406	1318	0	0
T10	2124	2046	0	0
T16	1541	1471	0	0
T17	1625	1542	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	391176692	2579774	0	0
T1	2070	50	0	0
T2	3480	0	0	0
T3	1887	69	0	0
T4	4370	0	0	0
T5	677	1	0	0
T8	45213	297	0	0
T9	1406	1	0	0
T10	2124	2	0	0
T11	0	2	0	0
T16	1541	0	0	0
T17	1625	0	0	0
T22	0	24	0	0
T25	0	81	0	0
T31	0	29	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	391176692	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	391176692	269714767	0	0
T1	2070	530	0	0
T2	3480	3349	0	0
T3	1887	419	0	0
T4	4370	3720	0	0
T5	677	527	0	0
T8	45213	1778	0	0
T9	1406	286	0	0
T10	2124	1037	0	0
T16	1541	1439	0	0
T17	1625	1510	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	391176692	2579774	0	0
T1	2070	50	0	0
T2	3480	0	0	0
T3	1887	69	0	0
T4	4370	0	0	0
T5	677	1	0	0
T8	45213	297	0	0
T9	1406	1	0	0
T10	2124	2	0	0
T11	0	2	0	0
T16	1541	0	0	0
T17	1625	0	0	0
T22	0	24	0	0
T25	0	81	0	0
T31	0	29	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	391176692	2579774	0	0
T1	2070	50	0	0
T2	3480	0	0	0
T3	1887	69	0	0
T4	4370	0	0	0
T5	677	1	0	0
T8	45213	297	0	0
T9	1406	1	0	0
T10	2124	2	0	0
T11	0	2	0	0
T16	1541	0	0	0
T17	1625	0	0	0
T22	0	24	0	0
T25	0	81	0	0
T31	0	29	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	391176692	115185371	0	0
T1	2070	1404	0	0
T2	3480	0	0	0
T3	1887	1367	0	0
T4	4370	0	0	0
T5	677	16	0	0
T8	45213	43337	0	0
T9	1406	996	0	0
T10	2124	969	0	0
T11	0	8	0	0
T16	1541	0	0	0
T17	1625	0	0	0
T22	0	854	0	0
T25	0	2764	0	0
T31	0	370	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	391176692	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	391176692	0	0	1047

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	391176692	390364170	0	0
T1	2070	1970	0	0
T2	3480	3381	0	0
T3	1887	1822	0	0
T4	4370	3912	0	0
T5	677	579	0	0
T8	45213	45151	0	0
T9	1406	1318	0	0
T10	2124	2046	0	0
T16	1541	1471	0	0
T17	1625	1542	0	0

Line Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_rd.u_valid_random

	Line No.	Total	Covered	Percent
TOTAL		52	48	92.31
CONT_ASSIGN	62	0	0
CONT_ASSIGN	112	1	1	100.00
CONT_ASSIGN	112	1	1	100.00
CONT_ASSIGN	112	1	1	100.00
CONT_ASSIGN	112	1	1	100.00
CONT_ASSIGN	118	1	1	100.00
CONT_ASSIGN	118	1	1	100.00
CONT_ASSIGN	118	1	1	100.00
CONT_ASSIGN	118	1	1	100.00
CONT_ASSIGN	122	1	0	0.00
CONT_ASSIGN	122	1	0	0.00
CONT_ASSIGN	122	1	0	0.00
CONT_ASSIGN	122	1	0	0.00
CONT_ASSIGN	126	1	1	100.00
CONT_ASSIGN	126	1	1	100.00
CONT_ASSIGN	126	1	1	100.00
CONT_ASSIGN	126	1	1	100.00
CONT_ASSIGN	128	1	1	100.00
CONT_ASSIGN	128	1	1	100.00
CONT_ASSIGN	128	1	1	100.00
CONT_ASSIGN	128	1	1	100.00
CONT_ASSIGN	148	1	1	100.00
CONT_ASSIGN	148	1	1	100.00
CONT_ASSIGN	148	1	1	100.00
CONT_ASSIGN	150	1	1	100.00
CONT_ASSIGN	150	1	1	100.00
CONT_ASSIGN	150	1	1	100.00
CONT_ASSIGN	151	1	1	100.00
CONT_ASSIGN	151	1	1	100.00
CONT_ASSIGN	151	1	1	100.00
CONT_ASSIGN	155	1	1	100.00
CONT_ASSIGN	155	1	1	100.00
CONT_ASSIGN	155	1	1	100.00
CONT_ASSIGN	156	1	1	100.00
CONT_ASSIGN	156	1	1	100.00
CONT_ASSIGN	156	1	1	100.00
CONT_ASSIGN	160	1	1	100.00
CONT_ASSIGN	160	1	1	100.00
CONT_ASSIGN	160	1	1	100.00
CONT_ASSIGN	161	1	1	100.00
CONT_ASSIGN	161	1	1	100.00
CONT_ASSIGN	161	1	1	100.00
CONT_ASSIGN	163	0	0
CONT_ASSIGN	163	0	0
CONT_ASSIGN	163	1	1	100.00
CONT_ASSIGN	164	1	1	100.00
CONT_ASSIGN	164	1	1	100.00
CONT_ASSIGN	164	1	1	100.00
CONT_ASSIGN	174	1	1	100.00
CONT_ASSIGN	180	1	1	100.00
CONT_ASSIGN	182	1	1	100.00
CONT_ASSIGN	183	1	1	100.00
ALWAYS	191	3	3	100.00

61                        logic unused_req_chk;
62         unreachable    assign unused_req_chk = req_chk_i;
63                      
64                        `ASSERT_INIT(CheckNGreaterZero_A, N > 0)
65                      
66                        // this case is basically just a bypass
67                        if (N == 1) begin : gen_degenerate_case
68                      
69                          assign valid_o  = req_i[0];
70                          assign data_o   = data_i[0];
71                          assign gnt_o[0] = valid_o & ready_i;
72                          assign idx_o    = '0;
73                      
74                        end else begin : gen_normal_case
75                      
76                          // align to powers of 2 for simplicity
77                          // a full binary tree with N levels has 2**N + 2**N-1 nodes
78                          logic [2**(IdxW+1)-2:0]           req_tree;
79                          logic [2**(IdxW+1)-2:0]           prio_tree;
80                          logic [2**(IdxW+1)-2:0]           sel_tree;
81                          logic [2**(IdxW+1)-2:0]           mask_tree;
82                          logic [2**(IdxW+1)-2:0][IdxW-1:0] idx_tree;
83                          logic [2**(IdxW+1)-2:0][DW-1:0]   data_tree;
84                          logic [N-1:0]                     prio_mask_d, prio_mask_q;
85                      
86                          for (genvar level = 0; level < IdxW+1; level++) begin : gen_tree
87                            //
88                            // level+1   C0   C1   <- "Base1" points to the first node on "level+1",
89                            //            \  /         these nodes are the children of the nodes one level below
90                            // level       Pa      <- "Base0", points to the first node on "level",
91                            //                         these nodes are the parents of the nodes one level above
92                            //
93                            // hence we have the following indices for the Pa, C0, C1 nodes:
94                            // Pa = 2**level     - 1 + offset       = Base0 + offset
95                            // C0 = 2**(level+1) - 1 + 2*offset     = Base1 + 2*offset
96                            // C1 = 2**(level+1) - 1 + 2*offset + 1 = Base1 + 2*offset + 1
97                            //
98                            localparam int Base0 = (2**level)-1;
99                            localparam int Base1 = (2**(level+1))-1;
100                     
101                           for (genvar offset = 0; offset < 2**level; offset++) begin : gen_level
102                             localparam int Pa = Base0 + offset;
103                             localparam int C0 = Base1 + 2*offset;
104                             localparam int C1 = Base1 + 2*offset + 1;
105                     
106                             // this assigns the gated interrupt source signals, their
107                             // corresponding IDs and priorities to the tree leafs
108                             if (level == IdxW) begin : gen_leafs
109                               if (offset < N) begin : gen_assign
110                                 // forward path (requests and data)
111                                 // all requests inputs are assigned to the request tree
112        4/4                      assign req_tree[Pa]      = req_i[offset];
           Tests:       T1 T2 T3  | T1 T2 T3  | T1 T2 T3  | T1 T2 T3 
113                                 // we basically split the incoming request vector into two halves with the following
114                                 // priority assignment. the prio_mask_q register contains a prefix sum that has been
115                                 // computed using the last winning index, and hence masks out all requests at offsets
116                                 // lower or equal the previously granted index. hence, all higher indices are considered
117                                 // first in the arbitration tree nodes below, before considering the lower indices.
118        4/4                      assign prio_tree[Pa]     = req_i[offset] & prio_mask_q[offset];
           Tests:       T1 T2 T3  | T1 T2 T3  | T1 T2 T3  | T1 T2 T3 
119                                 // input for the index muxes (used to compute the winner index)
120                                 assign idx_tree[Pa]      = offset;
121                                 // input for the data muxes
122        0/4     ==>              assign data_tree[Pa]     = data_i[offset];
123                     
124                                 // backward path (grants and prefix sum)
125                                 // grant if selected, ready and request asserted
126        4/4                      assign gnt_o[offset]       = req_i[offset] & sel_tree[Pa] & ready_i;
           Tests:       T1 T2 T3  | T1 T2 T3  | T1 T2 T3  | T1 T2 T3 
127                                 // only update mask if there is a valid request
128        4/4                      assign prio_mask_d[offset] = (|req_i) ?
           Tests:       T1 T2 T3  | T1 T2 T3  | T1 T2 T3  | T1 T2 T3 
129                                                              mask_tree[Pa] | sel_tree[Pa] & ~ready_i :
130                                                              prio_mask_q[offset];
131                               end else begin : gen_tie_off
132                                 // forward path
133                                 assign req_tree[Pa]  = '0;
134                                 assign prio_tree[Pa] = '0;
135                                 assign idx_tree[Pa]  = '0;
136                                 assign data_tree[Pa] = '0;
137                                 logic unused_sigs;
138                                 assign unused_sigs = ^{mask_tree[Pa],
139                                                        sel_tree[Pa]};
140                               end
141                             // this creates the node assignments
142                             end else begin : gen_nodes
143                               // local helper variable
144                               logic sel;
145                     
146                               // forward path (requests and data)
147                               // each node looks at its two children, and selects the one with higher priority
148        3/3                    assign sel = ~req_tree[C0] | ~prio_tree[C0] & prio_tree[C1];
           Tests:       T1 T2 T3  | T1 T2 T3  | T1 T2 T3 
149                               // propagate requests
150        3/3                    assign req_tree[Pa]  = req_tree[C0] | req_tree[C1];
           Tests:       T1 T2 T3  | T1 T2 T3  | T1 T2 T3 
151        3/3                    assign prio_tree[Pa] = prio_tree[C1] | prio_tree[C0];
           Tests:       T1 T2 T3  | T1 T2 T3  | T1 T2 T3 
152                               // data and index muxes
153                               // Note: these ternaries have triggered a synthesis bug in Vivado versions older
154                               // than 2020.2. If the problem resurfaces again, have a look at issue #1408.
155        3/3                    assign idx_tree[Pa]  = (sel) ? idx_tree[C1]  : idx_tree[C0];
           Tests:       T1 T2 T3  | T1 T2 T3  | T1 T2 T3 
156        3/3                    assign data_tree[Pa] = (sel) ? data_tree[C1] : data_tree[C0];
           Tests:       T1 T2 T3  | T1 T2 T3  | T1 T2 T3 
157                     
158                               // backward path (grants and prefix sum)
159                               // this propagates the selction index back and computes a hot one mask
160        3/3                    assign sel_tree[C0] = sel_tree[Pa] & ~sel;
           Tests:       T1 T2 T3  | T1 T2 T3  | T1 T2 T3 
161        3/3                    assign sel_tree[C1] = sel_tree[Pa] &  sel;
           Tests:       T1 T2 T3  | T1 T2 T3  | T1 T2 T3 
162                               // this performs a prefix sum for masking the input requests in the next cycle
163        1/1(2 unreachable)            assign mask_tree[C0] = mask_tree[Pa];
           Tests:       T1 T2 T3 
164        3/3                    assign mask_tree[C1] = mask_tree[Pa] | sel_tree[C0];
           Tests:       T1 T2 T3  | T1 T2 T3  | T1 T2 T3 
165                             end
166                           end : gen_level
167                         end : gen_tree
168                     
169                         // the results can be found at the tree root
170                         if (EnDataPort) begin : gen_data_port
171                           assign data_o      = data_tree[0];
172                         end else begin : gen_no_dataport
173                           logic [DW-1:0] unused_data;
174        1/1                assign unused_data = data_tree[0];
           Tests:       T1 T2 T3 
175                           assign data_o = '1;
176                         end
177                     
178                         // This index is unused.
179                         logic unused_prio_tree;
180        1/1              assign unused_prio_tree = prio_tree[0];
           Tests:       T1 T2 T3 
181                     
182        1/1              assign idx_o       = idx_tree[0];
           Tests:       T1 T2 T3 
183        1/1              assign valid_o     = req_tree[0];
           Tests:       T1 T2 T3 
184                     
185                         // the select tree computes a hot one signal that indicates which request is currently selected
186                         assign sel_tree[0] = 1'b1;
187                         // the mask tree is basically a prefix sum of the hot one select signal computed above
188                         assign mask_tree[0] = 1'b0;
189                     
190                         always_ff @(posedge clk_i or negedge rst_ni) begin : p_mask_reg
191        1/1                if (!rst_ni) begin
           Tests:       T1 T2 T3 
192        1/1                  prio_mask_q <= '0;
           Tests:       T1 T2 T3 
193                           end else begin
194        1/1                  prio_mask_q <= prio_mask_d;
           Tests:       T1 T2 T3 

---

Cond Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_rd.u_valid_random

	Total	Covered	Percent
Conditions	130	127	97.69
Logical	130	127	97.69
Non-Logical	0	0
Event	0	0

 LINE       118
 EXPRESSION (req_i[0] & gen_normal_case.prio_mask_q[0])
             ----1---   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T22,T12,T32
1	0	Covered	T8,T31,T25
1	1	Covered	T8,T31,T25

 LINE       118
 EXPRESSION (req_i[1] & gen_normal_case.prio_mask_q[1])
             ----1---   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T22,T12,T32
1	0	Covered	T8,T31,T25
1	1	Covered	T8,T31,T25

 LINE       118
 EXPRESSION (req_i[2] & gen_normal_case.prio_mask_q[2])
             ----1---   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T22,T12,T30
1	0	Covered	T8,T31,T25
1	1	Covered	T8,T31,T25

 LINE       118
 EXPRESSION (req_i[3] & gen_normal_case.prio_mask_q[3])
             ----1---   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T8,T31,T25
1	0	Covered	T59,T60,T211
1	1	Covered	T8,T31,T25

 LINE       126
 EXPRESSION (req_i[0] & gen_normal_case.sel_tree[gen_normal_case.gen_tree[2].gen_level[0].Pa] & ready_i)
             ----1---   ----------------------------------2----------------------------------   ---3---

-1-	-2-	-3-	Status	Tests
0	1	1	Not Covered
1	0	1	Covered	T8,T31,T25
1	1	0	Covered	T8,T31,T25
1	1	1	Covered	T8,T31,T25

 LINE       126
 EXPRESSION (req_i[1] & gen_normal_case.sel_tree[gen_normal_case.gen_tree[2].gen_level[1].Pa] & ready_i)
             ----1---   ----------------------------------2----------------------------------   ---3---

-1-	-2-	-3-	Status	Tests
0	1	1	Not Covered
1	0	1	Covered	T8,T31,T25
1	1	0	Covered	T8,T31,T25
1	1	1	Covered	T8,T31,T25

 LINE       126
 EXPRESSION (req_i[2] & gen_normal_case.sel_tree[gen_normal_case.gen_tree[2].gen_level[2].Pa] & ready_i)
             ----1---   ----------------------------------2----------------------------------   ---3---

-1-	-2-	-3-	Status	Tests
0	1	1	Not Covered
1	0	1	Covered	T8,T31,T25
1	1	0	Covered	T8,T31,T25
1	1	1	Covered	T8,T25,T11

 LINE       126
 EXPRESSION (req_i[3] & gen_normal_case.sel_tree[gen_normal_case.gen_tree[2].gen_level[3].Pa] & ready_i)
             ----1---   ----------------------------------2----------------------------------   ---3---

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T8,T31,T25
1	0	1	Covered	T8,T31,T25
1	1	0	Covered	T8,T25,T11
1	1	1	Covered	T8,T25,T11

 LINE       128
 EXPRESSION 
 Number  Term
      1  ((|req_i)) ? (gen_normal_case.mask_tree[gen_normal_case.gen_tree[2].gen_level[0].Pa] | (gen_normal_case.sel_tree[gen_normal_case.gen_tree[2].gen_level[0].Pa] & ((~ready_i)))) : gen_normal_case.prio_mask_q[0])

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T8,T31,T25

 LINE       128
 SUB-EXPRESSION 
 Number  Term
      1  gen_normal_case.mask_tree[gen_normal_case.gen_tree[2].gen_level[0].Pa] | 
      2  (gen_normal_case.sel_tree[gen_normal_case.gen_tree[2].gen_level[0].Pa] & ((~ready_i))))

-1-	-2-	Status	Tests
0	0	Covered	T8,T31,T25
0	1	Covered	T8,T31,T25
1	0	Unreachable

 LINE       128
 SUB-EXPRESSION (gen_normal_case.sel_tree[gen_normal_case.gen_tree[2].gen_level[0].Pa] & ((~ready_i)))
                 ----------------------------------1----------------------------------   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T8,T31,T25
1	0	Covered	T8,T31,T25
1	1	Covered	T8,T31,T25

 LINE       128
 EXPRESSION 
 Number  Term
      1  ((|req_i)) ? (gen_normal_case.mask_tree[gen_normal_case.gen_tree[2].gen_level[1].Pa] | (gen_normal_case.sel_tree[gen_normal_case.gen_tree[2].gen_level[1].Pa] & ((~ready_i)))) : gen_normal_case.prio_mask_q[1])

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T8,T31,T25

 LINE       128
 SUB-EXPRESSION 
 Number  Term
      1  gen_normal_case.mask_tree[gen_normal_case.gen_tree[2].gen_level[1].Pa] | 
      2  (gen_normal_case.sel_tree[gen_normal_case.gen_tree[2].gen_level[1].Pa] & ((~ready_i))))

-1-	-2-	Status	Tests
0	0	Covered	T8,T31,T25
0	1	Covered	T8,T31,T25
1	0	Covered	T8,T31,T25

 LINE       128
 SUB-EXPRESSION (gen_normal_case.sel_tree[gen_normal_case.gen_tree[2].gen_level[1].Pa] & ((~ready_i)))
                 ----------------------------------1----------------------------------   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T8,T31,T25
1	0	Covered	T8,T31,T25
1	1	Covered	T8,T31,T25

 LINE       128
 EXPRESSION 
 Number  Term
      1  ((|req_i)) ? (gen_normal_case.mask_tree[gen_normal_case.gen_tree[2].gen_level[2].Pa] | (gen_normal_case.sel_tree[gen_normal_case.gen_tree[2].gen_level[2].Pa] & ((~ready_i)))) : gen_normal_case.prio_mask_q[2])

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T8,T31,T25

 LINE       128
 SUB-EXPRESSION 
 Number  Term
      1  gen_normal_case.mask_tree[gen_normal_case.gen_tree[2].gen_level[2].Pa] | 
      2  (gen_normal_case.sel_tree[gen_normal_case.gen_tree[2].gen_level[2].Pa] & ((~ready_i))))

-1-	-2-	Status	Tests
0	0	Covered	T8,T25,T11
0	1	Covered	T8,T31,T25
1	0	Covered	T8,T31,T25

 LINE       128
 SUB-EXPRESSION (gen_normal_case.sel_tree[gen_normal_case.gen_tree[2].gen_level[2].Pa] & ((~ready_i)))
                 ----------------------------------1----------------------------------   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T8,T31,T25
1	0	Covered	T8,T25,T11
1	1	Covered	T8,T31,T25

 LINE       128
 EXPRESSION 
 Number  Term
      1  ((|req_i)) ? (gen_normal_case.mask_tree[gen_normal_case.gen_tree[2].gen_level[3].Pa] | (gen_normal_case.sel_tree[gen_normal_case.gen_tree[2].gen_level[3].Pa] & ((~ready_i)))) : gen_normal_case.prio_mask_q[3])

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T8,T31,T25

 LINE       128
 SUB-EXPRESSION 
 Number  Term
      1  gen_normal_case.mask_tree[gen_normal_case.gen_tree[2].gen_level[3].Pa] | 
      2  (gen_normal_case.sel_tree[gen_normal_case.gen_tree[2].gen_level[3].Pa] & ((~ready_i))))

-1-	-2-	Status	Tests
0	0	Covered	T8,T25,T11
0	1	Covered	T8,T25,T11
1	0	Covered	T8,T31,T25

 LINE       128
 SUB-EXPRESSION (gen_normal_case.sel_tree[gen_normal_case.gen_tree[2].gen_level[3].Pa] & ((~ready_i)))
                 ----------------------------------1----------------------------------   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T8,T31,T25
1	0	Covered	T8,T25,T11
1	1	Covered	T8,T25,T11

 LINE       148
 EXPRESSION 
 Number  Term
      1  ((~gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])) | 
      2  (((~gen_normal_case.prio_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])) & gen_normal_case.prio_tree[gen_normal_case.gen_tree[0].gen_level[0].C1]))

-1-	-2-	Status	Tests
0	0	Covered	T8,T31,T25
0	1	Covered	T8,T31,T25
1	0	Covered	T1,T2,T3

 LINE       148
 SUB-EXPRESSION 
 Number  Term
      1  ((~gen_normal_case.prio_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])) & 
      2  gen_normal_case.prio_tree[gen_normal_case.gen_tree[0].gen_level[0].C1])

-1-	-2-	Status	Tests
0	1	Covered	T8,T31,T25
1	0	Covered	T1,T2,T3
1	1	Covered	T8,T31,T25

 LINE       148
 EXPRESSION 
 Number  Term
      1  ((~gen_normal_case.req_tree[gen_normal_case.gen_tree[1].gen_level[0].C0])) | 
      2  (((~gen_normal_case.prio_tree[gen_normal_case.gen_tree[1].gen_level[0].C0])) & gen_normal_case.prio_tree[gen_normal_case.gen_tree[1].gen_level[0].C1]))

-1-	-2-	Status	Tests
0	0	Covered	T8,T31,T25
0	1	Covered	T8,T31,T25
1	0	Covered	T1,T2,T3

 LINE       148
 SUB-EXPRESSION 
 Number  Term
      1  ((~gen_normal_case.prio_tree[gen_normal_case.gen_tree[1].gen_level[0].C0])) & 
      2  gen_normal_case.prio_tree[gen_normal_case.gen_tree[1].gen_level[0].C1])

-1-	-2-	Status	Tests
0	1	Covered	T8,T31,T25
1	0	Covered	T1,T2,T3
1	1	Covered	T8,T31,T25

 LINE       148
 EXPRESSION 
 Number  Term
      1  ((~gen_normal_case.req_tree[gen_normal_case.gen_tree[1].gen_level[1].C0])) | 
      2  (((~gen_normal_case.prio_tree[gen_normal_case.gen_tree[1].gen_level[1].C0])) & gen_normal_case.prio_tree[gen_normal_case.gen_tree[1].gen_level[1].C1]))

-1-	-2-	Status	Tests
0	0	Covered	T8,T31,T25
0	1	Covered	T8,T25,T11
1	0	Covered	T1,T2,T3

 LINE       148
 SUB-EXPRESSION 
 Number  Term
      1  ((~gen_normal_case.prio_tree[gen_normal_case.gen_tree[1].gen_level[1].C0])) & 
      2  gen_normal_case.prio_tree[gen_normal_case.gen_tree[1].gen_level[1].C1])

-1-	-2-	Status	Tests
0	1	Covered	T8,T31,T25
1	0	Covered	T1,T2,T3
1	1	Covered	T8,T25,T11

 LINE       150
 EXPRESSION (gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C0] | gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C1])
             ----------------------------------1----------------------------------   ----------------------------------2----------------------------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T54,T43,T60
1	0	Covered	T54,T43,T60

 LINE       150
 EXPRESSION (gen_normal_case.req_tree[gen_normal_case.gen_tree[1].gen_level[0].C0] | gen_normal_case.req_tree[gen_normal_case.gen_tree[1].gen_level[0].C1])
             ----------------------------------1----------------------------------   ----------------------------------2----------------------------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T8,T31,T25
1	0	Covered	T8,T31,T25

 LINE       150
 EXPRESSION (gen_normal_case.req_tree[gen_normal_case.gen_tree[1].gen_level[1].C0] | gen_normal_case.req_tree[gen_normal_case.gen_tree[1].gen_level[1].C1])
             ----------------------------------1----------------------------------   ----------------------------------2----------------------------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T8,T25,T11
1	0	Covered	T8,T31,T25

 LINE       151
 EXPRESSION (gen_normal_case.prio_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] | gen_normal_case.prio_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])
             -----------------------------------1----------------------------------   -----------------------------------2----------------------------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T54,T43,T60
1	0	Covered	T8,T31,T25

 LINE       151
 EXPRESSION (gen_normal_case.prio_tree[gen_normal_case.gen_tree[1].gen_level[0].C1] | gen_normal_case.prio_tree[gen_normal_case.gen_tree[1].gen_level[0].C0])
             -----------------------------------1----------------------------------   -----------------------------------2----------------------------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T12,T104,T68
1	0	Covered	T8,T31,T25

 LINE       151
 EXPRESSION (gen_normal_case.prio_tree[gen_normal_case.gen_tree[1].gen_level[1].C1] | gen_normal_case.prio_tree[gen_normal_case.gen_tree[1].gen_level[1].C0])
             -----------------------------------1----------------------------------   -----------------------------------2----------------------------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T8,T31,T25
1	0	Covered	T8,T25,T11

 LINE       155
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])

-1-	Status	Tests
0	Covered	T8,T31,T25
1	Covered	T1,T2,T3

 LINE       155
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[1].gen_level[0].gen_nodes.sel ? gen_normal_case.idx_tree[gen_normal_case.gen_tree[1].gen_level[0].C1] : gen_normal_case.idx_tree[gen_normal_case.gen_tree[1].gen_level[0].C0])

-1-	Status	Tests
0	Covered	T8,T31,T25
1	Covered	T1,T2,T3

 LINE       155
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[1].gen_level[1].gen_nodes.sel ? gen_normal_case.idx_tree[gen_normal_case.gen_tree[1].gen_level[1].C1] : gen_normal_case.idx_tree[gen_normal_case.gen_tree[1].gen_level[1].C0])

-1-	Status	Tests
0	Covered	T8,T31,T25
1	Covered	T1,T2,T3

 LINE       156
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])

-1-	Status	Tests
0	Covered	T8,T31,T25
1	Covered	T1,T2,T3

 LINE       156
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[1].gen_level[0].gen_nodes.sel ? gen_normal_case.data_tree[gen_normal_case.gen_tree[1].gen_level[0].C1] : gen_normal_case.data_tree[gen_normal_case.gen_tree[1].gen_level[0].C0])

-1-	Status	Tests
0	Covered	T8,T31,T25
1	Covered	T1,T2,T3

 LINE       156
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[1].gen_level[1].gen_nodes.sel ? gen_normal_case.data_tree[gen_normal_case.gen_tree[1].gen_level[1].C1] : gen_normal_case.data_tree[gen_normal_case.gen_tree[1].gen_level[1].C0])

-1-	Status	Tests
0	Covered	T8,T31,T25
1	Covered	T1,T2,T3

 LINE       160
 EXPRESSION (gen_normal_case.sel_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & ((~gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)))
             ----------------------------------1----------------------------------   -----------------------------2-----------------------------

-1-	-2-	Status	Tests
0	1	Unreachable
1	0	Covered	T1,T2,T3
1	1	Covered	T8,T31,T25

 LINE       160
 EXPRESSION (gen_normal_case.sel_tree[gen_normal_case.gen_tree[1].gen_level[0].Pa] & ((~gen_normal_case.gen_tree[1].gen_level[0].gen_nodes.sel)))
             ----------------------------------1----------------------------------   -----------------------------2-----------------------------

-1-	-2-	Status	Tests
0	1	Covered	T8,T31,T25
1	0	Covered	T8,T31,T25
1	1	Covered	T8,T31,T25

 LINE       160
 EXPRESSION (gen_normal_case.sel_tree[gen_normal_case.gen_tree[1].gen_level[1].Pa] & ((~gen_normal_case.gen_tree[1].gen_level[1].gen_nodes.sel)))
             ----------------------------------1----------------------------------   -----------------------------2-----------------------------

-1-	-2-	Status	Tests
0	1	Covered	T8,T31,T25
1	0	Covered	T1,T2,T3
1	1	Covered	T8,T31,T25

 LINE       161
 EXPRESSION (gen_normal_case.sel_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)
             ----------------------------------1----------------------------------   ---------------------------2--------------------------

-1-	-2-	Status	Tests
0	1	Unreachable
1	0	Covered	T8,T31,T25
1	1	Covered	T1,T2,T3

 LINE       161
 EXPRESSION (gen_normal_case.sel_tree[gen_normal_case.gen_tree[1].gen_level[0].Pa] & gen_normal_case.gen_tree[1].gen_level[0].gen_nodes.sel)
             ----------------------------------1----------------------------------   ---------------------------2--------------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T8,T31,T25
1	1	Covered	T8,T31,T25

 LINE       161
 EXPRESSION (gen_normal_case.sel_tree[gen_normal_case.gen_tree[1].gen_level[1].Pa] & gen_normal_case.gen_tree[1].gen_level[1].gen_nodes.sel)
             ----------------------------------1----------------------------------   ---------------------------2--------------------------

-1-	-2-	Status	Tests
0	1	Covered	T12,T30,T104
1	0	Covered	T8,T31,T25
1	1	Covered	T1,T2,T3

 LINE       164
 EXPRESSION (gen_normal_case.mask_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] | gen_normal_case.sel_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])
             -----------------------------------1----------------------------------   ----------------------------------2----------------------------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T8,T31,T25
1	0	Unreachable

 LINE       164
 EXPRESSION (gen_normal_case.mask_tree[gen_normal_case.gen_tree[1].gen_level[0].Pa] | gen_normal_case.sel_tree[gen_normal_case.gen_tree[1].gen_level[0].C0])
             -----------------------------------1----------------------------------   ----------------------------------2----------------------------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T8,T31,T25
1	0	Unreachable

 LINE       164
 EXPRESSION (gen_normal_case.mask_tree[gen_normal_case.gen_tree[1].gen_level[1].Pa] | gen_normal_case.sel_tree[gen_normal_case.gen_tree[1].gen_level[1].C0])
             -----------------------------------1----------------------------------   ----------------------------------2----------------------------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T8,T31,T25
1	0	Covered	T8,T31,T25

---

Branch Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_rd.u_valid_random

	Line No.	Total	Covered	Percent
Branches		22	22	100.00
TERNARY	155	2	2	100.00
TERNARY	156	2	2	100.00
TERNARY	155	2	2	100.00
TERNARY	156	2	2	100.00
TERNARY	155	2	2	100.00
TERNARY	156	2	2	100.00
TERNARY	128	2	2	100.00
TERNARY	128	2	2	100.00
TERNARY	128	2	2	100.00
TERNARY	128	2	2	100.00
IF	191	2	2	100.00

155                  assign idx_tree[Pa]  = (sel) ? idx_tree[C1]  : idx_tree[C0];
                                                  -1-  
                                                  ==>  
                                                  ==>  

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T8,T31,T25

156                  assign data_tree[Pa] = (sel) ? data_tree[C1] : data_tree[C0];
                                                  -1-  
                                                  ==>  
                                                  ==>  

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T8,T31,T25

155                  assign idx_tree[Pa]  = (sel) ? idx_tree[C1]  : idx_tree[C0];
                                                  -1-  
                                                  ==>  
                                                  ==>  

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T8,T31,T25

156                  assign data_tree[Pa] = (sel) ? data_tree[C1] : data_tree[C0];
                                                  -1-  
                                                  ==>  
                                                  ==>  

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T8,T31,T25

155                  assign idx_tree[Pa]  = (sel) ? idx_tree[C1]  : idx_tree[C0];
                                                  -1-  
                                                  ==>  
                                                  ==>  

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T8,T31,T25

156                  assign data_tree[Pa] = (sel) ? data_tree[C1] : data_tree[C0];
                                                  -1-  
                                                  ==>  
                                                  ==>  

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T8,T31,T25

128                    assign prio_mask_d[offset] = (|req_i) ?
                                                             -1-  
                                                             ==>  
                                                             ==>  

Branches:

-1-	Status	Tests
1	Covered	T8,T31,T25
0	Covered	T1,T2,T3

128                    assign prio_mask_d[offset] = (|req_i) ?
                                                             -1-  
                                                             ==>  
                                                             ==>  

Branches:

-1-	Status	Tests
1	Covered	T8,T31,T25
0	Covered	T1,T2,T3

128                    assign prio_mask_d[offset] = (|req_i) ?
                                                             -1-  
                                                             ==>  
                                                             ==>  

Branches:

-1-	Status	Tests
1	Covered	T8,T31,T25
0	Covered	T1,T2,T3

128                    assign prio_mask_d[offset] = (|req_i) ?
                                                             -1-  
                                                             ==>  
                                                             ==>  

Branches:

-1-	Status	Tests
1	Covered	T8,T31,T25
0	Covered	T1,T2,T3

191              if (!rst_ni) begin
                 -1-  
192                prio_mask_q <= '0;
                   ==>
193              end else begin
194                prio_mask_q <= prio_mask_d;
                   ==>

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_rd.u_valid_random

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	15	15	100.00	12	80.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	15	15	100.00	12	80.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	391176692	390364170	0	0
CheckNGreaterZero_A	1051	1051	0	0
GntImpliesReady_A	391176692	2287241	0	0
GntImpliesValid_A	391176692	2287241	0	0
GrantKnown_A	391176692	390364170	0	0
IdxKnown_A	391176692	390364170	0	0
IndexIsCorrect_A	391176692	2287241	0	0
LockArbDecision_A	391176692	0	0	0
NoReadyValidNoGrant_A	391176692	277642324	0	0
ReadyAndValidImplyGrant_A	391176692	2287241	0	0
ReqAndReadyImplyGrant_A	391176692	2287241	0	0
ReqImpliesValid_A	391176692	108119882	0	0
ReqStaysHighUntilGranted0_M	391176692	0	0	0
RoundRobin_A	391176692	0	0	1047
ValidKnown_A	391176692	390364170	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	391176692	390364170	0	0
T1	2070	1970	0	0
T2	3480	3381	0	0
T3	1887	1822	0	0
T4	4370	3912	0	0
T5	677	579	0	0
T8	45213	45151	0	0
T9	1406	1318	0	0
T10	2124	2046	0	0
T16	1541	1471	0	0
T17	1625	1542	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1051	1051	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	391176692	2287241	0	0
T6	1297	0	0	0
T8	45213	211	0	0
T9	1406	0	0	0
T10	2124	0	0	0
T11	493	0	0	0
T12	0	30	0	0
T16	1541	0	0	0
T17	1625	0	0	0
T22	0	24	0	0
T25	5313	18	0	0
T30	0	269	0	0
T31	1776	2	0	0
T32	0	510	0	0
T48	0	122	0	0
T61	0	2	0	0
T62	1074	0	0	0
T67	0	460	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	391176692	2287241	0	0
T6	1297	0	0	0
T8	45213	211	0	0
T9	1406	0	0	0
T10	2124	0	0	0
T11	493	0	0	0
T12	0	30	0	0
T16	1541	0	0	0
T17	1625	0	0	0
T22	0	24	0	0
T25	5313	18	0	0
T30	0	269	0	0
T31	1776	2	0	0
T32	0	510	0	0
T48	0	122	0	0
T61	0	2	0	0
T62	1074	0	0	0
T67	0	460	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	391176692	390364170	0	0
T1	2070	1970	0	0
T2	3480	3381	0	0
T3	1887	1822	0	0
T4	4370	3912	0	0
T5	677	579	0	0
T8	45213	45151	0	0
T9	1406	1318	0	0
T10	2124	2046	0	0
T16	1541	1471	0	0
T17	1625	1542	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	391176692	390364170	0	0
T1	2070	1970	0	0
T2	3480	3381	0	0
T3	1887	1822	0	0
T4	4370	3912	0	0
T5	677	579	0	0
T8	45213	45151	0	0
T9	1406	1318	0	0
T10	2124	2046	0	0
T16	1541	1471	0	0
T17	1625	1542	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	391176692	2287241	0	0
T6	1297	0	0	0
T8	45213	211	0	0
T9	1406	0	0	0
T10	2124	0	0	0
T11	493	0	0	0
T12	0	30	0	0
T16	1541	0	0	0
T17	1625	0	0	0
T22	0	24	0	0
T25	5313	18	0	0
T30	0	269	0	0
T31	1776	2	0	0
T32	0	510	0	0
T48	0	122	0	0
T61	0	2	0	0
T62	1074	0	0	0
T67	0	460	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	391176692	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	391176692	277642324	0	0
T1	2070	1970	0	0
T2	3480	3381	0	0
T3	1887	1822	0	0
T4	4370	3912	0	0
T5	677	579	0	0
T8	45213	840	0	0
T9	1406	1318	0	0
T10	2124	2046	0	0
T16	1541	1471	0	0
T17	1625	1542	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	391176692	2287241	0	0
T6	1297	0	0	0
T8	45213	211	0	0
T9	1406	0	0	0
T10	2124	0	0	0
T11	493	0	0	0
T12	0	30	0	0
T16	1541	0	0	0
T17	1625	0	0	0
T22	0	24	0	0
T25	5313	18	0	0
T30	0	269	0	0
T31	1776	2	0	0
T32	0	510	0	0
T48	0	122	0	0
T61	0	2	0	0
T62	1074	0	0	0
T67	0	460	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	391176692	2287241	0	0
T6	1297	0	0	0
T8	45213	211	0	0
T9	1406	0	0	0
T10	2124	0	0	0
T11	493	0	0	0
T12	0	30	0	0
T16	1541	0	0	0
T17	1625	0	0	0
T22	0	24	0	0
T25	5313	18	0	0
T30	0	269	0	0
T31	1776	2	0	0
T32	0	510	0	0
T48	0	122	0	0
T61	0	2	0	0
T62	1074	0	0	0
T67	0	460	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	391176692	108119882	0	0
T6	1297	0	0	0
T8	45213	44307	0	0
T9	1406	0	0	0
T10	2124	0	0	0
T11	493	3	0	0
T12	0	41845	0	0
T16	1541	0	0	0
T17	1625	0	0	0
T22	0	440	0	0
T25	5313	4209	0	0
T30	0	40355	0	0
T31	1776	603	0	0
T48	0	11834	0	0
T61	0	175	0	0
T62	1074	0	0	0
T67	0	41852	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	391176692	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	391176692	0	0	1047

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	391176692	390364170	0	0
T1	2070	1970	0	0
T2	3480	3381	0	0
T3	1887	1822	0	0
T4	4370	3912	0	0
T5	677	579	0	0
T8	45213	45151	0	0
T9	1406	1318	0	0
T10	2124	2046	0	0
T16	1541	1471	0	0
T17	1625	1542	0	0

Line Coverage for Instance : tb.dut.u_eflash.u_scramble.u_prim_arbiter_tree_op.gen_input_bufs[0].gen_rr_arbiter.u_arb

	Line No.	Total	Covered	Percent
TOTAL		25	25	100.00
CONT_ASSIGN	62	0	0
CONT_ASSIGN	112	1	1	100.00
CONT_ASSIGN	112	1	1	100.00
CONT_ASSIGN	118	1	1	100.00
CONT_ASSIGN	118	1	1	100.00
CONT_ASSIGN	122	1	1	100.00
CONT_ASSIGN	122	1	1	100.00
CONT_ASSIGN	126	1	1	100.00
CONT_ASSIGN	126	1	1	100.00
CONT_ASSIGN	128	1	1	100.00
CONT_ASSIGN	128	1	1	100.00
CONT_ASSIGN	148	1	1	100.00
CONT_ASSIGN	150	1	1	100.00
CONT_ASSIGN	151	1	1	100.00
CONT_ASSIGN	155	1	1	100.00
CONT_ASSIGN	156	1	1	100.00
CONT_ASSIGN	160	1	1	100.00
CONT_ASSIGN	161	1	1	100.00
CONT_ASSIGN	163	0	0
CONT_ASSIGN	164	1	1	100.00
CONT_ASSIGN	171	1	1	100.00
CONT_ASSIGN	180	1	1	100.00
CONT_ASSIGN	182	1	1	100.00
CONT_ASSIGN	183	1	1	100.00
ALWAYS	191	3	3	100.00

61                        logic unused_req_chk;
62         unreachable    assign unused_req_chk = req_chk_i;
63                      
64                        `ASSERT_INIT(CheckNGreaterZero_A, N > 0)
65                      
66                        // this case is basically just a bypass
67                        if (N == 1) begin : gen_degenerate_case
68                      
69                          assign valid_o  = req_i[0];
70                          assign data_o   = data_i[0];
71                          assign gnt_o[0] = valid_o & ready_i;
72                          assign idx_o    = '0;
73                      
74                        end else begin : gen_normal_case
75                      
76                          // align to powers of 2 for simplicity
77                          // a full binary tree with N levels has 2**N + 2**N-1 nodes
78                          logic [2**(IdxW+1)-2:0]           req_tree;
79                          logic [2**(IdxW+1)-2:0]           prio_tree;
80                          logic [2**(IdxW+1)-2:0]           sel_tree;
81                          logic [2**(IdxW+1)-2:0]           mask_tree;
82                          logic [2**(IdxW+1)-2:0][IdxW-1:0] idx_tree;
83                          logic [2**(IdxW+1)-2:0][DW-1:0]   data_tree;
84                          logic [N-1:0]                     prio_mask_d, prio_mask_q;
85                      
86                          for (genvar level = 0; level < IdxW+1; level++) begin : gen_tree
87                            //
88                            // level+1   C0   C1   <- "Base1" points to the first node on "level+1",
89                            //            \  /         these nodes are the children of the nodes one level below
90                            // level       Pa      <- "Base0", points to the first node on "level",
91                            //                         these nodes are the parents of the nodes one level above
92                            //
93                            // hence we have the following indices for the Pa, C0, C1 nodes:
94                            // Pa = 2**level     - 1 + offset       = Base0 + offset
95                            // C0 = 2**(level+1) - 1 + 2*offset     = Base1 + 2*offset
96                            // C1 = 2**(level+1) - 1 + 2*offset + 1 = Base1 + 2*offset + 1
97                            //
98                            localparam int Base0 = (2**level)-1;
99                            localparam int Base1 = (2**(level+1))-1;
100                     
101                           for (genvar offset = 0; offset < 2**level; offset++) begin : gen_level
102                             localparam int Pa = Base0 + offset;
103                             localparam int C0 = Base1 + 2*offset;
104                             localparam int C1 = Base1 + 2*offset + 1;
105                     
106                             // this assigns the gated interrupt source signals, their
107                             // corresponding IDs and priorities to the tree leafs
108                             if (level == IdxW) begin : gen_leafs
109                               if (offset < N) begin : gen_assign
110                                 // forward path (requests and data)
111                                 // all requests inputs are assigned to the request tree
112        2/2                      assign req_tree[Pa]      = req_i[offset];
           Tests:       T1 T2 T3  | T1 T2 T3 
113                                 // we basically split the incoming request vector into two halves with the following
114                                 // priority assignment. the prio_mask_q register contains a prefix sum that has been
115                                 // computed using the last winning index, and hence masks out all requests at offsets
116                                 // lower or equal the previously granted index. hence, all higher indices are considered
117                                 // first in the arbitration tree nodes below, before considering the lower indices.
118        2/2                      assign prio_tree[Pa]     = req_i[offset] & prio_mask_q[offset];
           Tests:       T1 T2 T3  | T1 T2 T3 
119                                 // input for the index muxes (used to compute the winner index)
120                                 assign idx_tree[Pa]      = offset;
121                                 // input for the data muxes
122        2/2                      assign data_tree[Pa]     = data_i[offset];
           Tests:       T1 T2 T3  | T1 T2 T3 
123                     
124                                 // backward path (grants and prefix sum)
125                                 // grant if selected, ready and request asserted
126        2/2                      assign gnt_o[offset]       = req_i[offset] & sel_tree[Pa] & ready_i;
           Tests:       T1 T2 T3  | T1 T2 T3 
127                                 // only update mask if there is a valid request
128        2/2                      assign prio_mask_d[offset] = (|req_i) ?
           Tests:       T1 T2 T3  | T1 T2 T3 
129                                                              mask_tree[Pa] | sel_tree[Pa] & ~ready_i :
130                                                              prio_mask_q[offset];
131                               end else begin : gen_tie_off
132                                 // forward path
133                                 assign req_tree[Pa]  = '0;
134                                 assign prio_tree[Pa] = '0;
135                                 assign idx_tree[Pa]  = '0;
136                                 assign data_tree[Pa] = '0;
137                                 logic unused_sigs;
138                                 assign unused_sigs = ^{mask_tree[Pa],
139                                                        sel_tree[Pa]};
140                               end
141                             // this creates the node assignments
142                             end else begin : gen_nodes
143                               // local helper variable
144                               logic sel;
145                     
146                               // forward path (requests and data)
147                               // each node looks at its two children, and selects the one with higher priority
148        1/1                    assign sel = ~req_tree[C0] | ~prio_tree[C0] & prio_tree[C1];
           Tests:       T1 T2 T3 
149                               // propagate requests
150        1/1                    assign req_tree[Pa]  = req_tree[C0] | req_tree[C1];
           Tests:       T1 T2 T3 
151        1/1                    assign prio_tree[Pa] = prio_tree[C1] | prio_tree[C0];
           Tests:       T1 T2 T3 
152                               // data and index muxes
153                               // Note: these ternaries have triggered a synthesis bug in Vivado versions older
154                               // than 2020.2. If the problem resurfaces again, have a look at issue #1408.
155        1/1                    assign idx_tree[Pa]  = (sel) ? idx_tree[C1]  : idx_tree[C0];
           Tests:       T1 T2 T3 
156        1/1                    assign data_tree[Pa] = (sel) ? data_tree[C1] : data_tree[C0];
           Tests:       T1 T2 T3 
157                     
158                               // backward path (grants and prefix sum)
159                               // this propagates the selction index back and computes a hot one mask
160        1/1                    assign sel_tree[C0] = sel_tree[Pa] & ~sel;
           Tests:       T1 T2 T3 
161        1/1                    assign sel_tree[C1] = sel_tree[Pa] &  sel;
           Tests:       T1 T2 T3 
162                               // this performs a prefix sum for masking the input requests in the next cycle
163        unreachable            assign mask_tree[C0] = mask_tree[Pa];
164        1/1                    assign mask_tree[C1] = mask_tree[Pa] | sel_tree[C0];
           Tests:       T1 T2 T3 
165                             end
166                           end : gen_level
167                         end : gen_tree
168                     
169                         // the results can be found at the tree root
170                         if (EnDataPort) begin : gen_data_port
171        1/1                assign data_o      = data_tree[0];
           Tests:       T1 T2 T3 
172                         end else begin : gen_no_dataport
173                           logic [DW-1:0] unused_data;
174                           assign unused_data = data_tree[0];
175                           assign data_o = '1;
176                         end
177                     
178                         // This index is unused.
179                         logic unused_prio_tree;
180        1/1              assign unused_prio_tree = prio_tree[0];
           Tests:       T1 T2 T3 
181                     
182        1/1              assign idx_o       = idx_tree[0];
           Tests:       T1 T2 T3 
183        1/1              assign valid_o     = req_tree[0];
           Tests:       T1 T2 T3 
184                     
185                         // the select tree computes a hot one signal that indicates which request is currently selected
186                         assign sel_tree[0] = 1'b1;
187                         // the mask tree is basically a prefix sum of the hot one select signal computed above
188                         assign mask_tree[0] = 1'b0;
189                     
190                         always_ff @(posedge clk_i or negedge rst_ni) begin : p_mask_reg
191        1/1                if (!rst_ni) begin
           Tests:       T1 T2 T3 
192        1/1                  prio_mask_q <= '0;
           Tests:       T1 T2 T3 
193                           end else begin
194        1/1                  prio_mask_q <= prio_mask_d;
           Tests:       T1 T2 T3 

---

Cond Coverage for Instance : tb.dut.u_eflash.u_scramble.u_prim_arbiter_tree_op.gen_input_bufs[0].gen_rr_arbiter.u_arb

	Total	Covered	Percent
Conditions	51	45	88.24
Logical	51	45	88.24
Non-Logical	0	0
Event	0	0

 LINE       118
 EXPRESSION (req_i[0] & gen_normal_case.prio_mask_q[0])
             ----1---   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       118
 EXPRESSION (req_i[1] & gen_normal_case.prio_mask_q[1])
             ----1---   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T6,T25,T22
1	1	Covered	T4,T6,T31

 LINE       126
 EXPRESSION (req_i[0] & gen_normal_case.sel_tree[gen_normal_case.gen_tree[1].gen_level[0].Pa] & ready_i)
             ----1---   ----------------------------------2----------------------------------   ---3---

-1-	-2-	-3-	Status	Tests
0	1	1	Not Covered
1	0	1	Not Covered
1	1	0	Covered	T1,T2,T3
1	1	1	Covered	T1,T2,T3

 LINE       126
 EXPRESSION (req_i[1] & gen_normal_case.sel_tree[gen_normal_case.gen_tree[1].gen_level[1].Pa] & ready_i)
             ----1---   ----------------------------------2----------------------------------   ---3---

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T12
1	0	1	Not Covered
1	1	0	Covered	T4,T6,T31
1	1	1	Covered	T4,T6,T31

 LINE       128
 EXPRESSION 
 Number  Term
      1  ((|req_i)) ? (gen_normal_case.mask_tree[gen_normal_case.gen_tree[1].gen_level[0].Pa] | (gen_normal_case.sel_tree[gen_normal_case.gen_tree[1].gen_level[0].Pa] & ((~ready_i)))) : gen_normal_case.prio_mask_q[0])

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       128
 SUB-EXPRESSION 
 Number  Term
      1  gen_normal_case.mask_tree[gen_normal_case.gen_tree[1].gen_level[0].Pa] | 
      2  (gen_normal_case.sel_tree[gen_normal_case.gen_tree[1].gen_level[0].Pa] & ((~ready_i))))

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Unreachable

 LINE       128
 SUB-EXPRESSION (gen_normal_case.sel_tree[gen_normal_case.gen_tree[1].gen_level[0].Pa] & ((~ready_i)))
                 ----------------------------------1----------------------------------   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T4,T6,T31
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       128
 EXPRESSION 
 Number  Term
      1  ((|req_i)) ? (gen_normal_case.mask_tree[gen_normal_case.gen_tree[1].gen_level[1].Pa] | (gen_normal_case.sel_tree[gen_normal_case.gen_tree[1].gen_level[1].Pa] & ((~ready_i)))) : gen_normal_case.prio_mask_q[1])

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       128
 SUB-EXPRESSION 
 Number  Term
      1  gen_normal_case.mask_tree[gen_normal_case.gen_tree[1].gen_level[1].Pa] | 
      2  (gen_normal_case.sel_tree[gen_normal_case.gen_tree[1].gen_level[1].Pa] & ((~ready_i))))

-1-	-2-	Status	Tests
0	0	Covered	T4,T6,T31
0	1	Covered	T4,T6,T31
1	0	Covered	T1,T2,T3

 LINE       128
 SUB-EXPRESSION (gen_normal_case.sel_tree[gen_normal_case.gen_tree[1].gen_level[1].Pa] & ((~ready_i)))
                 ----------------------------------1----------------------------------   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T4,T6,T31
1	1	Covered	T4,T6,T31

 LINE       148
 EXPRESSION 
 Number  Term
      1  ((~gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])) | 
      2  (((~gen_normal_case.prio_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])) & gen_normal_case.prio_tree[gen_normal_case.gen_tree[0].gen_level[0].C1]))

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Not Covered
1	0	Covered	T1,T2,T3

 LINE       148
 SUB-EXPRESSION 
 Number  Term
      1  ((~gen_normal_case.prio_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])) & 
      2  gen_normal_case.prio_tree[gen_normal_case.gen_tree[0].gen_level[0].C1])

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T1,T2,T3
1	1	Covered	T4,T6,T31

 LINE       150
 EXPRESSION (gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C0] | gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C1])
             ----------------------------------1----------------------------------   ----------------------------------2----------------------------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T4,T6,T31
1	0	Covered	T1,T2,T3

 LINE       151
 EXPRESSION (gen_normal_case.prio_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] | gen_normal_case.prio_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])
             -----------------------------------1----------------------------------   -----------------------------------2----------------------------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T4,T6,T31

 LINE       155
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       156
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       160
 EXPRESSION (gen_normal_case.sel_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & ((~gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)))
             ----------------------------------1----------------------------------   -----------------------------2-----------------------------

-1-	-2-	Status	Tests
0	1	Unreachable
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       161
 EXPRESSION (gen_normal_case.sel_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)
             ----------------------------------1----------------------------------   ---------------------------2--------------------------

-1-	-2-	Status	Tests
0	1	Unreachable
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       164
 EXPRESSION (gen_normal_case.mask_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] | gen_normal_case.sel_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])
             -----------------------------------1----------------------------------   ----------------------------------2----------------------------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Unreachable

---

Branch Coverage for Instance : tb.dut.u_eflash.u_scramble.u_prim_arbiter_tree_op.gen_input_bufs[0].gen_rr_arbiter.u_arb

	Line No.	Total	Covered	Percent
Branches		10	10	100.00
TERNARY	155	2	2	100.00
TERNARY	156	2	2	100.00
TERNARY	128	2	2	100.00
TERNARY	128	2	2	100.00
IF	191	2	2	100.00

155                  assign idx_tree[Pa]  = (sel) ? idx_tree[C1]  : idx_tree[C0];
                                                  -1-  
                                                  ==>  
                                                  ==>  

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

156                  assign data_tree[Pa] = (sel) ? data_tree[C1] : data_tree[C0];
                                                  -1-  
                                                  ==>  
                                                  ==>  

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

128                    assign prio_mask_d[offset] = (|req_i) ?
                                                             -1-  
                                                             ==>  
                                                             ==>  

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

128                    assign prio_mask_d[offset] = (|req_i) ?
                                                             -1-  
                                                             ==>  
                                                             ==>  

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

191              if (!rst_ni) begin
                 -1-  
192                prio_mask_q <= '0;
                   ==>
193              end else begin
194                prio_mask_q <= prio_mask_d;
                   ==>

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_eflash.u_scramble.u_prim_arbiter_tree_op.gen_input_bufs[0].gen_rr_arbiter.u_arb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	15	93.75
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	15	93.75

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	391176692	390364170	0	0
CheckNGreaterZero_A	1051	1051	0	0
GntImpliesReady_A	391176692	15204174	0	0
GntImpliesValid_A	391176692	15204174	0	0
GrantKnown_A	391176692	390364170	0	0
IdxKnown_A	391176692	390364170	0	0
IndexIsCorrect_A	391176692	15204174	0	0
LockArbDecision_A	391134227	15204091	0	0
NoReadyValidNoGrant_A	391176692	359955770	0	0
ReadyAndValidImplyGrant_A	391176692	15204174	0	0
ReqAndReadyImplyGrant_A	391176692	15204174	0	0
ReqImpliesValid_A	391176692	30408355	0	0
ReqStaysHighUntilGranted0_M	391134227	15204091	0	0
RoundRobin_A	391176692	0	0	1047
ValidKnown_A	391176692	390364170	0	0
gen_data_port_assertion.DataFlow_A	391176692	15204174	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	391176692	390364170	0	0
T1	2070	1970	0	0
T2	3480	3381	0	0
T3	1887	1822	0	0
T4	4370	3912	0	0
T5	677	579	0	0
T8	45213	45151	0	0
T9	1406	1318	0	0
T10	2124	2046	0	0
T16	1541	1471	0	0
T17	1625	1542	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1051	1051	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	391176692	15204174	0	0
T1	2070	32	0	0
T2	3480	32	0	0
T3	1887	105	0	0
T4	4370	198	0	0
T5	677	37	0	0
T8	45213	32	0	0
T9	1406	32	0	0
T10	2124	32	0	0
T16	1541	32	0	0
T17	1625	32	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	391176692	15204174	0	0
T1	2070	32	0	0
T2	3480	32	0	0
T3	1887	105	0	0
T4	4370	198	0	0
T5	677	37	0	0
T8	45213	32	0	0
T9	1406	32	0	0
T10	2124	32	0	0
T16	1541	32	0	0
T17	1625	32	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	391176692	390364170	0	0
T1	2070	1970	0	0
T2	3480	3381	0	0
T3	1887	1822	0	0
T4	4370	3912	0	0
T5	677	579	0	0
T8	45213	45151	0	0
T9	1406	1318	0	0
T10	2124	2046	0	0
T16	1541	1471	0	0
T17	1625	1542	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	391176692	390364170	0	0
T1	2070	1970	0	0
T2	3480	3381	0	0
T3	1887	1822	0	0
T4	4370	3912	0	0
T5	677	579	0	0
T8	45213	45151	0	0
T9	1406	1318	0	0
T10	2124	2046	0	0
T16	1541	1471	0	0
T17	1625	1542	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	391176692	15204174	0	0
T1	2070	32	0	0
T2	3480	32	0	0
T3	1887	105	0	0
T4	4370	198	0	0
T5	677	37	0	0
T8	45213	32	0	0
T9	1406	32	0	0
T10	2124	32	0	0
T16	1541	32	0	0
T17	1625	32	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	391134227	15204091	0	0
T1	2070	32	0	0
T2	3480	32	0	0
T3	1887	105	0	0
T4	4370	198	0	0
T5	677	37	0	0
T8	45213	32	0	0
T9	1406	32	0	0
T10	2124	32	0	0
T16	1541	32	0	0
T17	1625	32	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	391176692	359955770	0	0
T1	2070	1906	0	0
T2	3480	3317	0	0
T3	1887	1612	0	0
T4	4370	3516	0	0
T5	677	505	0	0
T8	45213	45087	0	0
T9	1406	1254	0	0
T10	2124	1982	0	0
T16	1541	1407	0	0
T17	1625	1478	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	391176692	15204174	0	0
T1	2070	32	0	0
T2	3480	32	0	0
T3	1887	105	0	0
T4	4370	198	0	0
T5	677	37	0	0
T8	45213	32	0	0
T9	1406	32	0	0
T10	2124	32	0	0
T16	1541	32	0	0
T17	1625	32	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	391176692	15204174	0	0
T1	2070	32	0	0
T2	3480	32	0	0
T3	1887	105	0	0
T4	4370	198	0	0
T5	677	37	0	0
T8	45213	32	0	0
T9	1406	32	0	0
T10	2124	32	0	0
T16	1541	32	0	0
T17	1625	32	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	391176692	30408355	0	0
T1	2070	64	0	0
T2	3480	64	0	0
T3	1887	210	0	0
T4	4370	396	0	0
T5	677	74	0	0
T8	45213	64	0	0
T9	1406	64	0	0
T10	2124	64	0	0
T16	1541	64	0	0
T17	1625	64	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	391134227	15204091	0	0
T1	2070	32	0	0
T2	3480	32	0	0
T3	1887	105	0	0
T4	4370	198	0	0
T5	677	37	0	0
T8	45213	32	0	0
T9	1406	32	0	0
T10	2124	32	0	0
T16	1541	32	0	0
T17	1625	32	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	391176692	0	0	1047

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	391176692	390364170	0	0
T1	2070	1970	0	0
T2	3480	3381	0	0
T3	1887	1822	0	0
T4	4370	3912	0	0
T5	677	579	0	0
T8	45213	45151	0	0
T9	1406	1318	0	0
T10	2124	2046	0	0
T16	1541	1471	0	0
T17	1625	1542	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	391176692	15204174	0	0
T1	2070	32	0	0
T2	3480	32	0	0
T3	1887	105	0	0
T4	4370	198	0	0
T5	677	37	0	0
T8	45213	32	0	0
T9	1406	32	0	0
T10	2124	32	0	0
T16	1541	32	0	0
T17	1625	32	0	0

Line Coverage for Instance : tb.dut.u_eflash.u_scramble.u_prim_arbiter_tree_op.gen_input_bufs[1].gen_rr_arbiter.u_arb

	Line No.	Total	Covered	Percent
TOTAL		25	25	100.00
CONT_ASSIGN	62	0	0
CONT_ASSIGN	112	1	1	100.00
CONT_ASSIGN	112	1	1	100.00
CONT_ASSIGN	118	1	1	100.00
CONT_ASSIGN	118	1	1	100.00
CONT_ASSIGN	122	1	1	100.00
CONT_ASSIGN	122	1	1	100.00
CONT_ASSIGN	126	1	1	100.00
CONT_ASSIGN	126	1	1	100.00
CONT_ASSIGN	128	1	1	100.00
CONT_ASSIGN	128	1	1	100.00
CONT_ASSIGN	148	1	1	100.00
CONT_ASSIGN	150	1	1	100.00
CONT_ASSIGN	151	1	1	100.00
CONT_ASSIGN	155	1	1	100.00
CONT_ASSIGN	156	1	1	100.00
CONT_ASSIGN	160	1	1	100.00
CONT_ASSIGN	161	1	1	100.00
CONT_ASSIGN	163	0	0
CONT_ASSIGN	164	1	1	100.00
CONT_ASSIGN	171	1	1	100.00
CONT_ASSIGN	180	1	1	100.00
CONT_ASSIGN	182	1	1	100.00
CONT_ASSIGN	183	1	1	100.00
ALWAYS	191	3	3	100.00

61                        logic unused_req_chk;
62         unreachable    assign unused_req_chk = req_chk_i;
63                      
64                        `ASSERT_INIT(CheckNGreaterZero_A, N > 0)
65                      
66                        // this case is basically just a bypass
67                        if (N == 1) begin : gen_degenerate_case
68                      
69                          assign valid_o  = req_i[0];
70                          assign data_o   = data_i[0];
71                          assign gnt_o[0] = valid_o & ready_i;
72                          assign idx_o    = '0;
73                      
74                        end else begin : gen_normal_case
75                      
76                          // align to powers of 2 for simplicity
77                          // a full binary tree with N levels has 2**N + 2**N-1 nodes
78                          logic [2**(IdxW+1)-2:0]           req_tree;
79                          logic [2**(IdxW+1)-2:0]           prio_tree;
80                          logic [2**(IdxW+1)-2:0]           sel_tree;
81                          logic [2**(IdxW+1)-2:0]           mask_tree;
82                          logic [2**(IdxW+1)-2:0][IdxW-1:0] idx_tree;
83                          logic [2**(IdxW+1)-2:0][DW-1:0]   data_tree;
84                          logic [N-1:0]                     prio_mask_d, prio_mask_q;
85                      
86                          for (genvar level = 0; level < IdxW+1; level++) begin : gen_tree
87                            //
88                            // level+1   C0   C1   <- "Base1" points to the first node on "level+1",
89                            //            \  /         these nodes are the children of the nodes one level below
90                            // level       Pa      <- "Base0", points to the first node on "level",
91                            //                         these nodes are the parents of the nodes one level above
92                            //
93                            // hence we have the following indices for the Pa, C0, C1 nodes:
94                            // Pa = 2**level     - 1 + offset       = Base0 + offset
95                            // C0 = 2**(level+1) - 1 + 2*offset     = Base1 + 2*offset
96                            // C1 = 2**(level+1) - 1 + 2*offset + 1 = Base1 + 2*offset + 1
97                            //
98                            localparam int Base0 = (2**level)-1;
99                            localparam int Base1 = (2**(level+1))-1;
100                     
101                           for (genvar offset = 0; offset < 2**level; offset++) begin : gen_level
102                             localparam int Pa = Base0 + offset;
103                             localparam int C0 = Base1 + 2*offset;
104                             localparam int C1 = Base1 + 2*offset + 1;
105                     
106                             // this assigns the gated interrupt source signals, their
107                             // corresponding IDs and priorities to the tree leafs
108                             if (level == IdxW) begin : gen_leafs
109                               if (offset < N) begin : gen_assign
110                                 // forward path (requests and data)
111                                 // all requests inputs are assigned to the request tree
112        2/2                      assign req_tree[Pa]      = req_i[offset];
           Tests:       T1 T2 T3  | T1 T2 T3 
113                                 // we basically split the incoming request vector into two halves with the following
114                                 // priority assignment. the prio_mask_q register contains a prefix sum that has been
115                                 // computed using the last winning index, and hence masks out all requests at offsets
116                                 // lower or equal the previously granted index. hence, all higher indices are considered
117                                 // first in the arbitration tree nodes below, before considering the lower indices.
118        2/2                      assign prio_tree[Pa]     = req_i[offset] & prio_mask_q[offset];
           Tests:       T1 T2 T3  | T1 T2 T3 
119                                 // input for the index muxes (used to compute the winner index)
120                                 assign idx_tree[Pa]      = offset;
121                                 // input for the data muxes
122        2/2                      assign data_tree[Pa]     = data_i[offset];
           Tests:       T1 T2 T3  | T1 T2 T3 
123                     
124                                 // backward path (grants and prefix sum)
125                                 // grant if selected, ready and request asserted
126        2/2                      assign gnt_o[offset]       = req_i[offset] & sel_tree[Pa] & ready_i;
           Tests:       T1 T2 T3  | T1 T2 T3 
127                                 // only update mask if there is a valid request
128        2/2                      assign prio_mask_d[offset] = (|req_i) ?
           Tests:       T1 T2 T3  | T1 T2 T3 
129                                                              mask_tree[Pa] | sel_tree[Pa] & ~ready_i :
130                                                              prio_mask_q[offset];
131                               end else begin : gen_tie_off
132                                 // forward path
133                                 assign req_tree[Pa]  = '0;
134                                 assign prio_tree[Pa] = '0;
135                                 assign idx_tree[Pa]  = '0;
136                                 assign data_tree[Pa] = '0;
137                                 logic unused_sigs;
138                                 assign unused_sigs = ^{mask_tree[Pa],
139                                                        sel_tree[Pa]};
140                               end
141                             // this creates the node assignments
142                             end else begin : gen_nodes
143                               // local helper variable
144                               logic sel;
145                     
146                               // forward path (requests and data)
147                               // each node looks at its two children, and selects the one with higher priority
148        1/1                    assign sel = ~req_tree[C0] | ~prio_tree[C0] & prio_tree[C1];
           Tests:       T1 T2 T3 
149                               // propagate requests
150        1/1                    assign req_tree[Pa]  = req_tree[C0] | req_tree[C1];
           Tests:       T1 T2 T3 
151        1/1                    assign prio_tree[Pa] = prio_tree[C1] | prio_tree[C0];
           Tests:       T1 T2 T3 
152                               // data and index muxes
153                               // Note: these ternaries have triggered a synthesis bug in Vivado versions older
154                               // than 2020.2. If the problem resurfaces again, have a look at issue #1408.
155        1/1                    assign idx_tree[Pa]  = (sel) ? idx_tree[C1]  : idx_tree[C0];
           Tests:       T1 T2 T3 
156        1/1                    assign data_tree[Pa] = (sel) ? data_tree[C1] : data_tree[C0];
           Tests:       T1 T2 T3 
157                     
158                               // backward path (grants and prefix sum)
159                               // this propagates the selction index back and computes a hot one mask
160        1/1                    assign sel_tree[C0] = sel_tree[Pa] & ~sel;
           Tests:       T1 T2 T3 
161        1/1                    assign sel_tree[C1] = sel_tree[Pa] &  sel;
           Tests:       T1 T2 T3 
162                               // this performs a prefix sum for masking the input requests in the next cycle
163        unreachable            assign mask_tree[C0] = mask_tree[Pa];
164        1/1                    assign mask_tree[C1] = mask_tree[Pa] | sel_tree[C0];
           Tests:       T1 T2 T3 
165                             end
166                           end : gen_level
167                         end : gen_tree
168                     
169                         // the results can be found at the tree root
170                         if (EnDataPort) begin : gen_data_port
171        1/1                assign data_o      = data_tree[0];
           Tests:       T1 T2 T3 
172                         end else begin : gen_no_dataport
173                           logic [DW-1:0] unused_data;
174                           assign unused_data = data_tree[0];
175                           assign data_o = '1;
176                         end
177                     
178                         // This index is unused.
179                         logic unused_prio_tree;
180        1/1              assign unused_prio_tree = prio_tree[0];
           Tests:       T1 T2 T3 
181                     
182        1/1              assign idx_o       = idx_tree[0];
           Tests:       T1 T2 T3 
183        1/1              assign valid_o     = req_tree[0];
           Tests:       T1 T2 T3 
184                     
185                         // the select tree computes a hot one signal that indicates which request is currently selected
186                         assign sel_tree[0] = 1'b1;
187                         // the mask tree is basically a prefix sum of the hot one select signal computed above
188                         assign mask_tree[0] = 1'b0;
189                     
190                         always_ff @(posedge clk_i or negedge rst_ni) begin : p_mask_reg
191        1/1                if (!rst_ni) begin
           Tests:       T1 T2 T3 
192        1/1                  prio_mask_q <= '0;
           Tests:       T1 T2 T3 
193                           end else begin
194        1/1                  prio_mask_q <= prio_mask_d;
           Tests:       T1 T2 T3 

---

Cond Coverage for Instance : tb.dut.u_eflash.u_scramble.u_prim_arbiter_tree_op.gen_input_bufs[1].gen_rr_arbiter.u_arb

	Total	Covered	Percent
Conditions	51	49	96.08
Logical	51	49	96.08
Non-Logical	0	0
Event	0	0

 LINE       118
 EXPRESSION (req_i[0] & gen_normal_case.prio_mask_q[0])
             ----1---   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       118
 EXPRESSION (req_i[1] & gen_normal_case.prio_mask_q[1])
             ----1---   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T6,T25,T22
1	1	Covered	T4,T6,T31

 LINE       126
 EXPRESSION (req_i[0] & gen_normal_case.sel_tree[gen_normal_case.gen_tree[1].gen_level[0].Pa] & ready_i)
             ----1---   ----------------------------------2----------------------------------   ---3---

-1-	-2-	-3-	Status	Tests
0	1	1	Not Covered
1	0	1	Covered	T12
1	1	0	Covered	T1,T2,T3
1	1	1	Covered	T1,T2,T3

 LINE       126
 EXPRESSION (req_i[1] & gen_normal_case.sel_tree[gen_normal_case.gen_tree[1].gen_level[1].Pa] & ready_i)
             ----1---   ----------------------------------2----------------------------------   ---3---

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T12
1	0	1	Covered	T12
1	1	0	Covered	T4,T6,T31
1	1	1	Covered	T4,T6,T31

 LINE       128
 EXPRESSION 
 Number  Term
      1  ((|req_i)) ? (gen_normal_case.mask_tree[gen_normal_case.gen_tree[1].gen_level[0].Pa] | (gen_normal_case.sel_tree[gen_normal_case.gen_tree[1].gen_level[0].Pa] & ((~ready_i)))) : gen_normal_case.prio_mask_q[0])

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       128
 SUB-EXPRESSION 
 Number  Term
      1  gen_normal_case.mask_tree[gen_normal_case.gen_tree[1].gen_level[0].Pa] | 
      2  (gen_normal_case.sel_tree[gen_normal_case.gen_tree[1].gen_level[0].Pa] & ((~ready_i))))

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Unreachable

 LINE       128
 SUB-EXPRESSION (gen_normal_case.sel_tree[gen_normal_case.gen_tree[1].gen_level[0].Pa] & ((~ready_i)))
                 ----------------------------------1----------------------------------   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T4,T6,T31
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       128
 EXPRESSION 
 Number  Term
      1  ((|req_i)) ? (gen_normal_case.mask_tree[gen_normal_case.gen_tree[1].gen_level[1].Pa] | (gen_normal_case.sel_tree[gen_normal_case.gen_tree[1].gen_level[1].Pa] & ((~ready_i)))) : gen_normal_case.prio_mask_q[1])

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       128
 SUB-EXPRESSION 
 Number  Term
      1  gen_normal_case.mask_tree[gen_normal_case.gen_tree[1].gen_level[1].Pa] | 
      2  (gen_normal_case.sel_tree[gen_normal_case.gen_tree[1].gen_level[1].Pa] & ((~ready_i))))

-1-	-2-	Status	Tests
0	0	Covered	T4,T6,T31
0	1	Covered	T4,T6,T31
1	0	Covered	T1,T2,T3

 LINE       128
 SUB-EXPRESSION (gen_normal_case.sel_tree[gen_normal_case.gen_tree[1].gen_level[1].Pa] & ((~ready_i)))
                 ----------------------------------1----------------------------------   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T4,T6,T31
1	1	Covered	T4,T6,T31

 LINE       148
 EXPRESSION 
 Number  Term
      1  ((~gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])) | 
      2  (((~gen_normal_case.prio_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])) & gen_normal_case.prio_tree[gen_normal_case.gen_tree[0].gen_level[0].C1]))

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T12
1	0	Covered	T1,T2,T3

 LINE       148
 SUB-EXPRESSION 
 Number  Term
      1  ((~gen_normal_case.prio_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])) & 
      2  gen_normal_case.prio_tree[gen_normal_case.gen_tree[0].gen_level[0].C1])

-1-	-2-	Status	Tests
0	1	Covered	T12
1	0	Covered	T1,T2,T3
1	1	Covered	T4,T6,T31

 LINE       150
 EXPRESSION (gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C0] | gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C1])
             ----------------------------------1----------------------------------   ----------------------------------2----------------------------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T4,T6,T31
1	0	Covered	T1,T2,T3

 LINE       151
 EXPRESSION (gen_normal_case.prio_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] | gen_normal_case.prio_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])
             -----------------------------------1----------------------------------   -----------------------------------2----------------------------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T4,T6,T31

 LINE       155
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       156
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       160
 EXPRESSION (gen_normal_case.sel_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & ((~gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)))
             ----------------------------------1----------------------------------   -----------------------------2-----------------------------

-1-	-2-	Status	Tests
0	1	Unreachable
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       161
 EXPRESSION (gen_normal_case.sel_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)
             ----------------------------------1----------------------------------   ---------------------------2--------------------------

-1-	-2-	Status	Tests
0	1	Unreachable
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       164
 EXPRESSION (gen_normal_case.mask_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] | gen_normal_case.sel_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])
             -----------------------------------1----------------------------------   ----------------------------------2----------------------------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Unreachable

---

Branch Coverage for Instance : tb.dut.u_eflash.u_scramble.u_prim_arbiter_tree_op.gen_input_bufs[1].gen_rr_arbiter.u_arb

	Line No.	Total	Covered	Percent
Branches		10	10	100.00
TERNARY	155	2	2	100.00
TERNARY	156	2	2	100.00
TERNARY	128	2	2	100.00
TERNARY	128	2	2	100.00
IF	191	2	2	100.00

155                  assign idx_tree[Pa]  = (sel) ? idx_tree[C1]  : idx_tree[C0];
                                                  -1-  
                                                  ==>  
                                                  ==>  

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

156                  assign data_tree[Pa] = (sel) ? data_tree[C1] : data_tree[C0];
                                                  -1-  
                                                  ==>  
                                                  ==>  

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

128                    assign prio_mask_d[offset] = (|req_i) ?
                                                             -1-  
                                                             ==>  
                                                             ==>  

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

128                    assign prio_mask_d[offset] = (|req_i) ?
                                                             -1-  
                                                             ==>  
                                                             ==>  

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

191              if (!rst_ni) begin
                 -1-  
192                prio_mask_q <= '0;
                   ==>
193              end else begin
194                prio_mask_q <= prio_mask_d;
                   ==>

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_eflash.u_scramble.u_prim_arbiter_tree_op.gen_input_bufs[1].gen_rr_arbiter.u_arb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	15	93.75
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	15	93.75

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	391176692	390364170	0	0
CheckNGreaterZero_A	1051	1051	0	0
GntImpliesReady_A	391176692	15204218	0	0
GntImpliesValid_A	391176692	15204218	0	0
GrantKnown_A	391176692	390364170	0	0
IdxKnown_A	391176692	390364170	0	0
IndexIsCorrect_A	391176692	15204218	0	0
LockArbDecision_A	391134227	15204091	0	0
NoReadyValidNoGrant_A	391176692	359955725	0	0
ReadyAndValidImplyGrant_A	391176692	15204218	0	0
ReqAndReadyImplyGrant_A	391176692	15204218	0	0
ReqImpliesValid_A	391176692	30408444	0	0
ReqStaysHighUntilGranted0_M	391134227	15204091	0	0
RoundRobin_A	391176692	0	0	1047
ValidKnown_A	391176692	390364170	0	0
gen_data_port_assertion.DataFlow_A	391176692	15204218	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	391176692	390364170	0	0
T1	2070	1970	0	0
T2	3480	3381	0	0
T3	1887	1822	0	0
T4	4370	3912	0	0
T5	677	579	0	0
T8	45213	45151	0	0
T9	1406	1318	0	0
T10	2124	2046	0	0
T16	1541	1471	0	0
T17	1625	1542	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1051	1051	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	391176692	15204218	0	0
T1	2070	32	0	0
T2	3480	32	0	0
T3	1887	105	0	0
T4	4370	198	0	0
T5	677	37	0	0
T8	45213	32	0	0
T9	1406	32	0	0
T10	2124	32	0	0
T16	1541	32	0	0
T17	1625	32	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	391176692	15204218	0	0
T1	2070	32	0	0
T2	3480	32	0	0
T3	1887	105	0	0
T4	4370	198	0	0
T5	677	37	0	0
T8	45213	32	0	0
T9	1406	32	0	0
T10	2124	32	0	0
T16	1541	32	0	0
T17	1625	32	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	391176692	390364170	0	0
T1	2070	1970	0	0
T2	3480	3381	0	0
T3	1887	1822	0	0
T4	4370	3912	0	0
T5	677	579	0	0
T8	45213	45151	0	0
T9	1406	1318	0	0
T10	2124	2046	0	0
T16	1541	1471	0	0
T17	1625	1542	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	391176692	390364170	0	0
T1	2070	1970	0	0
T2	3480	3381	0	0
T3	1887	1822	0	0
T4	4370	3912	0	0
T5	677	579	0	0
T8	45213	45151	0	0
T9	1406	1318	0	0
T10	2124	2046	0	0
T16	1541	1471	0	0
T17	1625	1542	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	391176692	15204218	0	0
T1	2070	32	0	0
T2	3480	32	0	0
T3	1887	105	0	0
T4	4370	198	0	0
T5	677	37	0	0
T8	45213	32	0	0
T9	1406	32	0	0
T10	2124	32	0	0
T16	1541	32	0	0
T17	1625	32	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	391134227	15204091	0	0
T1	2070	32	0	0
T2	3480	32	0	0
T3	1887	105	0	0
T4	4370	198	0	0
T5	677	37	0	0
T8	45213	32	0	0
T9	1406	32	0	0
T10	2124	32	0	0
T16	1541	32	0	0
T17	1625	32	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	391176692	359955725	0	0
T1	2070	1906	0	0
T2	3480	3317	0	0
T3	1887	1612	0	0
T4	4370	3516	0	0
T5	677	505	0	0
T8	45213	45087	0	0
T9	1406	1254	0	0
T10	2124	1982	0	0
T16	1541	1407	0	0
T17	1625	1478	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	391176692	15204218	0	0
T1	2070	32	0	0
T2	3480	32	0	0
T3	1887	105	0	0
T4	4370	198	0	0
T5	677	37	0	0
T8	45213	32	0	0
T9	1406	32	0	0
T10	2124	32	0	0
T16	1541	32	0	0
T17	1625	32	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	391176692	15204218	0	0
T1	2070	32	0	0
T2	3480	32	0	0
T3	1887	105	0	0
T4	4370	198	0	0
T5	677	37	0	0
T8	45213	32	0	0
T9	1406	32	0	0
T10	2124	32	0	0
T16	1541	32	0	0
T17	1625	32	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	391176692	30408444	0	0
T1	2070	64	0	0
T2	3480	64	0	0
T3	1887	210	0	0
T4	4370	396	0	0
T5	677	74	0	0
T8	45213	64	0	0
T9	1406	64	0	0
T10	2124	64	0	0
T16	1541	64	0	0
T17	1625	64	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	391134227	15204091	0	0
T1	2070	32	0	0
T2	3480	32	0	0
T3	1887	105	0	0
T4	4370	198	0	0
T5	677	37	0	0
T8	45213	32	0	0
T9	1406	32	0	0
T10	2124	32	0	0
T16	1541	32	0	0
T17	1625	32	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	391176692	0	0	1047

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	391176692	390364170	0	0
T1	2070	1970	0	0
T2	3480	3381	0	0
T3	1887	1822	0	0
T4	4370	3912	0	0
T5	677	579	0	0
T8	45213	45151	0	0
T9	1406	1318	0	0
T10	2124	2046	0	0
T16	1541	1471	0	0
T17	1625	1542	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	391176692	15204218	0	0
T1	2070	32	0	0
T2	3480	32	0	0
T3	1887	105	0	0
T4	4370	198	0	0
T5	677	37	0	0
T8	45213	32	0	0
T9	1406	32	0	0
T10	2124	32	0	0
T16	1541	32	0	0
T17	1625	32	0	0

Line Coverage for Instance : tb.dut.u_eflash.u_scramble.u_prim_arbiter_tree_calc.gen_input_bufs[1].gen_rr_arbiter.u_arb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	62	0	0
CONT_ASSIGN	112	1	1	100.00
CONT_ASSIGN	112	1	1	100.00
CONT_ASSIGN	118	1	1	100.00
CONT_ASSIGN	118	1	1	100.00
CONT_ASSIGN	122	1	1	100.00
CONT_ASSIGN	122	1	1	100.00
CONT_ASSIGN	126	0	0
CONT_ASSIGN	126	0	0
CONT_ASSIGN	128	1	1	100.00
CONT_ASSIGN	128	1	1	100.00
CONT_ASSIGN	148	1	1	100.00
CONT_ASSIGN	150	1	1	100.00
CONT_ASSIGN	151	1	1	100.00
CONT_ASSIGN	155	1	1	100.00
CONT_ASSIGN	156	1	1	100.00
CONT_ASSIGN	160	1	1	100.00
CONT_ASSIGN	161	1	1	100.00
CONT_ASSIGN	163	0	0
CONT_ASSIGN	164	1	1	100.00
CONT_ASSIGN	171	1	1	100.00
CONT_ASSIGN	180	1	1	100.00
CONT_ASSIGN	182	1	1	100.00
CONT_ASSIGN	183	1	1	100.00
ALWAYS	191	3	3	100.00

61                        logic unused_req_chk;
62         unreachable    assign unused_req_chk = req_chk_i;
63                      
64                        `ASSERT_INIT(CheckNGreaterZero_A, N > 0)
65                      
66                        // this case is basically just a bypass
67                        if (N == 1) begin : gen_degenerate_case
68                      
69                          assign valid_o  = req_i[0];
70                          assign data_o   = data_i[0];
71                          assign gnt_o[0] = valid_o & ready_i;
72                          assign idx_o    = '0;
73                      
74                        end else begin : gen_normal_case
75                      
76                          // align to powers of 2 for simplicity
77                          // a full binary tree with N levels has 2**N + 2**N-1 nodes
78                          logic [2**(IdxW+1)-2:0]           req_tree;
79                          logic [2**(IdxW+1)-2:0]           prio_tree;
80                          logic [2**(IdxW+1)-2:0]           sel_tree;
81                          logic [2**(IdxW+1)-2:0]           mask_tree;
82                          logic [2**(IdxW+1)-2:0][IdxW-1:0] idx_tree;
83                          logic [2**(IdxW+1)-2:0][DW-1:0]   data_tree;
84                          logic [N-1:0]                     prio_mask_d, prio_mask_q;
85                      
86                          for (genvar level = 0; level < IdxW+1; level++) begin : gen_tree
87                            //
88                            // level+1   C0   C1   <- "Base1" points to the first node on "level+1",
89                            //            \  /         these nodes are the children of the nodes one level below
90                            // level       Pa      <- "Base0", points to the first node on "level",
91                            //                         these nodes are the parents of the nodes one level above
92                            //
93                            // hence we have the following indices for the Pa, C0, C1 nodes:
94                            // Pa = 2**level     - 1 + offset       = Base0 + offset
95                            // C0 = 2**(level+1) - 1 + 2*offset     = Base1 + 2*offset
96                            // C1 = 2**(level+1) - 1 + 2*offset + 1 = Base1 + 2*offset + 1
97                            //
98                            localparam int Base0 = (2**level)-1;
99                            localparam int Base1 = (2**(level+1))-1;
100                     
101                           for (genvar offset = 0; offset < 2**level; offset++) begin : gen_level
102                             localparam int Pa = Base0 + offset;
103                             localparam int C0 = Base1 + 2*offset;
104                             localparam int C1 = Base1 + 2*offset + 1;
105                     
106                             // this assigns the gated interrupt source signals, their
107                             // corresponding IDs and priorities to the tree leafs
108                             if (level == IdxW) begin : gen_leafs
109                               if (offset < N) begin : gen_assign
110                                 // forward path (requests and data)
111                                 // all requests inputs are assigned to the request tree
112        2/2                      assign req_tree[Pa]      = req_i[offset];
           Tests:       T1 T2 T3  | T1 T2 T3 
113                                 // we basically split the incoming request vector into two halves with the following
114                                 // priority assignment. the prio_mask_q register contains a prefix sum that has been
115                                 // computed using the last winning index, and hence masks out all requests at offsets
116                                 // lower or equal the previously granted index. hence, all higher indices are considered
117                                 // first in the arbitration tree nodes below, before considering the lower indices.
118        2/2                      assign prio_tree[Pa]     = req_i[offset] & prio_mask_q[offset];
           Tests:       T1 T2 T3  | T1 T2 T3 
119                                 // input for the index muxes (used to compute the winner index)
120                                 assign idx_tree[Pa]      = offset;
121                                 // input for the data muxes
122        2/2                      assign data_tree[Pa]     = data_i[offset];
           Tests:       T1 T2 T3  | T1 T2 T3 
123                     
124                                 // backward path (grants and prefix sum)
125                                 // grant if selected, ready and request asserted
126        unreachable              assign gnt_o[offset]       = req_i[offset] & sel_tree[Pa] & ready_i;
127                                 // only update mask if there is a valid request
128        2/2                      assign prio_mask_d[offset] = (|req_i) ?
           Tests:       T1 T2 T3  | T1 T2 T3 
129                                                              mask_tree[Pa] | sel_tree[Pa] & ~ready_i :
130                                                              prio_mask_q[offset];
131                               end else begin : gen_tie_off
132                                 // forward path
133                                 assign req_tree[Pa]  = '0;
134                                 assign prio_tree[Pa] = '0;
135                                 assign idx_tree[Pa]  = '0;
136                                 assign data_tree[Pa] = '0;
137                                 logic unused_sigs;
138                                 assign unused_sigs = ^{mask_tree[Pa],
139                                                        sel_tree[Pa]};
140                               end
141                             // this creates the node assignments
142                             end else begin : gen_nodes
143                               // local helper variable
144                               logic sel;
145                     
146                               // forward path (requests and data)
147                               // each node looks at its two children, and selects the one with higher priority
148        1/1                    assign sel = ~req_tree[C0] | ~prio_tree[C0] & prio_tree[C1];
           Tests:       T1 T2 T3 
149                               // propagate requests
150        1/1                    assign req_tree[Pa]  = req_tree[C0] | req_tree[C1];
           Tests:       T1 T2 T3 
151        1/1                    assign prio_tree[Pa] = prio_tree[C1] | prio_tree[C0];
           Tests:       T1 T2 T3 
152                               // data and index muxes
153                               // Note: these ternaries have triggered a synthesis bug in Vivado versions older
154                               // than 2020.2. If the problem resurfaces again, have a look at issue #1408.
155        1/1                    assign idx_tree[Pa]  = (sel) ? idx_tree[C1]  : idx_tree[C0];
           Tests:       T1 T2 T3 
156        1/1                    assign data_tree[Pa] = (sel) ? data_tree[C1] : data_tree[C0];
           Tests:       T1 T2 T3 
157                     
158                               // backward path (grants and prefix sum)
159                               // this propagates the selction index back and computes a hot one mask
160        1/1                    assign sel_tree[C0] = sel_tree[Pa] & ~sel;
           Tests:       T1 T2 T3 
161        1/1                    assign sel_tree[C1] = sel_tree[Pa] &  sel;
           Tests:       T1 T2 T3 
162                               // this performs a prefix sum for masking the input requests in the next cycle
163        unreachable            assign mask_tree[C0] = mask_tree[Pa];
164        1/1                    assign mask_tree[C1] = mask_tree[Pa] | sel_tree[C0];
           Tests:       T1 T2 T3 
165                             end
166                           end : gen_level
167                         end : gen_tree
168                     
169                         // the results can be found at the tree root
170                         if (EnDataPort) begin : gen_data_port
171        1/1                assign data_o      = data_tree[0];
           Tests:       T1 T2 T3 
172                         end else begin : gen_no_dataport
173                           logic [DW-1:0] unused_data;
174                           assign unused_data = data_tree[0];
175                           assign data_o = '1;
176                         end
177                     
178                         // This index is unused.
179                         logic unused_prio_tree;
180        1/1              assign unused_prio_tree = prio_tree[0];
           Tests:       T1 T2 T3 
181                     
182        1/1              assign idx_o       = idx_tree[0];
           Tests:       T1 T2 T3 
183        1/1              assign valid_o     = req_tree[0];
           Tests:       T1 T2 T3 
184                     
185                         // the select tree computes a hot one signal that indicates which request is currently selected
186                         assign sel_tree[0] = 1'b1;
187                         // the mask tree is basically a prefix sum of the hot one select signal computed above
188                         assign mask_tree[0] = 1'b0;
189                     
190                         always_ff @(posedge clk_i or negedge rst_ni) begin : p_mask_reg
191        1/1                if (!rst_ni) begin
           Tests:       T1 T2 T3 
192        1/1                  prio_mask_q <= '0;
           Tests:       T1 T2 T3 
193                           end else begin
194        1/1                  prio_mask_q <= prio_mask_d;
           Tests:       T1 T2 T3 

---

Cond Coverage for Instance : tb.dut.u_eflash.u_scramble.u_prim_arbiter_tree_calc.gen_input_bufs[1].gen_rr_arbiter.u_arb

	Total	Covered	Percent
Conditions	43	42	97.67
Logical	43	42	97.67
Non-Logical	0	0
Event	0	0

 LINE       118
 EXPRESSION (req_i[0] & gen_normal_case.prio_mask_q[0])
             ----1---   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       118
 EXPRESSION (req_i[1] & gen_normal_case.prio_mask_q[1])
             ----1---   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T6,T25,T11
1	1	Covered	T4,T6,T31

 LINE       126
 EXPRESSION (req_i[0] & gen_normal_case.sel_tree[gen_normal_case.gen_tree[1].gen_level[0].Pa] & ready_i)
             ----1---   ----------------------------------2----------------------------------   ---3---

-1-	-2-	-3-	Status	Tests
0	1	1	Unreachable
1	0	1	Unreachable	T11,T61,T68
1	1	0	Covered	T1,T2,T3
1	1	1	Unreachable	T1,T2,T3

 LINE       126
 EXPRESSION (req_i[1] & gen_normal_case.sel_tree[gen_normal_case.gen_tree[1].gen_level[1].Pa] & ready_i)
             ----1---   ----------------------------------2----------------------------------   ---3---

-1-	-2-	-3-	Status	Tests
0	1	1	Unreachable	T99
1	0	1	Unreachable	T11,T61,T68
1	1	0	Covered	T4,T6,T31
1	1	1	Unreachable	T4,T6,T31

 LINE       128
 EXPRESSION 
 Number  Term
      1  ((|req_i)) ? (gen_normal_case.mask_tree[gen_normal_case.gen_tree[1].gen_level[0].Pa] | (gen_normal_case.sel_tree[gen_normal_case.gen_tree[1].gen_level[0].Pa] & ((~ready_i)))) : gen_normal_case.prio_mask_q[0])

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       128
 SUB-EXPRESSION 
 Number  Term
      1  gen_normal_case.mask_tree[gen_normal_case.gen_tree[1].gen_level[0].Pa] | 
      2  (gen_normal_case.sel_tree[gen_normal_case.gen_tree[1].gen_level[0].Pa] & ((~ready_i))))

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Unreachable

 LINE       128
 SUB-EXPRESSION (gen_normal_case.sel_tree[gen_normal_case.gen_tree[1].gen_level[0].Pa] & ((~ready_i)))
                 ----------------------------------1----------------------------------   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T4,T6,T31
1	0	Unreachable	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       128
 EXPRESSION 
 Number  Term
      1  ((|req_i)) ? (gen_normal_case.mask_tree[gen_normal_case.gen_tree[1].gen_level[1].Pa] | (gen_normal_case.sel_tree[gen_normal_case.gen_tree[1].gen_level[1].Pa] & ((~ready_i)))) : gen_normal_case.prio_mask_q[1])

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       128
 SUB-EXPRESSION 
 Number  Term
      1  gen_normal_case.mask_tree[gen_normal_case.gen_tree[1].gen_level[1].Pa] | 
      2  (gen_normal_case.sel_tree[gen_normal_case.gen_tree[1].gen_level[1].Pa] & ((~ready_i))))

-1-	-2-	Status	Tests
0	0	Covered	T4,T6,T31
0	1	Covered	T4,T6,T31
1	0	Covered	T1,T2,T3

 LINE       128
 SUB-EXPRESSION (gen_normal_case.sel_tree[gen_normal_case.gen_tree[1].gen_level[1].Pa] & ((~ready_i)))
                 ----------------------------------1----------------------------------   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Unreachable	T4,T6,T31
1	1	Covered	T4,T6,T31

 LINE       148
 EXPRESSION 
 Number  Term
      1  ((~gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])) | 
      2  (((~gen_normal_case.prio_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])) & gen_normal_case.prio_tree[gen_normal_case.gen_tree[0].gen_level[0].C1]))

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T11,T61,T68
1	0	Covered	T1,T2,T3

 LINE       148
 SUB-EXPRESSION 
 Number  Term
      1  ((~gen_normal_case.prio_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])) & 
      2  gen_normal_case.prio_tree[gen_normal_case.gen_tree[0].gen_level[0].C1])

-1-	-2-	Status	Tests
0	1	Covered	T11,T61,T68
1	0	Covered	T1,T2,T3
1	1	Covered	T4,T6,T31

 LINE       150
 EXPRESSION (gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C0] | gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C1])
             ----------------------------------1----------------------------------   ----------------------------------2----------------------------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T4,T6,T31
1	0	Covered	T1,T2,T3

 LINE       151
 EXPRESSION (gen_normal_case.prio_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] | gen_normal_case.prio_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])
             -----------------------------------1----------------------------------   -----------------------------------2----------------------------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T4,T6,T31

 LINE       155
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       156
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       160
 EXPRESSION (gen_normal_case.sel_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & ((~gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)))
             ----------------------------------1----------------------------------   -----------------------------2-----------------------------

-1-	-2-	Status	Tests
0	1	Unreachable
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       161
 EXPRESSION (gen_normal_case.sel_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)
             ----------------------------------1----------------------------------   ---------------------------2--------------------------

-1-	-2-	Status	Tests
0	1	Unreachable
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       164
 EXPRESSION (gen_normal_case.mask_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] | gen_normal_case.sel_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])
             -----------------------------------1----------------------------------   ----------------------------------2----------------------------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Unreachable

---

Branch Coverage for Instance : tb.dut.u_eflash.u_scramble.u_prim_arbiter_tree_calc.gen_input_bufs[1].gen_rr_arbiter.u_arb

	Line No.	Total	Covered	Percent
Branches		10	10	100.00
TERNARY	155	2	2	100.00
TERNARY	156	2	2	100.00
TERNARY	128	2	2	100.00
TERNARY	128	2	2	100.00
IF	191	2	2	100.00

155                  assign idx_tree[Pa]  = (sel) ? idx_tree[C1]  : idx_tree[C0];
                                                  -1-  
                                                  ==>  
                                                  ==>  

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

156                  assign data_tree[Pa] = (sel) ? data_tree[C1] : data_tree[C0];
                                                  -1-  
                                                  ==>  
                                                  ==>  

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

128                    assign prio_mask_d[offset] = (|req_i) ?
                                                             -1-  
                                                             ==>  
                                                             ==>  

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

128                    assign prio_mask_d[offset] = (|req_i) ?
                                                             -1-  
                                                             ==>  
                                                             ==>  

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

191              if (!rst_ni) begin
                 -1-  
192                prio_mask_q <= '0;
                   ==>
193              end else begin
194                prio_mask_q <= prio_mask_d;
                   ==>

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_eflash.u_scramble.u_prim_arbiter_tree_calc.gen_input_bufs[1].gen_rr_arbiter.u_arb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	15	93.75
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	15	93.75

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	391176692	390364170	0	0
CheckNGreaterZero_A	1051	1051	0	0
GntImpliesReady_A	391176692	17043664	0	0
GntImpliesValid_A	391176692	17043664	0	0
GrantKnown_A	391176692	390364170	0	0
IdxKnown_A	391176692	390364170	0	0
IndexIsCorrect_A	391176692	17043664	0	0
LockArbDecision_A	391176539	17043588	0	0
NoReadyValidNoGrant_A	391176692	356276812	0	0
ReadyAndValidImplyGrant_A	391176692	17043664	0	0
ReqAndReadyImplyGrant_A	391176692	17043664	0	0
ReqImpliesValid_A	391176692	34087340	0	0
ReqStaysHighUntilGranted0_M	391107693	17043368	0	0
RoundRobin_A	391176692	0	0	1047
ValidKnown_A	391176692	390364170	0	0
gen_data_port_assertion.DataFlow_A	391176692	17043664	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	391176692	390364170	0	0
T1	2070	1970	0	0
T2	3480	3381	0	0
T3	1887	1822	0	0
T4	4370	3912	0	0
T5	677	579	0	0
T8	45213	45151	0	0
T9	1406	1318	0	0
T10	2124	2046	0	0
T16	1541	1471	0	0
T17	1625	1542	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1051	1051	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	391176692	17043664	0	0
T1	2070	32	0	0
T2	3480	32	0	0
T3	1887	105	0	0
T4	4370	198	0	0
T5	677	37	0	0
T8	45213	32	0	0
T9	1406	32	0	0
T10	2124	32	0	0
T16	1541	32	0	0
T17	1625	32	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	391176692	17043664	0	0
T1	2070	32	0	0
T2	3480	32	0	0
T3	1887	105	0	0
T4	4370	198	0	0
T5	677	37	0	0
T8	45213	32	0	0
T9	1406	32	0	0
T10	2124	32	0	0
T16	1541	32	0	0
T17	1625	32	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	391176692	390364170	0	0
T1	2070	1970	0	0
T2	3480	3381	0	0
T3	1887	1822	0	0
T4	4370	3912	0	0
T5	677	579	0	0
T8	45213	45151	0	0
T9	1406	1318	0	0
T10	2124	2046	0	0
T16	1541	1471	0	0
T17	1625	1542	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	391176692	390364170	0	0
T1	2070	1970	0	0
T2	3480	3381	0	0
T3	1887	1822	0	0
T4	4370	3912	0	0
T5	677	579	0	0
T8	45213	45151	0	0
T9	1406	1318	0	0
T10	2124	2046	0	0
T16	1541	1471	0	0
T17	1625	1542	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	391176692	17043664	0	0
T1	2070	32	0	0
T2	3480	32	0	0
T3	1887	105	0	0
T4	4370	198	0	0
T5	677	37	0	0
T8	45213	32	0	0
T9	1406	32	0	0
T10	2124	32	0	0
T16	1541	32	0	0
T17	1625	32	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	391176539	17043588	0	0
T1	2070	32	0	0
T2	3480	32	0	0
T3	1887	105	0	0
T4	4370	198	0	0
T5	677	37	0	0
T8	45213	32	0	0
T9	1406	32	0	0
T10	2124	32	0	0
T16	1541	32	0	0
T17	1625	32	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	391176692	356276812	0	0
T1	2070	1906	0	0
T2	3480	3317	0	0
T3	1887	1612	0	0
T4	4370	3516	0	0
T5	677	505	0	0
T8	45213	45087	0	0
T9	1406	1254	0	0
T10	2124	1982	0	0
T16	1541	1407	0	0
T17	1625	1478	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	391176692	17043664	0	0
T1	2070	32	0	0
T2	3480	32	0	0
T3	1887	105	0	0
T4	4370	198	0	0
T5	677	37	0	0
T8	45213	32	0	0
T9	1406	32	0	0
T10	2124	32	0	0
T16	1541	32	0	0
T17	1625	32	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	391176692	17043664	0	0
T1	2070	32	0	0
T2	3480	32	0	0
T3	1887	105	0	0
T4	4370	198	0	0
T5	677	37	0	0
T8	45213	32	0	0
T9	1406	32	0	0
T10	2124	32	0	0
T16	1541	32	0	0
T17	1625	32	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	391176692	34087340	0	0
T1	2070	64	0	0
T2	3480	64	0	0
T3	1887	210	0	0
T4	4370	396	0	0
T5	677	74	0	0
T8	45213	64	0	0
T9	1406	64	0	0
T10	2124	64	0	0
T16	1541	64	0	0
T17	1625	64	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	391107693	17043368	0	0
T1	2070	32	0	0
T2	3480	32	0	0
T3	1887	105	0	0
T4	4370	198	0	0
T5	677	37	0	0
T8	45213	32	0	0
T9	1406	32	0	0
T10	2124	32	0	0
T16	1541	32	0	0
T17	1625	32	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	391176692	0	0	1047

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	391176692	390364170	0	0
T1	2070	1970	0	0
T2	3480	3381	0	0
T3	1887	1822	0	0
T4	4370	3912	0	0
T5	677	579	0	0
T8	45213	45151	0	0
T9	1406	1318	0	0
T10	2124	2046	0	0
T16	1541	1471	0	0
T17	1625	1542	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	391176692	17043664	0	0
T1	2070	32	0	0
T2	3480	32	0	0
T3	1887	105	0	0
T4	4370	198	0	0
T5	677	37	0	0
T8	45213	32	0	0
T9	1406	32	0	0
T10	2124	32	0	0
T16	1541	32	0	0
T17	1625	32	0	0

Line Coverage for Instance : tb.dut.u_eflash.u_scramble.u_prim_arbiter_tree_calc.gen_input_bufs[0].gen_rr_arbiter.u_arb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	62	0	0
CONT_ASSIGN	112	1	1	100.00
CONT_ASSIGN	112	1	1	100.00
CONT_ASSIGN	118	1	1	100.00
CONT_ASSIGN	118	1	1	100.00
CONT_ASSIGN	122	1	1	100.00
CONT_ASSIGN	122	1	1	100.00
CONT_ASSIGN	126	0	0
CONT_ASSIGN	126	0	0
CONT_ASSIGN	128	1	1	100.00
CONT_ASSIGN	128	1	1	100.00
CONT_ASSIGN	148	1	1	100.00
CONT_ASSIGN	150	1	1	100.00
CONT_ASSIGN	151	1	1	100.00
CONT_ASSIGN	155	1	1	100.00
CONT_ASSIGN	156	1	1	100.00
CONT_ASSIGN	160	1	1	100.00
CONT_ASSIGN	161	1	1	100.00
CONT_ASSIGN	163	0	0
CONT_ASSIGN	164	1	1	100.00
CONT_ASSIGN	171	1	1	100.00
CONT_ASSIGN	180	1	1	100.00
CONT_ASSIGN	182	1	1	100.00
CONT_ASSIGN	183	1	1	100.00
ALWAYS	191	3	3	100.00

61                        logic unused_req_chk;
62         unreachable    assign unused_req_chk = req_chk_i;
63                      
64                        `ASSERT_INIT(CheckNGreaterZero_A, N > 0)
65                      
66                        // this case is basically just a bypass
67                        if (N == 1) begin : gen_degenerate_case
68                      
69                          assign valid_o  = req_i[0];
70                          assign data_o   = data_i[0];
71                          assign gnt_o[0] = valid_o & ready_i;
72                          assign idx_o    = '0;
73                      
74                        end else begin : gen_normal_case
75                      
76                          // align to powers of 2 for simplicity
77                          // a full binary tree with N levels has 2**N + 2**N-1 nodes
78                          logic [2**(IdxW+1)-2:0]           req_tree;
79                          logic [2**(IdxW+1)-2:0]           prio_tree;
80                          logic [2**(IdxW+1)-2:0]           sel_tree;
81                          logic [2**(IdxW+1)-2:0]           mask_tree;
82                          logic [2**(IdxW+1)-2:0][IdxW-1:0] idx_tree;
83                          logic [2**(IdxW+1)-2:0][DW-1:0]   data_tree;
84                          logic [N-1:0]                     prio_mask_d, prio_mask_q;
85                      
86                          for (genvar level = 0; level < IdxW+1; level++) begin : gen_tree
87                            //
88                            // level+1   C0   C1   <- "Base1" points to the first node on "level+1",
89                            //            \  /         these nodes are the children of the nodes one level below
90                            // level       Pa      <- "Base0", points to the first node on "level",
91                            //                         these nodes are the parents of the nodes one level above
92                            //
93                            // hence we have the following indices for the Pa, C0, C1 nodes:
94                            // Pa = 2**level     - 1 + offset       = Base0 + offset
95                            // C0 = 2**(level+1) - 1 + 2*offset     = Base1 + 2*offset
96                            // C1 = 2**(level+1) - 1 + 2*offset + 1 = Base1 + 2*offset + 1
97                            //
98                            localparam int Base0 = (2**level)-1;
99                            localparam int Base1 = (2**(level+1))-1;
100                     
101                           for (genvar offset = 0; offset < 2**level; offset++) begin : gen_level
102                             localparam int Pa = Base0 + offset;
103                             localparam int C0 = Base1 + 2*offset;
104                             localparam int C1 = Base1 + 2*offset + 1;
105                     
106                             // this assigns the gated interrupt source signals, their
107                             // corresponding IDs and priorities to the tree leafs
108                             if (level == IdxW) begin : gen_leafs
109                               if (offset < N) begin : gen_assign
110                                 // forward path (requests and data)
111                                 // all requests inputs are assigned to the request tree
112        2/2                      assign req_tree[Pa]      = req_i[offset];
           Tests:       T1 T2 T3  | T1 T2 T3 
113                                 // we basically split the incoming request vector into two halves with the following
114                                 // priority assignment. the prio_mask_q register contains a prefix sum that has been
115                                 // computed using the last winning index, and hence masks out all requests at offsets
116                                 // lower or equal the previously granted index. hence, all higher indices are considered
117                                 // first in the arbitration tree nodes below, before considering the lower indices.
118        2/2                      assign prio_tree[Pa]     = req_i[offset] & prio_mask_q[offset];
           Tests:       T1 T2 T3  | T1 T2 T3 
119                                 // input for the index muxes (used to compute the winner index)
120                                 assign idx_tree[Pa]      = offset;
121                                 // input for the data muxes
122        2/2                      assign data_tree[Pa]     = data_i[offset];
           Tests:       T1 T2 T3  | T1 T2 T3 
123                     
124                                 // backward path (grants and prefix sum)
125                                 // grant if selected, ready and request asserted
126        unreachable              assign gnt_o[offset]       = req_i[offset] & sel_tree[Pa] & ready_i;
127                                 // only update mask if there is a valid request
128        2/2                      assign prio_mask_d[offset] = (|req_i) ?
           Tests:       T1 T2 T3  | T1 T2 T3 
129                                                              mask_tree[Pa] | sel_tree[Pa] & ~ready_i :
130                                                              prio_mask_q[offset];
131                               end else begin : gen_tie_off
132                                 // forward path
133                                 assign req_tree[Pa]  = '0;
134                                 assign prio_tree[Pa] = '0;
135                                 assign idx_tree[Pa]  = '0;
136                                 assign data_tree[Pa] = '0;
137                                 logic unused_sigs;
138                                 assign unused_sigs = ^{mask_tree[Pa],
139                                                        sel_tree[Pa]};
140                               end
141                             // this creates the node assignments
142                             end else begin : gen_nodes
143                               // local helper variable
144                               logic sel;
145                     
146                               // forward path (requests and data)
147                               // each node looks at its two children, and selects the one with higher priority
148        1/1                    assign sel = ~req_tree[C0] | ~prio_tree[C0] & prio_tree[C1];
           Tests:       T1 T2 T3 
149                               // propagate requests
150        1/1                    assign req_tree[Pa]  = req_tree[C0] | req_tree[C1];
           Tests:       T1 T2 T3 
151        1/1                    assign prio_tree[Pa] = prio_tree[C1] | prio_tree[C0];
           Tests:       T1 T2 T3 
152                               // data and index muxes
153                               // Note: these ternaries have triggered a synthesis bug in Vivado versions older
154                               // than 2020.2. If the problem resurfaces again, have a look at issue #1408.
155        1/1                    assign idx_tree[Pa]  = (sel) ? idx_tree[C1]  : idx_tree[C0];
           Tests:       T1 T2 T3 
156        1/1                    assign data_tree[Pa] = (sel) ? data_tree[C1] : data_tree[C0];
           Tests:       T1 T2 T3 
157                     
158                               // backward path (grants and prefix sum)
159                               // this propagates the selction index back and computes a hot one mask
160        1/1                    assign sel_tree[C0] = sel_tree[Pa] & ~sel;
           Tests:       T1 T2 T3 
161        1/1                    assign sel_tree[C1] = sel_tree[Pa] &  sel;
           Tests:       T1 T2 T3 
162                               // this performs a prefix sum for masking the input requests in the next cycle
163        unreachable            assign mask_tree[C0] = mask_tree[Pa];
164        1/1                    assign mask_tree[C1] = mask_tree[Pa] | sel_tree[C0];
           Tests:       T1 T2 T3 
165                             end
166                           end : gen_level
167                         end : gen_tree
168                     
169                         // the results can be found at the tree root
170                         if (EnDataPort) begin : gen_data_port
171        1/1                assign data_o      = data_tree[0];
           Tests:       T1 T2 T3 
172                         end else begin : gen_no_dataport
173                           logic [DW-1:0] unused_data;
174                           assign unused_data = data_tree[0];
175                           assign data_o = '1;
176                         end
177                     
178                         // This index is unused.
179                         logic unused_prio_tree;
180        1/1              assign unused_prio_tree = prio_tree[0];
           Tests:       T1 T2 T3 
181                     
182        1/1              assign idx_o       = idx_tree[0];
           Tests:       T1 T2 T3 
183        1/1              assign valid_o     = req_tree[0];
           Tests:       T1 T2 T3 
184                     
185                         // the select tree computes a hot one signal that indicates which request is currently selected
186                         assign sel_tree[0] = 1'b1;
187                         // the mask tree is basically a prefix sum of the hot one select signal computed above
188                         assign mask_tree[0] = 1'b0;
189                     
190                         always_ff @(posedge clk_i or negedge rst_ni) begin : p_mask_reg
191        1/1                if (!rst_ni) begin
           Tests:       T1 T2 T3 
192        1/1                  prio_mask_q <= '0;
           Tests:       T1 T2 T3 
193                           end else begin
194        1/1                  prio_mask_q <= prio_mask_d;
           Tests:       T1 T2 T3 

---

Cond Coverage for Instance : tb.dut.u_eflash.u_scramble.u_prim_arbiter_tree_calc.gen_input_bufs[0].gen_rr_arbiter.u_arb

	Total	Covered	Percent
Conditions	43	43	100.00
Logical	43	43	100.00
Non-Logical	0	0
Event	0	0

 LINE       118
 EXPRESSION (req_i[0] & gen_normal_case.prio_mask_q[0])
             ----1---   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T99
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       118
 EXPRESSION (req_i[1] & gen_normal_case.prio_mask_q[1])
             ----1---   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T6,T25,T11
1	1	Covered	T4,T6,T31

 LINE       126
 EXPRESSION (req_i[0] & gen_normal_case.sel_tree[gen_normal_case.gen_tree[1].gen_level[0].Pa] & ready_i)
             ----1---   ----------------------------------2----------------------------------   ---3---

-1-	-2-	-3-	Status	Tests
0	1	1	Unreachable
1	0	1	Unreachable	T11,T61,T68
1	1	0	Covered	T1,T2,T3
1	1	1	Unreachable	T1,T2,T3

 LINE       126
 EXPRESSION (req_i[1] & gen_normal_case.sel_tree[gen_normal_case.gen_tree[1].gen_level[1].Pa] & ready_i)
             ----1---   ----------------------------------2----------------------------------   ---3---

-1-	-2-	-3-	Status	Tests
0	1	1	Unreachable	T99,T100
1	0	1	Unreachable	T11,T61,T68
1	1	0	Covered	T4,T6,T31
1	1	1	Unreachable	T4,T6,T31

 LINE       128
 EXPRESSION 
 Number  Term
      1  ((|req_i)) ? (gen_normal_case.mask_tree[gen_normal_case.gen_tree[1].gen_level[0].Pa] | (gen_normal_case.sel_tree[gen_normal_case.gen_tree[1].gen_level[0].Pa] & ((~ready_i)))) : gen_normal_case.prio_mask_q[0])

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       128
 SUB-EXPRESSION 
 Number  Term
      1  gen_normal_case.mask_tree[gen_normal_case.gen_tree[1].gen_level[0].Pa] | 
      2  (gen_normal_case.sel_tree[gen_normal_case.gen_tree[1].gen_level[0].Pa] & ((~ready_i))))

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Unreachable

 LINE       128
 SUB-EXPRESSION (gen_normal_case.sel_tree[gen_normal_case.gen_tree[1].gen_level[0].Pa] & ((~ready_i)))
                 ----------------------------------1----------------------------------   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T4,T6,T31
1	0	Unreachable	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       128
 EXPRESSION 
 Number  Term
      1  ((|req_i)) ? (gen_normal_case.mask_tree[gen_normal_case.gen_tree[1].gen_level[1].Pa] | (gen_normal_case.sel_tree[gen_normal_case.gen_tree[1].gen_level[1].Pa] & ((~ready_i)))) : gen_normal_case.prio_mask_q[1])

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       128
 SUB-EXPRESSION 
 Number  Term
      1  gen_normal_case.mask_tree[gen_normal_case.gen_tree[1].gen_level[1].Pa] | 
      2  (gen_normal_case.sel_tree[gen_normal_case.gen_tree[1].gen_level[1].Pa] & ((~ready_i))))

-1-	-2-	Status	Tests
0	0	Covered	T4,T6,T31
0	1	Covered	T4,T6,T31
1	0	Covered	T1,T2,T3

 LINE       128
 SUB-EXPRESSION (gen_normal_case.sel_tree[gen_normal_case.gen_tree[1].gen_level[1].Pa] & ((~ready_i)))
                 ----------------------------------1----------------------------------   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Unreachable	T4,T6,T31
1	1	Covered	T4,T6,T31

 LINE       148
 EXPRESSION 
 Number  Term
      1  ((~gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])) | 
      2  (((~gen_normal_case.prio_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])) & gen_normal_case.prio_tree[gen_normal_case.gen_tree[0].gen_level[0].C1]))

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T11,T61,T68
1	0	Covered	T1,T2,T3

 LINE       148
 SUB-EXPRESSION 
 Number  Term
      1  ((~gen_normal_case.prio_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])) & 
      2  gen_normal_case.prio_tree[gen_normal_case.gen_tree[0].gen_level[0].C1])

-1-	-2-	Status	Tests
0	1	Covered	T11,T61,T68
1	0	Covered	T1,T2,T3
1	1	Covered	T4,T6,T31

 LINE       150
 EXPRESSION (gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C0] | gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C1])
             ----------------------------------1----------------------------------   ----------------------------------2----------------------------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T4,T6,T31
1	0	Covered	T1,T2,T3

 LINE       151
 EXPRESSION (gen_normal_case.prio_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] | gen_normal_case.prio_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])
             -----------------------------------1----------------------------------   -----------------------------------2----------------------------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T4,T6,T31

 LINE       155
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       156
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       160
 EXPRESSION (gen_normal_case.sel_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & ((~gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)))
             ----------------------------------1----------------------------------   -----------------------------2-----------------------------

-1-	-2-	Status	Tests
0	1	Unreachable
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       161
 EXPRESSION (gen_normal_case.sel_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)
             ----------------------------------1----------------------------------   ---------------------------2--------------------------

-1-	-2-	Status	Tests
0	1	Unreachable
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       164
 EXPRESSION (gen_normal_case.mask_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] | gen_normal_case.sel_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])
             -----------------------------------1----------------------------------   ----------------------------------2----------------------------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Unreachable

---

Branch Coverage for Instance : tb.dut.u_eflash.u_scramble.u_prim_arbiter_tree_calc.gen_input_bufs[0].gen_rr_arbiter.u_arb

	Line No.	Total	Covered	Percent
Branches		10	10	100.00
TERNARY	155	2	2	100.00
TERNARY	156	2	2	100.00
TERNARY	128	2	2	100.00
TERNARY	128	2	2	100.00
IF	191	2	2	100.00

155                  assign idx_tree[Pa]  = (sel) ? idx_tree[C1]  : idx_tree[C0];
                                                  -1-  
                                                  ==>  
                                                  ==>  

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

156                  assign data_tree[Pa] = (sel) ? data_tree[C1] : data_tree[C0];
                                                  -1-  
                                                  ==>  
                                                  ==>  

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

128                    assign prio_mask_d[offset] = (|req_i) ?
                                                             -1-  
                                                             ==>  
                                                             ==>  

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

128                    assign prio_mask_d[offset] = (|req_i) ?
                                                             -1-  
                                                             ==>  
                                                             ==>  

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

191              if (!rst_ni) begin
                 -1-  
192                prio_mask_q <= '0;
                   ==>
193              end else begin
194                prio_mask_q <= prio_mask_d;
                   ==>

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_eflash.u_scramble.u_prim_arbiter_tree_calc.gen_input_bufs[0].gen_rr_arbiter.u_arb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	15	93.75
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	15	93.75

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	391176692	390364170	0	0
CheckNGreaterZero_A	1051	1051	0	0
GntImpliesReady_A	391176692	17043590	0	0
GntImpliesValid_A	391176692	17043590	0	0
GrantKnown_A	391176692	390364170	0	0
IdxKnown_A	391176692	390364170	0	0
IndexIsCorrect_A	391176692	17043590	0	0
LockArbDecision_A	391176539	17043588	0	0
NoReadyValidNoGrant_A	391176692	356276886	0	0
ReadyAndValidImplyGrant_A	391176692	17043590	0	0
ReqAndReadyImplyGrant_A	391176692	17043590	0	0
ReqImpliesValid_A	391176692	34087192	0	0
ReqStaysHighUntilGranted0_M	391107693	17043368	0	0
RoundRobin_A	391176692	0	0	1047
ValidKnown_A	391176692	390364170	0	0
gen_data_port_assertion.DataFlow_A	391176692	17043590	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	391176692	390364170	0	0
T1	2070	1970	0	0
T2	3480	3381	0	0
T3	1887	1822	0	0
T4	4370	3912	0	0
T5	677	579	0	0
T8	45213	45151	0	0
T9	1406	1318	0	0
T10	2124	2046	0	0
T16	1541	1471	0	0
T17	1625	1542	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1051	1051	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	391176692	17043590	0	0
T1	2070	32	0	0
T2	3480	32	0	0
T3	1887	105	0	0
T4	4370	198	0	0
T5	677	37	0	0
T8	45213	32	0	0
T9	1406	32	0	0
T10	2124	32	0	0
T16	1541	32	0	0
T17	1625	32	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	391176692	17043590	0	0
T1	2070	32	0	0
T2	3480	32	0	0
T3	1887	105	0	0
T4	4370	198	0	0
T5	677	37	0	0
T8	45213	32	0	0
T9	1406	32	0	0
T10	2124	32	0	0
T16	1541	32	0	0
T17	1625	32	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	391176692	390364170	0	0
T1	2070	1970	0	0
T2	3480	3381	0	0
T3	1887	1822	0	0
T4	4370	3912	0	0
T5	677	579	0	0
T8	45213	45151	0	0
T9	1406	1318	0	0
T10	2124	2046	0	0
T16	1541	1471	0	0
T17	1625	1542	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	391176692	390364170	0	0
T1	2070	1970	0	0
T2	3480	3381	0	0
T3	1887	1822	0	0
T4	4370	3912	0	0
T5	677	579	0	0
T8	45213	45151	0	0
T9	1406	1318	0	0
T10	2124	2046	0	0
T16	1541	1471	0	0
T17	1625	1542	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	391176692	17043590	0	0
T1	2070	32	0	0
T2	3480	32	0	0
T3	1887	105	0	0
T4	4370	198	0	0
T5	677	37	0	0
T8	45213	32	0	0
T9	1406	32	0	0
T10	2124	32	0	0
T16	1541	32	0	0
T17	1625	32	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	391176539	17043588	0	0
T1	2070	32	0	0
T2	3480	32	0	0
T3	1887	105	0	0
T4	4370	198	0	0
T5	677	37	0	0
T8	45213	32	0	0
T9	1406	32	0	0
T10	2124	32	0	0
T16	1541	32	0	0
T17	1625	32	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	391176692	356276886	0	0
T1	2070	1906	0	0
T2	3480	3317	0	0
T3	1887	1612	0	0
T4	4370	3516	0	0
T5	677	505	0	0
T8	45213	45087	0	0
T9	1406	1254	0	0
T10	2124	1982	0	0
T16	1541	1407	0	0
T17	1625	1478	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	391176692	17043590	0	0
T1	2070	32	0	0
T2	3480	32	0	0
T3	1887	105	0	0
T4	4370	198	0	0
T5	677	37	0	0
T8	45213	32	0	0
T9	1406	32	0	0
T10	2124	32	0	0
T16	1541	32	0	0
T17	1625	32	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	391176692	17043590	0	0
T1	2070	32	0	0
T2	3480	32	0	0
T3	1887	105	0	0
T4	4370	198	0	0
T5	677	37	0	0
T8	45213	32	0	0
T9	1406	32	0	0
T10	2124	32	0	0
T16	1541	32	0	0
T17	1625	32	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	391176692	34087192	0	0
T1	2070	64	0	0
T2	3480	64	0	0
T3	1887	210	0	0
T4	4370	396	0	0
T5	677	74	0	0
T8	45213	64	0	0
T9	1406	64	0	0
T10	2124	64	0	0
T16	1541	64	0	0
T17	1625	64	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	391107693	17043368	0	0
T1	2070	32	0	0
T2	3480	32	0	0
T3	1887	105	0	0
T4	4370	198	0	0
T5	677	37	0	0
T8	45213	32	0	0
T9	1406	32	0	0
T10	2124	32	0	0
T16	1541	32	0	0
T17	1625	32	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	391176692	0	0	1047

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	391176692	390364170	0	0
T1	2070	1970	0	0
T2	3480	3381	0	0
T3	1887	1822	0	0
T4	4370	3912	0	0
T5	677	579	0	0
T8	45213	45151	0	0
T9	1406	1318	0	0
T10	2124	2046	0	0
T16	1541	1471	0	0
T17	1625	1542	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	391176692	17043590	0	0
T1	2070	32	0	0
T2	3480	32	0	0
T3	1887	105	0	0
T4	4370	198	0	0
T5	677	37	0	0
T8	45213	32	0	0
T9	1406	32	0	0
T10	2124	32	0	0
T16	1541	32	0	0
T17	1625	32	0	0