Group : cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg
dashboard | hierarchy | modlist | groups | tests | asserts

Group : cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg
SCOREINSTANCESWEIGHTGOALAT LEASTPER INSTANCEAUTO BIN MAXPRINT MISSING
100.00 97.92 1 100 1 1 64 64


Source File(s) :
/workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

2 Instances:
NAMESCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
tl_intg_err_mem_subword_cgs_wrap[flash_ctrl_eflash_reg_block] 95.83 1 100 1 64 64
tl_intg_err_mem_subword_cgs_wrap[flash_ctrl_core_reg_block] 100.00 1 100 1 64 64



Group Instance : tl_intg_err_mem_subword_cgs_wrap[flash_ctrl_eflash_reg_block]
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
95.83 1 100 1 64 64



Summary for Group Instance tl_intg_err_mem_subword_cgs_wrap[flash_ctrl_eflash_reg_block]

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 8 0 8 100.00
Crosses 16 1 15 93.75


Variables for Group Instance tl_intg_err_mem_subword_cgs_wrap[flash_ctrl_eflash_reg_block]
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
cp_num_num_enable_bytes 2 0 2 100.00 100 1 1 0
cp_tl_intg_err_type 4 0 4 100.00 100 1 1 0
cp_write 2 0 2 100.00 100 1 1 2


Crosses for Group Instance tl_intg_err_mem_subword_cgs_wrap[flash_ctrl_eflash_reg_block]
CROSSEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTPRINT MISSINGCOMMENT
cr_all 16 1 15 93.75 100 1 1 0


Group Instance : tl_intg_err_mem_subword_cgs_wrap[flash_ctrl_core_reg_block]
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64



Summary for Group Instance tl_intg_err_mem_subword_cgs_wrap[flash_ctrl_core_reg_block]

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 8 0 8 100.00
Crosses 16 0 16 100.00


Variables for Group Instance tl_intg_err_mem_subword_cgs_wrap[flash_ctrl_core_reg_block]
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
cp_num_num_enable_bytes 2 0 2 100.00 100 1 1 0
cp_tl_intg_err_type 4 0 4 100.00 100 1 1 0
cp_write 2 0 2 100.00 100 1 1 2


Crosses for Group Instance tl_intg_err_mem_subword_cgs_wrap[flash_ctrl_core_reg_block]
CROSSEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTPRINT MISSINGCOMMENT
cr_all 16 0 16 100.00 100 1 1 0


Summary for Variable cp_num_num_enable_bytes

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 2 0 2 100.00


User Defined Bins for cp_num_num_enable_bytes

Bins
NAMECOUNTAT LEASTTESTCOUNTTESTCOUNTTESTCOUNT
partial 18566 1 T128 167 T72 210 T131 1241
full_word 3704031 1 T3 547 T10 10 T11 8


Summary for Variable cp_tl_intg_err_type

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 4 0 4 100.00


Automatically Generated Bins for cp_tl_intg_err_type

Bins
NAMECOUNTAT LEASTTESTCOUNTTESTCOUNTTESTCOUNT
auto[TlIntgErrNone] 3722312 1 T3 547 T10 10 T11 8
auto[TlIntgErrCmd] 99 1 T245 4 T246 5 T247 6
auto[TlIntgErrData] 111 1 T245 4 T246 4 T247 3
auto[TlIntgErrBoth] 75 1 T245 2 T247 1 T383 3


Summary for Variable cp_write

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_write

Bins
NAMECOUNTAT LEASTTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 3699215 1 T3 547 T10 10 T11 8
auto[1] 23382 1 T128 289 T72 271 T131 1722


Summary for Cross cr_all

Samples crossed: cp_tl_intg_err_type cp_num_num_enable_bytes cp_write
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
Automatically Generated Cross Bins 16 1 15 93.75 1


Automatically Generated Cross Bins for cr_all

Uncovered bins
cp_tl_intg_err_typecp_num_num_enable_bytescp_writeCOUNTAT LEASTNUMBER
[auto[TlIntgErrBoth]] [full_word] [auto[0]] 0 1 1


Covered bins
cp_tl_intg_err_typecp_num_num_enable_bytescp_writeCOUNTAT LEASTTESTCOUNTTESTCOUNTTESTCOUNT
auto[TlIntgErrNone] partial auto[0] 1120 1 T128 6 T72 10 T131 64
auto[TlIntgErrNone] partial auto[1] 17178 1 T128 161 T72 200 T131 1177
auto[TlIntgErrNone] full_word auto[0] 3697975 1 T3 547 T10 10 T11 8
auto[TlIntgErrNone] full_word auto[1] 6039 1 T128 128 T72 71 T131 545
auto[TlIntgErrCmd] partial auto[0] 34 1 T246 1 T247 1 T383 1
auto[TlIntgErrCmd] partial auto[1] 60 1 T245 3 T246 4 T247 4
auto[TlIntgErrCmd] full_word auto[0] 2 1 T245 1 T390 1 - -
auto[TlIntgErrCmd] full_word auto[1] 3 1 T247 1 T387 1 T380 1
auto[TlIntgErrData] partial auto[0] 55 1 T245 3 T246 2 T247 1
auto[TlIntgErrData] partial auto[1] 47 1 T245 1 T246 2 T247 1
auto[TlIntgErrData] full_word auto[0] 5 1 T247 1 T391 2 T388 1
auto[TlIntgErrData] full_word auto[1] 4 1 T392 2 T387 1 T386 1
auto[TlIntgErrBoth] partial auto[0] 24 1 T245 1 T383 1 T379 1
auto[TlIntgErrBoth] partial auto[1] 48 1 T245 1 T247 1 T383 2
auto[TlIntgErrBoth] full_word auto[1] 3 1 T386 1 T388 1 T393 1


Summary for Variable cp_num_num_enable_bytes

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 2 0 2 100.00


User Defined Bins for cp_num_num_enable_bytes

Bins
NAMECOUNTAT LEASTTESTCOUNTTESTCOUNTTESTCOUNT
partial 25301908 1 T1 1141 T2 290 T3 1226
full_word 7261938 1 T1 157 T2 236 T3 3427


Summary for Variable cp_tl_intg_err_type

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 4 0 4 100.00


Automatically Generated Bins for cp_tl_intg_err_type

Bins
NAMECOUNTAT LEASTTESTCOUNTTESTCOUNTTESTCOUNT
auto[TlIntgErrNone] 32563546 1 T1 1298 T2 526 T3 4653
auto[TlIntgErrCmd] 97 1 T245 4 T246 3 T247 4
auto[TlIntgErrData] 101 1 T245 4 T246 4 T247 4
auto[TlIntgErrBoth] 102 1 T245 2 T246 3 T247 2


Summary for Variable cp_write

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_write

Bins
NAMECOUNTAT LEASTTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 28314664 1 T1 1132 T2 420 T3 1760
auto[1] 4249182 1 T1 166 T2 106 T3 2893


Summary for Cross cr_all

Samples crossed: cp_tl_intg_err_type cp_num_num_enable_bytes cp_write
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
Automatically Generated Cross Bins 16 0 16 100.00


Automatically Generated Cross Bins for cr_all

Bins
cp_tl_intg_err_typecp_num_num_enable_bytescp_writeCOUNTAT LEASTTESTCOUNTTESTCOUNTTESTCOUNT
auto[TlIntgErrNone] partial auto[0] 24631866 1 T1 1125 T2 264 T3 996
auto[TlIntgErrNone] partial auto[1] 669757 1 T1 16 T2 26 T3 230
auto[TlIntgErrNone] full_word auto[0] 3682661 1 T1 7 T2 156 T3 764
auto[TlIntgErrNone] full_word auto[1] 3579262 1 T1 150 T2 80 T3 2663
auto[TlIntgErrCmd] partial auto[0] 35 1 T245 2 T246 1 T247 2
auto[TlIntgErrCmd] partial auto[1] 56 1 T245 1 T246 2 T247 2
auto[TlIntgErrCmd] full_word auto[0] 3 1 T385 2 T382 1 - -
auto[TlIntgErrCmd] full_word auto[1] 3 1 T245 1 T392 1 T389 1
auto[TlIntgErrData] partial auto[0] 54 1 T245 3 T246 1 T383 1
auto[TlIntgErrData] partial auto[1] 43 1 T245 1 T246 3 T247 3
auto[TlIntgErrData] full_word auto[0] 2 1 T247 1 T382 1 - -
auto[TlIntgErrData] full_word auto[1] 2 1 T381 1 T389 1 - -
auto[TlIntgErrBoth] partial auto[0] 40 1 T245 1 T246 1 T247 2
auto[TlIntgErrBoth] partial auto[1] 57 1 T245 1 T246 2 T383 2
auto[TlIntgErrBoth] full_word auto[0] 3 1 T390 1 T387 1 T389 1
auto[TlIntgErrBoth] full_word auto[1] 2 1 T387 1 T388 1 - -

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