Line Coverage for Module :
flash_phy_rd_buf_dep
| Line No. | Total | Covered | Percent |
TOTAL | | 23 | 23 | 100.00 |
ALWAYS | 48 | 7 | 7 | 100.00 |
CONT_ASSIGN | 61 | 1 | 1 | 100.00 |
CONT_ASSIGN | 62 | 1 | 1 | 100.00 |
CONT_ASSIGN | 65 | 1 | 1 | 100.00 |
CONT_ASSIGN | 66 | 1 | 1 | 100.00 |
CONT_ASSIGN | 71 | 1 | 1 | 100.00 |
CONT_ASSIGN | 72 | 1 | 1 | 100.00 |
ALWAYS | 76 | 6 | 6 | 100.00 |
ALWAYS | 90 | 3 | 3 | 100.00 |
CONT_ASSIGN | 97 | 1 | 1 | 100.00 |
ALWAYS | 116 | 0 | 0 | |
47 always_comb begin
48 1/1 incr_buf_sel = '0;
Tests: T1 T2 T3
49 1/1 decr_buf_sel = '0;
Tests: T1 T2 T3
50 1/1 for (int unsigned i = 0; i < NumBuf; i++) begin
Tests: T1 T2 T3
51 1/1 if (wr_buf_i[i]) begin
Tests: T1 T2 T3
52 1/1 incr_buf_sel = buf_mux_cnt[i];
Tests: T2 T3 T4
53 end
MISSING_ELSE
54 1/1 if (rd_buf_i[i]) begin
Tests: T1 T2 T3
55 1/1 decr_buf_sel = buf_mux_cnt[i];
Tests: T2 T3 T4
56 end
MISSING_ELSE
57 end
58 end // always_comb
59
60 logic [BufDepCntWidth-1:0] curr_incr_cnt, curr_decr_cnt;
61 1/1 assign curr_incr_cnt = buf_dependency_cnt[incr_buf_sel];
Tests: T1 T2 T3
62 1/1 assign curr_decr_cnt = buf_dependency_cnt[decr_buf_sel];
Tests: T1 T2 T3
63
64 logic cnt_incr, cnt_decr;
65 1/1 assign cnt_incr = en_i & fifo_wr_i & (curr_incr_cnt < RspOrderDepth);
Tests: T1 T2 T3
66 1/1 assign cnt_decr = en_i & fifo_rd_i & (curr_decr_cnt > '0);
Tests: T1 T2 T3
67
68 //assign cnt_decr = fifo_rd_i & (rsp_fifo_vld & data_valid_o) & (curr_decr_cnt > '0);
69
70 logic fin_cnt_incr, fin_cnt_decr;
71 1/1 assign fin_cnt_incr = (incr_buf_sel == decr_buf_sel) ? cnt_incr && !cnt_decr : cnt_incr;
Tests: T1 T2 T3
72 1/1 assign fin_cnt_decr = (incr_buf_sel == decr_buf_sel) ? !cnt_incr && cnt_decr : cnt_decr;
Tests: T1 T2 T3
73
74 // This tells us which buffer currently has a dependency to an item in the rsp_order_fifo
75 always_ff @(posedge clk_i or negedge rst_ni) begin
76 1/1 if (!rst_ni) begin
Tests: T1 T2 T3
77 1/1 buf_dependency_cnt <= '0;
Tests: T1 T2 T3
78 end else begin
79 1/1 if (fin_cnt_incr) begin
Tests: T1 T2 T3
80 1/1 buf_dependency_cnt[incr_buf_sel] <= curr_incr_cnt + 1'b1;
Tests: T2 T3 T4
81 end
MISSING_ELSE
82 1/1 if (fin_cnt_decr) begin
Tests: T1 T2 T3
83 1/1 buf_dependency_cnt[decr_buf_sel] <= curr_decr_cnt - 1'b1;
Tests: T2 T3 T4
84 end
MISSING_ELSE
85 end
86 end
87
88 // per buffer dependency determination
89 always_comb begin
90 1/1 dependency_o = '0;
Tests: T1 T2 T3
91 1/1 for (int i = 0; i < NumBuf; i++) begin
Tests: T1 T2 T3
92 1/1 dependency_o[i] = |buf_dependency_cnt[i];
Tests: T1 T2 T3
93 end
94 end
95
96 // all buffer entries currently have a dependency
97 1/1 assign all_dependency_o = &dependency_o;
Tests: T1 T2 T3
98
99
100 // If there are more buffers than there are number of response fifo entries, we an never have
101 // a fully dependent condition
102 `ASSERT(BufferDepRsp_A, NumBuf > RspOrderDepth |-> ~all_dependency_o)
103
104 // We should never attempt to increment when at max value
105 `ASSERT(BufferIncrOverFlow_A, en_i & fifo_wr_i |-> curr_incr_cnt < RspOrderDepth)
106
107 // We should never attempt to decrement when at min value
108 `ASSERT(BufferDecrUnderRun_A, en_i & fifo_rd_i |-> (curr_decr_cnt > '0))
109
110 // The total number of dependent buffers cannot never exceed the size of response queue
111 `ifdef INC_ASSERT
112 //VCS coverage off
113 // pragma coverage off
114 logic [31:0] assert_cnt;
115 always_comb begin
116 unreachable assert_cnt = '0;
117 unreachable for (int unsigned i = 0; i < NumBuf; i++) begin
118 unreachable assert_cnt = assert_cnt + dependency_o[i];
Cond Coverage for Module :
flash_phy_rd_buf_dep
| Total | Covered | Percent |
Conditions | 22 | 19 | 86.36 |
Logical | 22 | 19 | 86.36 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 65
EXPRESSION (en_i & fifo_wr_i & (curr_incr_cnt < flash_phy_pkg::RspOrderDepth))
--1- ----2---- -----------------------3----------------------
-1- | -2- | -3- | Status | Tests |
0 | 1 | 1 | Covered | T1,T2,T3 |
1 | 0 | 1 | Covered | T1,T2,T3 |
1 | 1 | 0 | Not Covered | |
1 | 1 | 1 | Covered | T2,T3,T4 |
LINE 66
EXPRESSION (en_i & fifo_rd_i & (curr_decr_cnt > '0))
--1- ----2---- ----------3---------
-1- | -2- | -3- | Status | Tests |
0 | 1 | 1 | Not Covered | |
1 | 0 | 1 | Covered | T2,T3,T4 |
1 | 1 | 0 | Not Covered | |
1 | 1 | 1 | Covered | T2,T3,T4 |
LINE 71
EXPRESSION ((incr_buf_sel == decr_buf_sel) ? (cnt_incr && ((!cnt_decr))) : cnt_incr)
---------------1--------------
-1- | Status | Tests |
0 | Covered | T2,T3,T4 |
1 | Covered | T1,T2,T3 |
LINE 71
SUB-EXPRESSION (incr_buf_sel == decr_buf_sel)
---------------1--------------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T2,T3 |
LINE 71
SUB-EXPRESSION (cnt_incr && ((!cnt_decr)))
----1--- ------2------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T3,T10,T32 |
1 | 1 | Covered | T2,T3,T4 |
LINE 72
EXPRESSION ((incr_buf_sel == decr_buf_sel) ? (((!cnt_incr)) && cnt_decr) : cnt_decr)
---------------1--------------
-1- | Status | Tests |
0 | Covered | T2,T3,T4 |
1 | Covered | T1,T2,T3 |
LINE 72
SUB-EXPRESSION (incr_buf_sel == decr_buf_sel)
---------------1--------------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T2,T3 |
LINE 72
SUB-EXPRESSION (((!cnt_incr)) && cnt_decr)
------1------ ----2---
-1- | -2- | Status | Tests |
0 | 1 | Covered | T3,T10,T32 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T2,T3,T4 |
Branch Coverage for Module :
flash_phy_rd_buf_dep
| Line No. | Total | Covered | Percent |
Branches |
|
13 |
13 |
100.00 |
TERNARY |
71 |
2 |
2 |
100.00 |
TERNARY |
72 |
2 |
2 |
100.00 |
IF |
51 |
2 |
2 |
100.00 |
IF |
54 |
2 |
2 |
100.00 |
IF |
76 |
5 |
5 |
100.00 |
71 assign fin_cnt_incr = (incr_buf_sel == decr_buf_sel) ? cnt_incr && !cnt_decr : cnt_incr;
-1-
==>
==>
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T2,T3 |
0 |
Covered |
T2,T3,T4 |
72 assign fin_cnt_decr = (incr_buf_sel == decr_buf_sel) ? !cnt_incr && cnt_decr : cnt_decr;
-1-
==>
==>
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T2,T3 |
0 |
Covered |
T2,T3,T4 |
51 if (wr_buf_i[i]) begin
-1-
52 incr_buf_sel = buf_mux_cnt[i];
==>
53 end
MISSING_ELSE
==>
Branches:
-1- | Status | Tests |
1 |
Covered |
T2,T3,T4 |
0 |
Covered |
T1,T2,T3 |
54 if (rd_buf_i[i]) begin
-1-
55 decr_buf_sel = buf_mux_cnt[i];
==>
56 end
MISSING_ELSE
==>
Branches:
-1- | Status | Tests |
1 |
Covered |
T2,T3,T4 |
0 |
Covered |
T1,T2,T3 |
76 if (!rst_ni) begin
-1-
77 buf_dependency_cnt <= '0;
==>
78 end else begin
79 if (fin_cnt_incr) begin
-2-
80 buf_dependency_cnt[incr_buf_sel] <= curr_incr_cnt + 1'b1;
==>
81 end
MISSING_ELSE
==>
82 if (fin_cnt_decr) begin
-3-
83 buf_dependency_cnt[decr_buf_sel] <= curr_decr_cnt - 1'b1;
==>
84 end
MISSING_ELSE
==>
Branches:
-1- | -2- | -3- | Status | Tests |
1 |
- |
- |
Covered |
T1,T2,T3 |
0 |
1 |
- |
Covered |
T2,T3,T4 |
0 |
0 |
- |
Covered |
T1,T2,T3 |
0 |
- |
1 |
Covered |
T2,T3,T4 |
0 |
- |
0 |
Covered |
T1,T2,T3 |
Assert Coverage for Module :
flash_phy_rd_buf_dep
Assertion Details
BufferDecrUnderRun_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
712171850 |
6502674 |
0 |
0 |
T2 |
2197 |
146 |
0 |
0 |
T3 |
28796 |
1244 |
0 |
0 |
T4 |
4568 |
20 |
0 |
0 |
T5 |
1934 |
0 |
0 |
0 |
T10 |
3216 |
10 |
0 |
0 |
T11 |
1440 |
8 |
0 |
0 |
T16 |
4298 |
0 |
0 |
0 |
T17 |
4150 |
146 |
0 |
0 |
T18 |
3104 |
146 |
0 |
0 |
T19 |
2348 |
0 |
0 |
0 |
T22 |
4000 |
0 |
0 |
0 |
T26 |
0 |
53 |
0 |
0 |
T32 |
0 |
365 |
0 |
0 |
T33 |
0 |
1052 |
0 |
0 |
T36 |
0 |
63 |
0 |
0 |
T37 |
0 |
85 |
0 |
0 |
T38 |
0 |
62 |
0 |
0 |
T49 |
0 |
500 |
0 |
0 |
BufferDepRsp_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
712171850 |
710510120 |
0 |
0 |
T1 |
7936 |
7760 |
0 |
0 |
T2 |
4394 |
4212 |
0 |
0 |
T3 |
28796 |
28622 |
0 |
0 |
T4 |
4568 |
4448 |
0 |
0 |
T5 |
1934 |
1742 |
0 |
0 |
T10 |
3216 |
3050 |
0 |
0 |
T16 |
4298 |
4118 |
0 |
0 |
T17 |
4150 |
3982 |
0 |
0 |
T18 |
3104 |
2980 |
0 |
0 |
T19 |
2348 |
2208 |
0 |
0 |
BufferIncrOverFlow_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
712171850 |
6502680 |
0 |
0 |
T2 |
2197 |
146 |
0 |
0 |
T3 |
28796 |
1244 |
0 |
0 |
T4 |
4568 |
20 |
0 |
0 |
T5 |
1934 |
0 |
0 |
0 |
T10 |
3216 |
10 |
0 |
0 |
T11 |
1440 |
8 |
0 |
0 |
T16 |
4298 |
0 |
0 |
0 |
T17 |
4150 |
146 |
0 |
0 |
T18 |
3104 |
146 |
0 |
0 |
T19 |
2348 |
0 |
0 |
0 |
T22 |
4000 |
0 |
0 |
0 |
T26 |
0 |
53 |
0 |
0 |
T32 |
0 |
365 |
0 |
0 |
T33 |
0 |
1052 |
0 |
0 |
T36 |
0 |
63 |
0 |
0 |
T37 |
0 |
85 |
0 |
0 |
T38 |
0 |
62 |
0 |
0 |
T49 |
0 |
500 |
0 |
0 |
DepBufferRspOrder_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
712171850 |
16173953 |
0 |
0 |
T1 |
3968 |
32 |
0 |
0 |
T2 |
2197 |
178 |
0 |
0 |
T3 |
28796 |
1276 |
0 |
0 |
T4 |
4568 |
52 |
0 |
0 |
T5 |
1934 |
32 |
0 |
0 |
T10 |
3216 |
42 |
0 |
0 |
T11 |
1440 |
3 |
0 |
0 |
T16 |
4298 |
32 |
0 |
0 |
T17 |
4150 |
178 |
0 |
0 |
T18 |
3104 |
178 |
0 |
0 |
T19 |
2348 |
32 |
0 |
0 |
T22 |
2000 |
0 |
0 |
0 |
T26 |
0 |
53 |
0 |
0 |
T32 |
0 |
260 |
0 |
0 |
T33 |
0 |
1052 |
0 |
0 |
T36 |
0 |
63 |
0 |
0 |
T37 |
0 |
15 |
0 |
0 |
T38 |
0 |
6 |
0 |
0 |
T49 |
0 |
200 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_rd.u_rd_buf_dep
| Line No. | Total | Covered | Percent |
TOTAL | | 23 | 23 | 100.00 |
ALWAYS | 48 | 7 | 7 | 100.00 |
CONT_ASSIGN | 61 | 1 | 1 | 100.00 |
CONT_ASSIGN | 62 | 1 | 1 | 100.00 |
CONT_ASSIGN | 65 | 1 | 1 | 100.00 |
CONT_ASSIGN | 66 | 1 | 1 | 100.00 |
CONT_ASSIGN | 71 | 1 | 1 | 100.00 |
CONT_ASSIGN | 72 | 1 | 1 | 100.00 |
ALWAYS | 76 | 6 | 6 | 100.00 |
ALWAYS | 90 | 3 | 3 | 100.00 |
CONT_ASSIGN | 97 | 1 | 1 | 100.00 |
ALWAYS | 116 | 0 | 0 | |
47 always_comb begin
48 1/1 incr_buf_sel = '0;
Tests: T1 T2 T3
49 1/1 decr_buf_sel = '0;
Tests: T1 T2 T3
50 1/1 for (int unsigned i = 0; i < NumBuf; i++) begin
Tests: T1 T2 T3
51 1/1 if (wr_buf_i[i]) begin
Tests: T1 T2 T3
52 1/1 incr_buf_sel = buf_mux_cnt[i];
Tests: T2 T3 T4
53 end
MISSING_ELSE
54 1/1 if (rd_buf_i[i]) begin
Tests: T1 T2 T3
55 1/1 decr_buf_sel = buf_mux_cnt[i];
Tests: T2 T3 T4
56 end
MISSING_ELSE
57 end
58 end // always_comb
59
60 logic [BufDepCntWidth-1:0] curr_incr_cnt, curr_decr_cnt;
61 1/1 assign curr_incr_cnt = buf_dependency_cnt[incr_buf_sel];
Tests: T1 T2 T3
62 1/1 assign curr_decr_cnt = buf_dependency_cnt[decr_buf_sel];
Tests: T1 T2 T3
63
64 logic cnt_incr, cnt_decr;
65 1/1 assign cnt_incr = en_i & fifo_wr_i & (curr_incr_cnt < RspOrderDepth);
Tests: T1 T2 T3
66 1/1 assign cnt_decr = en_i & fifo_rd_i & (curr_decr_cnt > '0);
Tests: T1 T2 T3
67
68 //assign cnt_decr = fifo_rd_i & (rsp_fifo_vld & data_valid_o) & (curr_decr_cnt > '0);
69
70 logic fin_cnt_incr, fin_cnt_decr;
71 1/1 assign fin_cnt_incr = (incr_buf_sel == decr_buf_sel) ? cnt_incr && !cnt_decr : cnt_incr;
Tests: T1 T2 T3
72 1/1 assign fin_cnt_decr = (incr_buf_sel == decr_buf_sel) ? !cnt_incr && cnt_decr : cnt_decr;
Tests: T1 T2 T3
73
74 // This tells us which buffer currently has a dependency to an item in the rsp_order_fifo
75 always_ff @(posedge clk_i or negedge rst_ni) begin
76 1/1 if (!rst_ni) begin
Tests: T1 T2 T3
77 1/1 buf_dependency_cnt <= '0;
Tests: T1 T2 T3
78 end else begin
79 1/1 if (fin_cnt_incr) begin
Tests: T1 T2 T3
80 1/1 buf_dependency_cnt[incr_buf_sel] <= curr_incr_cnt + 1'b1;
Tests: T2 T3 T4
81 end
MISSING_ELSE
82 1/1 if (fin_cnt_decr) begin
Tests: T1 T2 T3
83 1/1 buf_dependency_cnt[decr_buf_sel] <= curr_decr_cnt - 1'b1;
Tests: T2 T3 T4
84 end
MISSING_ELSE
85 end
86 end
87
88 // per buffer dependency determination
89 always_comb begin
90 1/1 dependency_o = '0;
Tests: T1 T2 T3
91 1/1 for (int i = 0; i < NumBuf; i++) begin
Tests: T1 T2 T3
92 1/1 dependency_o[i] = |buf_dependency_cnt[i];
Tests: T1 T2 T3
93 end
94 end
95
96 // all buffer entries currently have a dependency
97 1/1 assign all_dependency_o = &dependency_o;
Tests: T1 T2 T3
98
99
100 // If there are more buffers than there are number of response fifo entries, we an never have
101 // a fully dependent condition
102 `ASSERT(BufferDepRsp_A, NumBuf > RspOrderDepth |-> ~all_dependency_o)
103
104 // We should never attempt to increment when at max value
105 `ASSERT(BufferIncrOverFlow_A, en_i & fifo_wr_i |-> curr_incr_cnt < RspOrderDepth)
106
107 // We should never attempt to decrement when at min value
108 `ASSERT(BufferDecrUnderRun_A, en_i & fifo_rd_i |-> (curr_decr_cnt > '0))
109
110 // The total number of dependent buffers cannot never exceed the size of response queue
111 `ifdef INC_ASSERT
112 //VCS coverage off
113 // pragma coverage off
114 logic [31:0] assert_cnt;
115 always_comb begin
116 unreachable assert_cnt = '0;
117 unreachable for (int unsigned i = 0; i < NumBuf; i++) begin
118 unreachable assert_cnt = assert_cnt + dependency_o[i];
Cond Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_rd.u_rd_buf_dep
| Total | Covered | Percent |
Conditions | 22 | 19 | 86.36 |
Logical | 22 | 19 | 86.36 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 65
EXPRESSION (en_i & fifo_wr_i & (curr_incr_cnt < flash_phy_pkg::RspOrderDepth))
--1- ----2---- -----------------------3----------------------
-1- | -2- | -3- | Status | Tests |
0 | 1 | 1 | Covered | T1,T2,T3 |
1 | 0 | 1 | Covered | T1,T2,T3 |
1 | 1 | 0 | Not Covered | |
1 | 1 | 1 | Covered | T2,T3,T4 |
LINE 66
EXPRESSION (en_i & fifo_rd_i & (curr_decr_cnt > '0))
--1- ----2---- ----------3---------
-1- | -2- | -3- | Status | Tests |
0 | 1 | 1 | Not Covered | |
1 | 0 | 1 | Covered | T2,T3,T4 |
1 | 1 | 0 | Not Covered | |
1 | 1 | 1 | Covered | T2,T3,T4 |
LINE 71
EXPRESSION ((incr_buf_sel == decr_buf_sel) ? (cnt_incr && ((!cnt_decr))) : cnt_incr)
---------------1--------------
-1- | Status | Tests |
0 | Covered | T2,T3,T4 |
1 | Covered | T1,T2,T3 |
LINE 71
SUB-EXPRESSION (incr_buf_sel == decr_buf_sel)
---------------1--------------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T2,T3 |
LINE 71
SUB-EXPRESSION (cnt_incr && ((!cnt_decr)))
----1--- ------2------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T3,T10,T32 |
1 | 1 | Covered | T2,T3,T4 |
LINE 72
EXPRESSION ((incr_buf_sel == decr_buf_sel) ? (((!cnt_incr)) && cnt_decr) : cnt_decr)
---------------1--------------
-1- | Status | Tests |
0 | Covered | T2,T3,T4 |
1 | Covered | T1,T2,T3 |
LINE 72
SUB-EXPRESSION (incr_buf_sel == decr_buf_sel)
---------------1--------------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T2,T3 |
LINE 72
SUB-EXPRESSION (((!cnt_incr)) && cnt_decr)
------1------ ----2---
-1- | -2- | Status | Tests |
0 | 1 | Covered | T3,T10,T32 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T2,T3,T4 |
Branch Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_rd.u_rd_buf_dep
| Line No. | Total | Covered | Percent |
Branches |
|
13 |
13 |
100.00 |
TERNARY |
71 |
2 |
2 |
100.00 |
TERNARY |
72 |
2 |
2 |
100.00 |
IF |
51 |
2 |
2 |
100.00 |
IF |
54 |
2 |
2 |
100.00 |
IF |
76 |
5 |
5 |
100.00 |
71 assign fin_cnt_incr = (incr_buf_sel == decr_buf_sel) ? cnt_incr && !cnt_decr : cnt_incr;
-1-
==>
==>
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T2,T3 |
0 |
Covered |
T2,T3,T4 |
72 assign fin_cnt_decr = (incr_buf_sel == decr_buf_sel) ? !cnt_incr && cnt_decr : cnt_decr;
-1-
==>
==>
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T2,T3 |
0 |
Covered |
T2,T3,T4 |
51 if (wr_buf_i[i]) begin
-1-
52 incr_buf_sel = buf_mux_cnt[i];
==>
53 end
MISSING_ELSE
==>
Branches:
-1- | Status | Tests |
1 |
Covered |
T2,T3,T4 |
0 |
Covered |
T1,T2,T3 |
54 if (rd_buf_i[i]) begin
-1-
55 decr_buf_sel = buf_mux_cnt[i];
==>
56 end
MISSING_ELSE
==>
Branches:
-1- | Status | Tests |
1 |
Covered |
T2,T3,T4 |
0 |
Covered |
T1,T2,T3 |
76 if (!rst_ni) begin
-1-
77 buf_dependency_cnt <= '0;
==>
78 end else begin
79 if (fin_cnt_incr) begin
-2-
80 buf_dependency_cnt[incr_buf_sel] <= curr_incr_cnt + 1'b1;
==>
81 end
MISSING_ELSE
==>
82 if (fin_cnt_decr) begin
-3-
83 buf_dependency_cnt[decr_buf_sel] <= curr_decr_cnt - 1'b1;
==>
84 end
MISSING_ELSE
==>
Branches:
-1- | -2- | -3- | Status | Tests |
1 |
- |
- |
Covered |
T1,T2,T3 |
0 |
1 |
- |
Covered |
T2,T3,T4 |
0 |
0 |
- |
Covered |
T1,T2,T3 |
0 |
- |
1 |
Covered |
T2,T3,T4 |
0 |
- |
0 |
Covered |
T1,T2,T3 |
Assert Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_rd.u_rd_buf_dep
Assertion Details
BufferDecrUnderRun_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
356085925 |
3352986 |
0 |
0 |
T2 |
2197 |
146 |
0 |
0 |
T3 |
14398 |
695 |
0 |
0 |
T4 |
2284 |
20 |
0 |
0 |
T5 |
967 |
0 |
0 |
0 |
T10 |
1608 |
10 |
0 |
0 |
T11 |
0 |
5 |
0 |
0 |
T16 |
2149 |
0 |
0 |
0 |
T17 |
2075 |
0 |
0 |
0 |
T18 |
1552 |
146 |
0 |
0 |
T19 |
1174 |
0 |
0 |
0 |
T22 |
2000 |
0 |
0 |
0 |
T32 |
0 |
105 |
0 |
0 |
T37 |
0 |
70 |
0 |
0 |
T38 |
0 |
56 |
0 |
0 |
T49 |
0 |
300 |
0 |
0 |
BufferDepRsp_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
356085925 |
355255060 |
0 |
0 |
T1 |
3968 |
3880 |
0 |
0 |
T2 |
2197 |
2106 |
0 |
0 |
T3 |
14398 |
14311 |
0 |
0 |
T4 |
2284 |
2224 |
0 |
0 |
T5 |
967 |
871 |
0 |
0 |
T10 |
1608 |
1525 |
0 |
0 |
T16 |
2149 |
2059 |
0 |
0 |
T17 |
2075 |
1991 |
0 |
0 |
T18 |
1552 |
1490 |
0 |
0 |
T19 |
1174 |
1104 |
0 |
0 |
BufferIncrOverFlow_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
356085925 |
3352989 |
0 |
0 |
T2 |
2197 |
146 |
0 |
0 |
T3 |
14398 |
695 |
0 |
0 |
T4 |
2284 |
20 |
0 |
0 |
T5 |
967 |
0 |
0 |
0 |
T10 |
1608 |
10 |
0 |
0 |
T11 |
0 |
5 |
0 |
0 |
T16 |
2149 |
0 |
0 |
0 |
T17 |
2075 |
0 |
0 |
0 |
T18 |
1552 |
146 |
0 |
0 |
T19 |
1174 |
0 |
0 |
0 |
T22 |
2000 |
0 |
0 |
0 |
T32 |
0 |
105 |
0 |
0 |
T37 |
0 |
70 |
0 |
0 |
T38 |
0 |
56 |
0 |
0 |
T49 |
0 |
300 |
0 |
0 |
DepBufferRspOrder_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
356085925 |
8580600 |
0 |
0 |
T1 |
3968 |
32 |
0 |
0 |
T2 |
2197 |
178 |
0 |
0 |
T3 |
14398 |
727 |
0 |
0 |
T4 |
2284 |
52 |
0 |
0 |
T5 |
967 |
32 |
0 |
0 |
T10 |
1608 |
42 |
0 |
0 |
T16 |
2149 |
32 |
0 |
0 |
T17 |
2075 |
32 |
0 |
0 |
T18 |
1552 |
178 |
0 |
0 |
T19 |
1174 |
32 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_rd.u_rd_buf_dep
| Line No. | Total | Covered | Percent |
TOTAL | | 23 | 23 | 100.00 |
ALWAYS | 48 | 7 | 7 | 100.00 |
CONT_ASSIGN | 61 | 1 | 1 | 100.00 |
CONT_ASSIGN | 62 | 1 | 1 | 100.00 |
CONT_ASSIGN | 65 | 1 | 1 | 100.00 |
CONT_ASSIGN | 66 | 1 | 1 | 100.00 |
CONT_ASSIGN | 71 | 1 | 1 | 100.00 |
CONT_ASSIGN | 72 | 1 | 1 | 100.00 |
ALWAYS | 76 | 6 | 6 | 100.00 |
ALWAYS | 90 | 3 | 3 | 100.00 |
CONT_ASSIGN | 97 | 1 | 1 | 100.00 |
ALWAYS | 116 | 0 | 0 | |
47 always_comb begin
48 1/1 incr_buf_sel = '0;
Tests: T1 T2 T3
49 1/1 decr_buf_sel = '0;
Tests: T1 T2 T3
50 1/1 for (int unsigned i = 0; i < NumBuf; i++) begin
Tests: T1 T2 T3
51 1/1 if (wr_buf_i[i]) begin
Tests: T1 T2 T3
52 1/1 incr_buf_sel = buf_mux_cnt[i];
Tests: T3 T17 T11
53 end
MISSING_ELSE
54 1/1 if (rd_buf_i[i]) begin
Tests: T1 T2 T3
55 1/1 decr_buf_sel = buf_mux_cnt[i];
Tests: T3 T17 T11
56 end
MISSING_ELSE
57 end
58 end // always_comb
59
60 logic [BufDepCntWidth-1:0] curr_incr_cnt, curr_decr_cnt;
61 1/1 assign curr_incr_cnt = buf_dependency_cnt[incr_buf_sel];
Tests: T1 T2 T3
62 1/1 assign curr_decr_cnt = buf_dependency_cnt[decr_buf_sel];
Tests: T1 T2 T3
63
64 logic cnt_incr, cnt_decr;
65 1/1 assign cnt_incr = en_i & fifo_wr_i & (curr_incr_cnt < RspOrderDepth);
Tests: T1 T2 T3
66 1/1 assign cnt_decr = en_i & fifo_rd_i & (curr_decr_cnt > '0);
Tests: T1 T2 T3
67
68 //assign cnt_decr = fifo_rd_i & (rsp_fifo_vld & data_valid_o) & (curr_decr_cnt > '0);
69
70 logic fin_cnt_incr, fin_cnt_decr;
71 1/1 assign fin_cnt_incr = (incr_buf_sel == decr_buf_sel) ? cnt_incr && !cnt_decr : cnt_incr;
Tests: T1 T2 T3
72 1/1 assign fin_cnt_decr = (incr_buf_sel == decr_buf_sel) ? !cnt_incr && cnt_decr : cnt_decr;
Tests: T1 T2 T3
73
74 // This tells us which buffer currently has a dependency to an item in the rsp_order_fifo
75 always_ff @(posedge clk_i or negedge rst_ni) begin
76 1/1 if (!rst_ni) begin
Tests: T1 T2 T3
77 1/1 buf_dependency_cnt <= '0;
Tests: T1 T2 T3
78 end else begin
79 1/1 if (fin_cnt_incr) begin
Tests: T1 T2 T3
80 1/1 buf_dependency_cnt[incr_buf_sel] <= curr_incr_cnt + 1'b1;
Tests: T3 T17 T11
81 end
MISSING_ELSE
82 1/1 if (fin_cnt_decr) begin
Tests: T1 T2 T3
83 1/1 buf_dependency_cnt[decr_buf_sel] <= curr_decr_cnt - 1'b1;
Tests: T3 T17 T11
84 end
MISSING_ELSE
85 end
86 end
87
88 // per buffer dependency determination
89 always_comb begin
90 1/1 dependency_o = '0;
Tests: T1 T2 T3
91 1/1 for (int i = 0; i < NumBuf; i++) begin
Tests: T1 T2 T3
92 1/1 dependency_o[i] = |buf_dependency_cnt[i];
Tests: T1 T2 T3
93 end
94 end
95
96 // all buffer entries currently have a dependency
97 1/1 assign all_dependency_o = &dependency_o;
Tests: T1 T2 T3
98
99
100 // If there are more buffers than there are number of response fifo entries, we an never have
101 // a fully dependent condition
102 `ASSERT(BufferDepRsp_A, NumBuf > RspOrderDepth |-> ~all_dependency_o)
103
104 // We should never attempt to increment when at max value
105 `ASSERT(BufferIncrOverFlow_A, en_i & fifo_wr_i |-> curr_incr_cnt < RspOrderDepth)
106
107 // We should never attempt to decrement when at min value
108 `ASSERT(BufferDecrUnderRun_A, en_i & fifo_rd_i |-> (curr_decr_cnt > '0))
109
110 // The total number of dependent buffers cannot never exceed the size of response queue
111 `ifdef INC_ASSERT
112 //VCS coverage off
113 // pragma coverage off
114 logic [31:0] assert_cnt;
115 always_comb begin
116 unreachable assert_cnt = '0;
117 unreachable for (int unsigned i = 0; i < NumBuf; i++) begin
118 unreachable assert_cnt = assert_cnt + dependency_o[i];
Cond Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_rd.u_rd_buf_dep
| Total | Covered | Percent |
Conditions | 22 | 19 | 86.36 |
Logical | 22 | 19 | 86.36 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 65
EXPRESSION (en_i & fifo_wr_i & (curr_incr_cnt < flash_phy_pkg::RspOrderDepth))
--1- ----2---- -----------------------3----------------------
-1- | -2- | -3- | Status | Tests |
0 | 1 | 1 | Covered | T140,T135,T141 |
1 | 0 | 1 | Covered | T1,T2,T3 |
1 | 1 | 0 | Not Covered | |
1 | 1 | 1 | Covered | T3,T17,T11 |
LINE 66
EXPRESSION (en_i & fifo_rd_i & (curr_decr_cnt > '0))
--1- ----2---- ----------3---------
-1- | -2- | -3- | Status | Tests |
0 | 1 | 1 | Not Covered | |
1 | 0 | 1 | Covered | T3,T17,T11 |
1 | 1 | 0 | Not Covered | |
1 | 1 | 1 | Covered | T3,T17,T11 |
LINE 71
EXPRESSION ((incr_buf_sel == decr_buf_sel) ? (cnt_incr && ((!cnt_decr))) : cnt_incr)
---------------1--------------
-1- | Status | Tests |
0 | Covered | T3,T17,T11 |
1 | Covered | T1,T2,T3 |
LINE 71
SUB-EXPRESSION (incr_buf_sel == decr_buf_sel)
---------------1--------------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T2,T3 |
LINE 71
SUB-EXPRESSION (cnt_incr && ((!cnt_decr)))
----1--- ------2------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T3,T32,T49 |
1 | 1 | Covered | T3,T17,T11 |
LINE 72
EXPRESSION ((incr_buf_sel == decr_buf_sel) ? (((!cnt_incr)) && cnt_decr) : cnt_decr)
---------------1--------------
-1- | Status | Tests |
0 | Covered | T3,T17,T11 |
1 | Covered | T1,T2,T3 |
LINE 72
SUB-EXPRESSION (incr_buf_sel == decr_buf_sel)
---------------1--------------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T2,T3 |
LINE 72
SUB-EXPRESSION (((!cnt_incr)) && cnt_decr)
------1------ ----2---
-1- | -2- | Status | Tests |
0 | 1 | Covered | T3,T32,T49 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T3,T17,T11 |
Branch Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_rd.u_rd_buf_dep
| Line No. | Total | Covered | Percent |
Branches |
|
13 |
13 |
100.00 |
TERNARY |
71 |
2 |
2 |
100.00 |
TERNARY |
72 |
2 |
2 |
100.00 |
IF |
51 |
2 |
2 |
100.00 |
IF |
54 |
2 |
2 |
100.00 |
IF |
76 |
5 |
5 |
100.00 |
71 assign fin_cnt_incr = (incr_buf_sel == decr_buf_sel) ? cnt_incr && !cnt_decr : cnt_incr;
-1-
==>
==>
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T2,T3 |
0 |
Covered |
T3,T17,T11 |
72 assign fin_cnt_decr = (incr_buf_sel == decr_buf_sel) ? !cnt_incr && cnt_decr : cnt_decr;
-1-
==>
==>
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T2,T3 |
0 |
Covered |
T3,T17,T11 |
51 if (wr_buf_i[i]) begin
-1-
52 incr_buf_sel = buf_mux_cnt[i];
==>
53 end
MISSING_ELSE
==>
Branches:
-1- | Status | Tests |
1 |
Covered |
T3,T17,T11 |
0 |
Covered |
T1,T2,T3 |
54 if (rd_buf_i[i]) begin
-1-
55 decr_buf_sel = buf_mux_cnt[i];
==>
56 end
MISSING_ELSE
==>
Branches:
-1- | Status | Tests |
1 |
Covered |
T3,T17,T11 |
0 |
Covered |
T1,T2,T3 |
76 if (!rst_ni) begin
-1-
77 buf_dependency_cnt <= '0;
==>
78 end else begin
79 if (fin_cnt_incr) begin
-2-
80 buf_dependency_cnt[incr_buf_sel] <= curr_incr_cnt + 1'b1;
==>
81 end
MISSING_ELSE
==>
82 if (fin_cnt_decr) begin
-3-
83 buf_dependency_cnt[decr_buf_sel] <= curr_decr_cnt - 1'b1;
==>
84 end
MISSING_ELSE
==>
Branches:
-1- | -2- | -3- | Status | Tests |
1 |
- |
- |
Covered |
T1,T2,T3 |
0 |
1 |
- |
Covered |
T3,T17,T11 |
0 |
0 |
- |
Covered |
T1,T2,T3 |
0 |
- |
1 |
Covered |
T3,T17,T11 |
0 |
- |
0 |
Covered |
T1,T2,T3 |
Assert Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_rd.u_rd_buf_dep
Assertion Details
BufferDecrUnderRun_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
356085925 |
3149688 |
0 |
0 |
T3 |
14398 |
549 |
0 |
0 |
T4 |
2284 |
0 |
0 |
0 |
T5 |
967 |
0 |
0 |
0 |
T10 |
1608 |
0 |
0 |
0 |
T11 |
1440 |
3 |
0 |
0 |
T16 |
2149 |
0 |
0 |
0 |
T17 |
2075 |
146 |
0 |
0 |
T18 |
1552 |
0 |
0 |
0 |
T19 |
1174 |
0 |
0 |
0 |
T22 |
2000 |
0 |
0 |
0 |
T26 |
0 |
53 |
0 |
0 |
T32 |
0 |
260 |
0 |
0 |
T33 |
0 |
1052 |
0 |
0 |
T36 |
0 |
63 |
0 |
0 |
T37 |
0 |
15 |
0 |
0 |
T38 |
0 |
6 |
0 |
0 |
T49 |
0 |
200 |
0 |
0 |
BufferDepRsp_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
356085925 |
355255060 |
0 |
0 |
T1 |
3968 |
3880 |
0 |
0 |
T2 |
2197 |
2106 |
0 |
0 |
T3 |
14398 |
14311 |
0 |
0 |
T4 |
2284 |
2224 |
0 |
0 |
T5 |
967 |
871 |
0 |
0 |
T10 |
1608 |
1525 |
0 |
0 |
T16 |
2149 |
2059 |
0 |
0 |
T17 |
2075 |
1991 |
0 |
0 |
T18 |
1552 |
1490 |
0 |
0 |
T19 |
1174 |
1104 |
0 |
0 |
BufferIncrOverFlow_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
356085925 |
3149691 |
0 |
0 |
T3 |
14398 |
549 |
0 |
0 |
T4 |
2284 |
0 |
0 |
0 |
T5 |
967 |
0 |
0 |
0 |
T10 |
1608 |
0 |
0 |
0 |
T11 |
1440 |
3 |
0 |
0 |
T16 |
2149 |
0 |
0 |
0 |
T17 |
2075 |
146 |
0 |
0 |
T18 |
1552 |
0 |
0 |
0 |
T19 |
1174 |
0 |
0 |
0 |
T22 |
2000 |
0 |
0 |
0 |
T26 |
0 |
53 |
0 |
0 |
T32 |
0 |
260 |
0 |
0 |
T33 |
0 |
1052 |
0 |
0 |
T36 |
0 |
63 |
0 |
0 |
T37 |
0 |
15 |
0 |
0 |
T38 |
0 |
6 |
0 |
0 |
T49 |
0 |
200 |
0 |
0 |
DepBufferRspOrder_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
356085925 |
7593353 |
0 |
0 |
T3 |
14398 |
549 |
0 |
0 |
T4 |
2284 |
0 |
0 |
0 |
T5 |
967 |
0 |
0 |
0 |
T10 |
1608 |
0 |
0 |
0 |
T11 |
1440 |
3 |
0 |
0 |
T16 |
2149 |
0 |
0 |
0 |
T17 |
2075 |
146 |
0 |
0 |
T18 |
1552 |
0 |
0 |
0 |
T19 |
1174 |
0 |
0 |
0 |
T22 |
2000 |
0 |
0 |
0 |
T26 |
0 |
53 |
0 |
0 |
T32 |
0 |
260 |
0 |
0 |
T33 |
0 |
1052 |
0 |
0 |
T36 |
0 |
63 |
0 |
0 |
T37 |
0 |
15 |
0 |
0 |
T38 |
0 |
6 |
0 |
0 |
T49 |
0 |
200 |
0 |
0 |