Unified Coverage Report :: Module :: prim_arbiter_fixed

Module : prim_arbiter_fixed

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.88	87.50	100.00			100.00	100.00

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_eflash.gen_flash_cores[0].u_core.u_host_arb.gen_input_bufs[0].gen_fixed_arbiter.u_arb	96.88	87.50	100.00			100.00	100.00
tb.dut.u_eflash.gen_flash_cores[0].u_core.u_host_arb.gen_input_bufs[1].gen_fixed_arbiter.u_arb	96.88	87.50	100.00			100.00	100.00
tb.dut.u_eflash.gen_flash_cores[1].u_core.u_host_arb.gen_input_bufs[0].gen_fixed_arbiter.u_arb	96.88	87.50	100.00			100.00	100.00
tb.dut.u_eflash.gen_flash_cores[1].u_core.u_host_arb.gen_input_bufs[1].gen_fixed_arbiter.u_arb	96.88	87.50	100.00			100.00	100.00

---

Module Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_host_arb.gen_input_bufs[0].gen_fixed_arbiter.u_arb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.88	87.50	100.00			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.88	87.50	100.00			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
76.67	90.00	40.00			100.00		u_host_arb

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_host_arb.gen_input_bufs[1].gen_fixed_arbiter.u_arb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.88	87.50	100.00			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.88	87.50	100.00			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
76.67	90.00	40.00			100.00		u_host_arb

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_host_arb.gen_input_bufs[0].gen_fixed_arbiter.u_arb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.88	87.50	100.00			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.88	87.50	100.00			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.67	90.00	100.00			100.00		u_host_arb

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_host_arb.gen_input_bufs[1].gen_fixed_arbiter.u_arb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.88	87.50	100.00			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.88	87.50	100.00			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.67	90.00	100.00			100.00		u_host_arb

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Module : prim_arbiter_fixed

	Line No.	Total	Covered	Percent
TOTAL		16	14	87.50
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	87	1	0	0.00
CONT_ASSIGN	87	1	0	0.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	89	1	1	100.00
ALWAYS	105	6	6	100.00
CONT_ASSIGN	124	1	1	100.00
CONT_ASSIGN	128	1	1	100.00
CONT_ASSIGN	129	1	1	100.00
CONT_ASSIGN	132	1	1	100.00

84                                  // forward path
85         2/2                      assign req_tree[Pa]      = req_i[offset];
           Tests:       T2 T3 T4  | T1 T2 T3 
86                                  assign idx_tree[Pa]      = offset;
87         0/2     ==>              assign data_tree[Pa]     = data_i[offset];
88                                  // backward (grant) path
89         2/2                      assign gnt_o[offset]     = gnt_tree[Pa];
           Tests:       T2 T3 T4  | T1 T2 T3 
90                      
91                                end else begin : gen_tie_off
92                                  // forward path
93                                  assign req_tree[Pa]  = '0;
94                                  assign idx_tree[Pa]  = '0;
95                                  assign data_tree[Pa] = '0;
96                                  logic unused_sigs;
97                                  assign unused_sigs = gnt_tree[Pa];
98                                end
99                              // this creates the node assignments
100                             end else begin : gen_nodes
101                               // forward path
102                               logic sel; // local helper variable
103                               always_comb begin : p_node
104                                 // this always gives priority to the left child
105        1/1                      sel = ~req_tree[C0];
           Tests:       T1 T2 T3 
106                                 // propagate requests
107        1/1                      req_tree[Pa]  = req_tree[C0] | req_tree[C1];
           Tests:       T1 T2 T3 
108                                 // data and index muxes
109        1/1                      idx_tree[Pa]  = (sel) ? idx_tree[C1]  : idx_tree[C0];
           Tests:       T1 T2 T3 
110        1/1                      data_tree[Pa] = (sel) ? data_tree[C1] : data_tree[C0];
           Tests:       T1 T2 T3 
111                                 // propagate the grants back to the input
112        1/1                      gnt_tree[C0] = gnt_tree[Pa] & ~sel;
           Tests:       T1 T2 T3 
113        1/1                      gnt_tree[C1] = gnt_tree[Pa] &  sel;
           Tests:       T1 T2 T3 
114                               end
115                             end
116                           end : gen_level
117                         end : gen_tree
118                     
119                         // the results can be found at the tree root
120                         if (EnDataPort) begin : gen_data_port
121                           assign data_o      = data_tree[0];
122                         end else begin : gen_no_dataport
123                           logic [DW-1:0] unused_data;
124        1/1                assign unused_data = data_tree[0];
           Tests:       T2 T3 T4 
125                           assign data_o = '1;
126                         end
127                     
128        1/1              assign idx_o       = idx_tree[0];
           Tests:       T2 T3 T4 
129        1/1              assign valid_o     = req_tree[0];
           Tests:       T1 T2 T3 
130                     
131                         // this propagates a grant back to the input
132        1/1              assign gnt_tree[0] = valid_o & ready_i;
           Tests:       T1 T2 T3 

---

Cond Coverage for Module : prim_arbiter_fixed

	Total	Covered	Percent
Conditions	16	16	100.00
Logical	16	16	100.00
Non-Logical	0	0
Event	0	0

 LINE       107
 EXPRESSION (gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C0] | gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C1])
             ----------------------------------1----------------------------------   ----------------------------------2----------------------------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T3,T10,T11

 LINE       109
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])

-1-	Status	Tests
0	Covered	T3,T10,T11
1	Covered	T1,T2,T3

 LINE       110
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])

-1-	Status	Tests
0	Covered	T3,T10,T11
1	Covered	T1,T2,T3

 LINE       112
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & ((~gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)))
             ----------------------------------1----------------------------------   -----------------------------2-----------------------------

-1-	-2-	Status	Tests
0	1	Covered	T11,T12,T32
1	0	Covered	T1,T2,T3
1	1	Covered	T3,T10,T11

 LINE       113
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)
             ----------------------------------1----------------------------------   ---------------------------2--------------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T3,T10,T11
1	1	Covered	T1,T2,T3

 LINE       132
 EXPRESSION (valid_o & ready_i)
             ---1---   ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T11,T12,T32
1	1	Covered	T1,T2,T3

---

Branch Coverage for Module : prim_arbiter_fixed

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
TERNARY	109	2	2	100.00
TERNARY	110	2	2	100.00

109                    idx_tree[Pa]  = (sel) ? idx_tree[C1]  : idx_tree[C0];
                                             -1-  
                                             ==>  
                                             ==>  

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T3,T10,T11

110                    data_tree[Pa] = (sel) ? data_tree[C1] : data_tree[C0];
                                             -1-  
                                             ==>  
                                             ==>  

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T3,T10,T11

---

Assert Coverage for Module : prim_arbiter_fixed

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	13	13	100.00	13	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	13	13	100.00	13	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	1424343700	1421020240	0	0
CheckNGreaterZero_A	4188	4188	0	0
GntImpliesReady_A	1424343700	386001402	0	0
GntImpliesValid_A	1424343700	386001402	0	0
GrantKnown_A	1424343700	1421020240	0	0
IdxKnown_A	1424343700	1421020240	0	0
IndexIsCorrect_A	1424343700	386001402	0	0
NoReadyValidNoGrant_A	1424343700	168625487	0	0
Priority_A	1424343700	409726991	0	0
ReadyAndValidImplyGrant_A	1424343700	386001402	0	0
ReqAndReadyImplyGrant_A	1424343700	386001402	0	0
ReqImpliesValid_A	1424343700	409726991	0	0
ValidKnown_A	1424343700	1421020240	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1424343700	1421020240	0	0
T1	15872	15520	0	0
T2	8788	8424	0	0
T3	57592	57244	0	0
T4	9136	8896	0	0
T5	3868	3484	0	0
T10	6432	6100	0	0
T16	8596	8236	0	0
T17	8300	7964	0	0
T18	6208	5960	0	0
T19	4696	4416	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	4188	4188	0	0
T1	4	4	0	0
T2	4	4	0	0
T3	4	4	0	0
T4	4	4	0	0
T5	4	4	0	0
T10	4	4	0	0
T16	4	4	0	0
T17	4	4	0	0
T18	4	4	0	0
T19	4	4	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1424343700	386001402	0	0
T1	7936	4444	0	0
T2	4394	356	0	0
T3	57592	2552	0	0
T4	9136	1110	0	0
T5	3868	304	0	0
T8	0	32	0	0
T10	6432	84	0	0
T11	2880	6	0	0
T16	8596	64	0	0
T17	8300	356	0	0
T18	6208	356	0	0
T19	4696	64	0	0
T22	4000	0	0	0
T26	0	2186	0	0
T31	0	888	0	0
T32	0	2000	0	0
T37	0	30	0	0
T38	0	12	0	0
T49	0	400	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1424343700	386001402	0	0
T1	7936	4444	0	0
T2	4394	356	0	0
T3	57592	2552	0	0
T4	9136	1110	0	0
T5	3868	304	0	0
T8	0	32	0	0
T10	6432	84	0	0
T11	2880	6	0	0
T16	8596	64	0	0
T17	8300	356	0	0
T18	6208	356	0	0
T19	4696	64	0	0
T22	4000	0	0	0
T26	0	2186	0	0
T31	0	888	0	0
T32	0	2000	0	0
T37	0	30	0	0
T38	0	12	0	0
T49	0	400	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1424343700	1421020240	0	0
T1	15872	15520	0	0
T2	8788	8424	0	0
T3	57592	57244	0	0
T4	9136	8896	0	0
T5	3868	3484	0	0
T10	6432	6100	0	0
T16	8596	8236	0	0
T17	8300	7964	0	0
T18	6208	5960	0	0
T19	4696	4416	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1424343700	1421020240	0	0
T1	15872	15520	0	0
T2	8788	8424	0	0
T3	57592	57244	0	0
T4	9136	8896	0	0
T5	3868	3484	0	0
T10	6432	6100	0	0
T16	8596	8236	0	0
T17	8300	7964	0	0
T18	6208	5960	0	0
T19	4696	4416	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1424343700	386001402	0	0
T1	7936	4444	0	0
T2	4394	356	0	0
T3	57592	2552	0	0
T4	9136	1110	0	0
T5	3868	304	0	0
T8	0	32	0	0
T10	6432	84	0	0
T11	2880	6	0	0
T16	8596	64	0	0
T17	8300	356	0	0
T18	6208	356	0	0
T19	4696	64	0	0
T22	4000	0	0	0
T26	0	2186	0	0
T31	0	888	0	0
T32	0	2000	0	0
T37	0	30	0	0
T38	0	12	0	0
T49	0	400	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1424343700	168625487	0	0
T1	7936	256	0	0
T2	4394	656	0	0
T3	57592	3940	0	0
T4	9136	316	0	0
T5	3868	256	0	0
T10	6432	286	0	0
T11	2880	12	0	0
T16	8596	256	0	0
T17	8300	986	0	0
T18	6208	694	0	0
T19	4696	256	0	0
T22	4000	0	0	0
T26	0	188	0	0
T32	0	984	0	0
T33	0	3156	0	0
T36	0	116	0	0
T37	0	78	0	0
T38	0	20	0	0
T49	0	904	0	0

Priority_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1424343700	409726991	0	0
T1	7936	4444	0	0
T2	4394	356	0	0
T3	57592	2552	0	0
T4	9136	1110	0	0
T5	3868	304	0	0
T8	0	32	0	0
T10	6432	84	0	0
T11	2880	6	0	0
T16	8596	64	0	0
T17	8300	356	0	0
T18	6208	356	0	0
T19	4696	64	0	0
T22	4000	0	0	0
T26	0	2186	0	0
T31	0	888	0	0
T32	0	2408	0	0
T37	0	30	0	0
T38	0	12	0	0
T49	0	400	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1424343700	386001402	0	0
T1	7936	4444	0	0
T2	4394	356	0	0
T3	57592	2552	0	0
T4	9136	1110	0	0
T5	3868	304	0	0
T8	0	32	0	0
T10	6432	84	0	0
T11	2880	6	0	0
T16	8596	64	0	0
T17	8300	356	0	0
T18	6208	356	0	0
T19	4696	64	0	0
T22	4000	0	0	0
T26	0	2186	0	0
T31	0	888	0	0
T32	0	2000	0	0
T37	0	30	0	0
T38	0	12	0	0
T49	0	400	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1424343700	386001402	0	0
T1	7936	4444	0	0
T2	4394	356	0	0
T3	57592	2552	0	0
T4	9136	1110	0	0
T5	3868	304	0	0
T8	0	32	0	0
T10	6432	84	0	0
T11	2880	6	0	0
T16	8596	64	0	0
T17	8300	356	0	0
T18	6208	356	0	0
T19	4696	64	0	0
T22	4000	0	0	0
T26	0	2186	0	0
T31	0	888	0	0
T32	0	2000	0	0
T37	0	30	0	0
T38	0	12	0	0
T49	0	400	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1424343700	409726991	0	0
T1	7936	4444	0	0
T2	4394	356	0	0
T3	57592	2552	0	0
T4	9136	1110	0	0
T5	3868	304	0	0
T8	0	32	0	0
T10	6432	84	0	0
T11	2880	6	0	0
T16	8596	64	0	0
T17	8300	356	0	0
T18	6208	356	0	0
T19	4696	64	0	0
T22	4000	0	0	0
T26	0	2186	0	0
T31	0	888	0	0
T32	0	2408	0	0
T37	0	30	0	0
T38	0	12	0	0
T49	0	400	0	0

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1424343700	1421020240	0	0
T1	15872	15520	0	0
T2	8788	8424	0	0
T3	57592	57244	0	0
T4	9136	8896	0	0
T5	3868	3484	0	0
T10	6432	6100	0	0
T16	8596	8236	0	0
T17	8300	7964	0	0
T18	6208	5960	0	0
T19	4696	4416	0	0

Line Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_host_arb.gen_input_bufs[0].gen_fixed_arbiter.u_arb

	Line No.	Total	Covered	Percent
TOTAL		16	14	87.50
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	87	1	0	0.00
CONT_ASSIGN	87	1	0	0.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	89	1	1	100.00
ALWAYS	105	6	6	100.00
CONT_ASSIGN	124	1	1	100.00
CONT_ASSIGN	128	1	1	100.00
CONT_ASSIGN	129	1	1	100.00
CONT_ASSIGN	132	1	1	100.00

84                                  // forward path
85         2/2                      assign req_tree[Pa]      = req_i[offset];
           Tests:       T2 T3 T4  | T1 T2 T3 
86                                  assign idx_tree[Pa]      = offset;
87         0/2     ==>              assign data_tree[Pa]     = data_i[offset];
88                                  // backward (grant) path
89         2/2                      assign gnt_o[offset]     = gnt_tree[Pa];
           Tests:       T2 T3 T4  | T1 T2 T3 
90                      
91                                end else begin : gen_tie_off
92                                  // forward path
93                                  assign req_tree[Pa]  = '0;
94                                  assign idx_tree[Pa]  = '0;
95                                  assign data_tree[Pa] = '0;
96                                  logic unused_sigs;
97                                  assign unused_sigs = gnt_tree[Pa];
98                                end
99                              // this creates the node assignments
100                             end else begin : gen_nodes
101                               // forward path
102                               logic sel; // local helper variable
103                               always_comb begin : p_node
104                                 // this always gives priority to the left child
105        1/1                      sel = ~req_tree[C0];
           Tests:       T1 T2 T3 
106                                 // propagate requests
107        1/1                      req_tree[Pa]  = req_tree[C0] | req_tree[C1];
           Tests:       T1 T2 T3 
108                                 // data and index muxes
109        1/1                      idx_tree[Pa]  = (sel) ? idx_tree[C1]  : idx_tree[C0];
           Tests:       T1 T2 T3 
110        1/1                      data_tree[Pa] = (sel) ? data_tree[C1] : data_tree[C0];
           Tests:       T1 T2 T3 
111                                 // propagate the grants back to the input
112        1/1                      gnt_tree[C0] = gnt_tree[Pa] & ~sel;
           Tests:       T1 T2 T3 
113        1/1                      gnt_tree[C1] = gnt_tree[Pa] &  sel;
           Tests:       T1 T2 T3 
114                               end
115                             end
116                           end : gen_level
117                         end : gen_tree
118                     
119                         // the results can be found at the tree root
120                         if (EnDataPort) begin : gen_data_port
121                           assign data_o      = data_tree[0];
122                         end else begin : gen_no_dataport
123                           logic [DW-1:0] unused_data;
124        1/1                assign unused_data = data_tree[0];
           Tests:       T2 T3 T4 
125                           assign data_o = '1;
126                         end
127                     
128        1/1              assign idx_o       = idx_tree[0];
           Tests:       T2 T3 T4 
129        1/1              assign valid_o     = req_tree[0];
           Tests:       T1 T2 T3 
130                     
131                         // this propagates a grant back to the input
132        1/1              assign gnt_tree[0] = valid_o & ready_i;
           Tests:       T1 T2 T3 

---

Cond Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_host_arb.gen_input_bufs[0].gen_fixed_arbiter.u_arb

	Total	Covered	Percent
Conditions	16	16	100.00
Logical	16	16	100.00
Non-Logical	0	0
Event	0	0

 LINE       107
 EXPRESSION (gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C0] | gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C1])
             ----------------------------------1----------------------------------   ----------------------------------2----------------------------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T3,T10,T11

 LINE       109
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])

-1-	Status	Tests
0	Covered	T3,T10,T11
1	Covered	T1,T2,T3

 LINE       110
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])

-1-	Status	Tests
0	Covered	T3,T10,T11
1	Covered	T1,T2,T3

 LINE       112
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & ((~gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)))
             ----------------------------------1----------------------------------   -----------------------------2-----------------------------

-1-	-2-	Status	Tests
0	1	Covered	T11,T12,T32
1	0	Covered	T1,T2,T3
1	1	Covered	T3,T10,T11

 LINE       113
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)
             ----------------------------------1----------------------------------   ---------------------------2--------------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T3,T10,T11
1	1	Covered	T1,T2,T3

 LINE       132
 EXPRESSION (valid_o & ready_i)
             ---1---   ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T11,T12,T32
1	1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_host_arb.gen_input_bufs[0].gen_fixed_arbiter.u_arb

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
TERNARY	109	2	2	100.00
TERNARY	110	2	2	100.00

109                    idx_tree[Pa]  = (sel) ? idx_tree[C1]  : idx_tree[C0];
                                             -1-  
                                             ==>  
                                             ==>  

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T3,T10,T11

110                    data_tree[Pa] = (sel) ? data_tree[C1] : data_tree[C0];
                                             -1-  
                                             ==>  
                                             ==>  

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T3,T10,T11

---

Assert Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_host_arb.gen_input_bufs[0].gen_fixed_arbiter.u_arb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	13	13	100.00	13	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	13	13	100.00	13	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	356085925	355255060	0	0
CheckNGreaterZero_A	1047	1047	0	0
GntImpliesReady_A	356085925	100815048	0	0
GntImpliesValid_A	356085925	100815048	0	0
GrantKnown_A	356085925	355255060	0	0
IdxKnown_A	356085925	355255060	0	0
IndexIsCorrect_A	356085925	100815048	0	0
NoReadyValidNoGrant_A	356085925	43913696	0	0
Priority_A	356085925	106878968	0	0
ReadyAndValidImplyGrant_A	356085925	100815048	0	0
ReqAndReadyImplyGrant_A	356085925	100815048	0	0
ReqImpliesValid_A	356085925	106878968	0	0
ValidKnown_A	356085925	355255060	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	356085925	355255060	0	0
T1	3968	3880	0	0
T2	2197	2106	0	0
T3	14398	14311	0	0
T4	2284	2224	0	0
T5	967	871	0	0
T10	1608	1525	0	0
T16	2149	2059	0	0
T17	2075	1991	0	0
T18	1552	1490	0	0
T19	1174	1104	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1047	1047	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T10	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	356085925	100815048	0	0
T1	3968	2222	0	0
T2	2197	178	0	0
T3	14398	727	0	0
T4	2284	555	0	0
T5	967	152	0	0
T10	1608	42	0	0
T16	2149	32	0	0
T17	2075	32	0	0
T18	1552	178	0	0
T19	1174	32	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	356085925	100815048	0	0
T1	3968	2222	0	0
T2	2197	178	0	0
T3	14398	727	0	0
T4	2284	555	0	0
T5	967	152	0	0
T10	1608	42	0	0
T16	2149	32	0	0
T17	2075	32	0	0
T18	1552	178	0	0
T19	1174	32	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	356085925	355255060	0	0
T1	3968	3880	0	0
T2	2197	2106	0	0
T3	14398	14311	0	0
T4	2284	2224	0	0
T5	967	871	0	0
T10	1608	1525	0	0
T16	2149	2059	0	0
T17	2075	1991	0	0
T18	1552	1490	0	0
T19	1174	1104	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	356085925	355255060	0	0
T1	3968	3880	0	0
T2	2197	2106	0	0
T3	14398	14311	0	0
T4	2284	2224	0	0
T5	967	871	0	0
T10	1608	1525	0	0
T16	2149	2059	0	0
T17	2075	1991	0	0
T18	1552	1490	0	0
T19	1174	1104	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	356085925	100815048	0	0
T1	3968	2222	0	0
T2	2197	178	0	0
T3	14398	727	0	0
T4	2284	555	0	0
T5	967	152	0	0
T10	1608	42	0	0
T16	2149	32	0	0
T17	2075	32	0	0
T18	1552	178	0	0
T19	1174	32	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	356085925	43913696	0	0
T1	3968	128	0	0
T2	2197	328	0	0
T3	14398	1154	0	0
T4	2284	158	0	0
T5	967	128	0	0
T10	1608	143	0	0
T16	2149	128	0	0
T17	2075	128	0	0
T18	1552	347	0	0
T19	1174	128	0	0

Priority_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	356085925	106878968	0	0
T1	3968	2222	0	0
T2	2197	178	0	0
T3	14398	727	0	0
T4	2284	555	0	0
T5	967	152	0	0
T10	1608	42	0	0
T16	2149	32	0	0
T17	2075	32	0	0
T18	1552	178	0	0
T19	1174	32	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	356085925	100815048	0	0
T1	3968	2222	0	0
T2	2197	178	0	0
T3	14398	727	0	0
T4	2284	555	0	0
T5	967	152	0	0
T10	1608	42	0	0
T16	2149	32	0	0
T17	2075	32	0	0
T18	1552	178	0	0
T19	1174	32	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	356085925	100815048	0	0
T1	3968	2222	0	0
T2	2197	178	0	0
T3	14398	727	0	0
T4	2284	555	0	0
T5	967	152	0	0
T10	1608	42	0	0
T16	2149	32	0	0
T17	2075	32	0	0
T18	1552	178	0	0
T19	1174	32	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	356085925	106878968	0	0
T1	3968	2222	0	0
T2	2197	178	0	0
T3	14398	727	0	0
T4	2284	555	0	0
T5	967	152	0	0
T10	1608	42	0	0
T16	2149	32	0	0
T17	2075	32	0	0
T18	1552	178	0	0
T19	1174	32	0	0

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	356085925	355255060	0	0
T1	3968	3880	0	0
T2	2197	2106	0	0
T3	14398	14311	0	0
T4	2284	2224	0	0
T5	967	871	0	0
T10	1608	1525	0	0
T16	2149	2059	0	0
T17	2075	1991	0	0
T18	1552	1490	0	0
T19	1174	1104	0	0

Line Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_host_arb.gen_input_bufs[1].gen_fixed_arbiter.u_arb

	Line No.	Total	Covered	Percent
TOTAL		16	14	87.50
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	87	1	0	0.00
CONT_ASSIGN	87	1	0	0.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	89	1	1	100.00
ALWAYS	105	6	6	100.00
CONT_ASSIGN	124	1	1	100.00
CONT_ASSIGN	128	1	1	100.00
CONT_ASSIGN	129	1	1	100.00
CONT_ASSIGN	132	1	1	100.00

84                                  // forward path
85         2/2                      assign req_tree[Pa]      = req_i[offset];
           Tests:       T2 T3 T4  | T1 T2 T3 
86                                  assign idx_tree[Pa]      = offset;
87         0/2     ==>              assign data_tree[Pa]     = data_i[offset];
88                                  // backward (grant) path
89         2/2                      assign gnt_o[offset]     = gnt_tree[Pa];
           Tests:       T2 T3 T4  | T1 T2 T3 
90                      
91                                end else begin : gen_tie_off
92                                  // forward path
93                                  assign req_tree[Pa]  = '0;
94                                  assign idx_tree[Pa]  = '0;
95                                  assign data_tree[Pa] = '0;
96                                  logic unused_sigs;
97                                  assign unused_sigs = gnt_tree[Pa];
98                                end
99                              // this creates the node assignments
100                             end else begin : gen_nodes
101                               // forward path
102                               logic sel; // local helper variable
103                               always_comb begin : p_node
104                                 // this always gives priority to the left child
105        1/1                      sel = ~req_tree[C0];
           Tests:       T1 T2 T3 
106                                 // propagate requests
107        1/1                      req_tree[Pa]  = req_tree[C0] | req_tree[C1];
           Tests:       T1 T2 T3 
108                                 // data and index muxes
109        1/1                      idx_tree[Pa]  = (sel) ? idx_tree[C1]  : idx_tree[C0];
           Tests:       T1 T2 T3 
110        1/1                      data_tree[Pa] = (sel) ? data_tree[C1] : data_tree[C0];
           Tests:       T1 T2 T3 
111                                 // propagate the grants back to the input
112        1/1                      gnt_tree[C0] = gnt_tree[Pa] & ~sel;
           Tests:       T1 T2 T3 
113        1/1                      gnt_tree[C1] = gnt_tree[Pa] &  sel;
           Tests:       T1 T2 T3 
114                               end
115                             end
116                           end : gen_level
117                         end : gen_tree
118                     
119                         // the results can be found at the tree root
120                         if (EnDataPort) begin : gen_data_port
121                           assign data_o      = data_tree[0];
122                         end else begin : gen_no_dataport
123                           logic [DW-1:0] unused_data;
124        1/1                assign unused_data = data_tree[0];
           Tests:       T2 T3 T4 
125                           assign data_o = '1;
126                         end
127                     
128        1/1              assign idx_o       = idx_tree[0];
           Tests:       T2 T3 T4 
129        1/1              assign valid_o     = req_tree[0];
           Tests:       T1 T2 T3 
130                     
131                         // this propagates a grant back to the input
132        1/1              assign gnt_tree[0] = valid_o & ready_i;
           Tests:       T1 T2 T3 

---

Cond Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_host_arb.gen_input_bufs[1].gen_fixed_arbiter.u_arb

	Total	Covered	Percent
Conditions	16	16	100.00
Logical	16	16	100.00
Non-Logical	0	0
Event	0	0

 LINE       107
 EXPRESSION (gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C0] | gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C1])
             ----------------------------------1----------------------------------   ----------------------------------2----------------------------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T3,T10,T11

 LINE       109
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])

-1-	Status	Tests
0	Covered	T3,T10,T11
1	Covered	T1,T2,T3

 LINE       110
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])

-1-	Status	Tests
0	Covered	T3,T10,T11
1	Covered	T1,T2,T3

 LINE       112
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & ((~gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)))
             ----------------------------------1----------------------------------   -----------------------------2-----------------------------

-1-	-2-	Status	Tests
0	1	Covered	T11,T12,T32
1	0	Covered	T1,T2,T3
1	1	Covered	T3,T10,T11

 LINE       113
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)
             ----------------------------------1----------------------------------   ---------------------------2--------------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T3,T10,T11
1	1	Covered	T1,T2,T3

 LINE       132
 EXPRESSION (valid_o & ready_i)
             ---1---   ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T11,T12,T32
1	1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_host_arb.gen_input_bufs[1].gen_fixed_arbiter.u_arb

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
TERNARY	109	2	2	100.00
TERNARY	110	2	2	100.00

109                    idx_tree[Pa]  = (sel) ? idx_tree[C1]  : idx_tree[C0];
                                             -1-  
                                             ==>  
                                             ==>  

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T3,T10,T11

110                    data_tree[Pa] = (sel) ? data_tree[C1] : data_tree[C0];
                                             -1-  
                                             ==>  
                                             ==>  

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T3,T10,T11

---

Assert Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_host_arb.gen_input_bufs[1].gen_fixed_arbiter.u_arb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	13	13	100.00	13	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	13	13	100.00	13	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	356085925	355255060	0	0
CheckNGreaterZero_A	1047	1047	0	0
GntImpliesReady_A	356085925	100815048	0	0
GntImpliesValid_A	356085925	100815048	0	0
GrantKnown_A	356085925	355255060	0	0
IdxKnown_A	356085925	355255060	0	0
IndexIsCorrect_A	356085925	100815048	0	0
NoReadyValidNoGrant_A	356085925	43913696	0	0
Priority_A	356085925	106878968	0	0
ReadyAndValidImplyGrant_A	356085925	100815048	0	0
ReqAndReadyImplyGrant_A	356085925	100815048	0	0
ReqImpliesValid_A	356085925	106878968	0	0
ValidKnown_A	356085925	355255060	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	356085925	355255060	0	0
T1	3968	3880	0	0
T2	2197	2106	0	0
T3	14398	14311	0	0
T4	2284	2224	0	0
T5	967	871	0	0
T10	1608	1525	0	0
T16	2149	2059	0	0
T17	2075	1991	0	0
T18	1552	1490	0	0
T19	1174	1104	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1047	1047	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T10	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	356085925	100815048	0	0
T1	3968	2222	0	0
T2	2197	178	0	0
T3	14398	727	0	0
T4	2284	555	0	0
T5	967	152	0	0
T10	1608	42	0	0
T16	2149	32	0	0
T17	2075	32	0	0
T18	1552	178	0	0
T19	1174	32	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	356085925	100815048	0	0
T1	3968	2222	0	0
T2	2197	178	0	0
T3	14398	727	0	0
T4	2284	555	0	0
T5	967	152	0	0
T10	1608	42	0	0
T16	2149	32	0	0
T17	2075	32	0	0
T18	1552	178	0	0
T19	1174	32	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	356085925	355255060	0	0
T1	3968	3880	0	0
T2	2197	2106	0	0
T3	14398	14311	0	0
T4	2284	2224	0	0
T5	967	871	0	0
T10	1608	1525	0	0
T16	2149	2059	0	0
T17	2075	1991	0	0
T18	1552	1490	0	0
T19	1174	1104	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	356085925	355255060	0	0
T1	3968	3880	0	0
T2	2197	2106	0	0
T3	14398	14311	0	0
T4	2284	2224	0	0
T5	967	871	0	0
T10	1608	1525	0	0
T16	2149	2059	0	0
T17	2075	1991	0	0
T18	1552	1490	0	0
T19	1174	1104	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	356085925	100815048	0	0
T1	3968	2222	0	0
T2	2197	178	0	0
T3	14398	727	0	0
T4	2284	555	0	0
T5	967	152	0	0
T10	1608	42	0	0
T16	2149	32	0	0
T17	2075	32	0	0
T18	1552	178	0	0
T19	1174	32	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	356085925	43913696	0	0
T1	3968	128	0	0
T2	2197	328	0	0
T3	14398	1154	0	0
T4	2284	158	0	0
T5	967	128	0	0
T10	1608	143	0	0
T16	2149	128	0	0
T17	2075	128	0	0
T18	1552	347	0	0
T19	1174	128	0	0

Priority_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	356085925	106878968	0	0
T1	3968	2222	0	0
T2	2197	178	0	0
T3	14398	727	0	0
T4	2284	555	0	0
T5	967	152	0	0
T10	1608	42	0	0
T16	2149	32	0	0
T17	2075	32	0	0
T18	1552	178	0	0
T19	1174	32	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	356085925	100815048	0	0
T1	3968	2222	0	0
T2	2197	178	0	0
T3	14398	727	0	0
T4	2284	555	0	0
T5	967	152	0	0
T10	1608	42	0	0
T16	2149	32	0	0
T17	2075	32	0	0
T18	1552	178	0	0
T19	1174	32	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	356085925	100815048	0	0
T1	3968	2222	0	0
T2	2197	178	0	0
T3	14398	727	0	0
T4	2284	555	0	0
T5	967	152	0	0
T10	1608	42	0	0
T16	2149	32	0	0
T17	2075	32	0	0
T18	1552	178	0	0
T19	1174	32	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	356085925	106878968	0	0
T1	3968	2222	0	0
T2	2197	178	0	0
T3	14398	727	0	0
T4	2284	555	0	0
T5	967	152	0	0
T10	1608	42	0	0
T16	2149	32	0	0
T17	2075	32	0	0
T18	1552	178	0	0
T19	1174	32	0	0

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	356085925	355255060	0	0
T1	3968	3880	0	0
T2	2197	2106	0	0
T3	14398	14311	0	0
T4	2284	2224	0	0
T5	967	871	0	0
T10	1608	1525	0	0
T16	2149	2059	0	0
T17	2075	1991	0	0
T18	1552	1490	0	0
T19	1174	1104	0	0

Line Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_host_arb.gen_input_bufs[0].gen_fixed_arbiter.u_arb

	Line No.	Total	Covered	Percent
TOTAL		16	14	87.50
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	87	1	0	0.00
CONT_ASSIGN	87	1	0	0.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	89	1	1	100.00
ALWAYS	105	6	6	100.00
CONT_ASSIGN	124	1	1	100.00
CONT_ASSIGN	128	1	1	100.00
CONT_ASSIGN	129	1	1	100.00
CONT_ASSIGN	132	1	1	100.00

84                                  // forward path
85         2/2                      assign req_tree[Pa]      = req_i[offset];
           Tests:       T2 T3 T4  | T1 T2 T3 
86                                  assign idx_tree[Pa]      = offset;
87         0/2     ==>              assign data_tree[Pa]     = data_i[offset];
88                                  // backward (grant) path
89         2/2                      assign gnt_o[offset]     = gnt_tree[Pa];
           Tests:       T2 T3 T4  | T1 T2 T3 
90                      
91                                end else begin : gen_tie_off
92                                  // forward path
93                                  assign req_tree[Pa]  = '0;
94                                  assign idx_tree[Pa]  = '0;
95                                  assign data_tree[Pa] = '0;
96                                  logic unused_sigs;
97                                  assign unused_sigs = gnt_tree[Pa];
98                                end
99                              // this creates the node assignments
100                             end else begin : gen_nodes
101                               // forward path
102                               logic sel; // local helper variable
103                               always_comb begin : p_node
104                                 // this always gives priority to the left child
105        1/1                      sel = ~req_tree[C0];
           Tests:       T1 T2 T3 
106                                 // propagate requests
107        1/1                      req_tree[Pa]  = req_tree[C0] | req_tree[C1];
           Tests:       T1 T2 T3 
108                                 // data and index muxes
109        1/1                      idx_tree[Pa]  = (sel) ? idx_tree[C1]  : idx_tree[C0];
           Tests:       T1 T2 T3 
110        1/1                      data_tree[Pa] = (sel) ? data_tree[C1] : data_tree[C0];
           Tests:       T1 T2 T3 
111                                 // propagate the grants back to the input
112        1/1                      gnt_tree[C0] = gnt_tree[Pa] & ~sel;
           Tests:       T1 T2 T3 
113        1/1                      gnt_tree[C1] = gnt_tree[Pa] &  sel;
           Tests:       T1 T2 T3 
114                               end
115                             end
116                           end : gen_level
117                         end : gen_tree
118                     
119                         // the results can be found at the tree root
120                         if (EnDataPort) begin : gen_data_port
121                           assign data_o      = data_tree[0];
122                         end else begin : gen_no_dataport
123                           logic [DW-1:0] unused_data;
124        1/1                assign unused_data = data_tree[0];
           Tests:       T2 T3 T4 
125                           assign data_o = '1;
126                         end
127                     
128        1/1              assign idx_o       = idx_tree[0];
           Tests:       T2 T3 T4 
129        1/1              assign valid_o     = req_tree[0];
           Tests:       T1 T2 T3 
130                     
131                         // this propagates a grant back to the input
132        1/1              assign gnt_tree[0] = valid_o & ready_i;
           Tests:       T1 T2 T3 

---

Cond Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_host_arb.gen_input_bufs[0].gen_fixed_arbiter.u_arb

	Total	Covered	Percent
Conditions	16	16	100.00
Logical	16	16	100.00
Non-Logical	0	0
Event	0	0

 LINE       107
 EXPRESSION (gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C0] | gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C1])
             ----------------------------------1----------------------------------   ----------------------------------2----------------------------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T3,T17,T8
1	0	Covered	T3,T11,T12

 LINE       109
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])

-1-	Status	Tests
0	Covered	T3,T11,T12
1	Covered	T1,T2,T3

 LINE       110
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])

-1-	Status	Tests
0	Covered	T3,T11,T12
1	Covered	T1,T2,T3

 LINE       112
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & ((~gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)))
             ----------------------------------1----------------------------------   -----------------------------2-----------------------------

-1-	-2-	Status	Tests
0	1	Covered	T11,T12,T32
1	0	Covered	T3,T17,T8
1	1	Covered	T3,T11,T12

 LINE       113
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)
             ----------------------------------1----------------------------------   ---------------------------2--------------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T3,T11,T12
1	1	Covered	T3,T17,T8

 LINE       132
 EXPRESSION (valid_o & ready_i)
             ---1---   ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T11,T12,T32
1	1	Covered	T3,T17,T11

---

Branch Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_host_arb.gen_input_bufs[0].gen_fixed_arbiter.u_arb

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
TERNARY	109	2	2	100.00
TERNARY	110	2	2	100.00

109                    idx_tree[Pa]  = (sel) ? idx_tree[C1]  : idx_tree[C0];
                                             -1-  
                                             ==>  
                                             ==>  

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T3,T11,T12

110                    data_tree[Pa] = (sel) ? data_tree[C1] : data_tree[C0];
                                             -1-  
                                             ==>  
                                             ==>  

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T3,T11,T12

---

Assert Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_host_arb.gen_input_bufs[0].gen_fixed_arbiter.u_arb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	13	13	100.00	13	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	13	13	100.00	13	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	356085925	355255060	0	0
CheckNGreaterZero_A	1047	1047	0	0
GntImpliesReady_A	356085925	92185680	0	0
GntImpliesValid_A	356085925	92185680	0	0
GrantKnown_A	356085925	355255060	0	0
IdxKnown_A	356085925	355255060	0	0
IndexIsCorrect_A	356085925	92185680	0	0
NoReadyValidNoGrant_A	356085925	40399071	0	0
Priority_A	356085925	97984531	0	0
ReadyAndValidImplyGrant_A	356085925	92185680	0	0
ReqAndReadyImplyGrant_A	356085925	92185680	0	0
ReqImpliesValid_A	356085925	97984531	0	0
ValidKnown_A	356085925	355255060	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	356085925	355255060	0	0
T1	3968	3880	0	0
T2	2197	2106	0	0
T3	14398	14311	0	0
T4	2284	2224	0	0
T5	967	871	0	0
T10	1608	1525	0	0
T16	2149	2059	0	0
T17	2075	1991	0	0
T18	1552	1490	0	0
T19	1174	1104	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1047	1047	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T10	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	356085925	92185680	0	0
T3	14398	549	0	0
T4	2284	0	0	0
T5	967	0	0	0
T8	0	16	0	0
T10	1608	0	0	0
T11	1440	3	0	0
T16	2149	0	0	0
T17	2075	146	0	0
T18	1552	0	0	0
T19	1174	0	0	0
T22	2000	0	0	0
T26	0	1093	0	0
T31	0	444	0	0
T32	0	1035	0	0
T37	0	15	0	0
T38	0	6	0	0
T49	0	200	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	356085925	92185680	0	0
T3	14398	549	0	0
T4	2284	0	0	0
T5	967	0	0	0
T8	0	16	0	0
T10	1608	0	0	0
T11	1440	3	0	0
T16	2149	0	0	0
T17	2075	146	0	0
T18	1552	0	0	0
T19	1174	0	0	0
T22	2000	0	0	0
T26	0	1093	0	0
T31	0	444	0	0
T32	0	1035	0	0
T37	0	15	0	0
T38	0	6	0	0
T49	0	200	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	356085925	355255060	0	0
T1	3968	3880	0	0
T2	2197	2106	0	0
T3	14398	14311	0	0
T4	2284	2224	0	0
T5	967	871	0	0
T10	1608	1525	0	0
T16	2149	2059	0	0
T17	2075	1991	0	0
T18	1552	1490	0	0
T19	1174	1104	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	356085925	355255060	0	0
T1	3968	3880	0	0
T2	2197	2106	0	0
T3	14398	14311	0	0
T4	2284	2224	0	0
T5	967	871	0	0
T10	1608	1525	0	0
T16	2149	2059	0	0
T17	2075	1991	0	0
T18	1552	1490	0	0
T19	1174	1104	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	356085925	92185680	0	0
T3	14398	549	0	0
T4	2284	0	0	0
T5	967	0	0	0
T8	0	16	0	0
T10	1608	0	0	0
T11	1440	3	0	0
T16	2149	0	0	0
T17	2075	146	0	0
T18	1552	0	0	0
T19	1174	0	0	0
T22	2000	0	0	0
T26	0	1093	0	0
T31	0	444	0	0
T32	0	1035	0	0
T37	0	15	0	0
T38	0	6	0	0
T49	0	200	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	356085925	40399071	0	0
T3	14398	816	0	0
T4	2284	0	0	0
T5	967	0	0	0
T10	1608	0	0	0
T11	1440	6	0	0
T16	2149	0	0	0
T17	2075	365	0	0
T18	1552	0	0	0
T19	1174	0	0	0
T22	2000	0	0	0
T26	0	94	0	0
T32	0	491	0	0
T33	0	1578	0	0
T36	0	58	0	0
T37	0	39	0	0
T38	0	10	0	0
T49	0	452	0	0

Priority_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	356085925	97984531	0	0
T3	14398	549	0	0
T4	2284	0	0	0
T5	967	0	0	0
T8	0	16	0	0
T10	1608	0	0	0
T11	1440	3	0	0
T16	2149	0	0	0
T17	2075	146	0	0
T18	1552	0	0	0
T19	1174	0	0	0
T22	2000	0	0	0
T26	0	1093	0	0
T31	0	444	0	0
T32	0	1240	0	0
T37	0	15	0	0
T38	0	6	0	0
T49	0	200	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	356085925	92185680	0	0
T3	14398	549	0	0
T4	2284	0	0	0
T5	967	0	0	0
T8	0	16	0	0
T10	1608	0	0	0
T11	1440	3	0	0
T16	2149	0	0	0
T17	2075	146	0	0
T18	1552	0	0	0
T19	1174	0	0	0
T22	2000	0	0	0
T26	0	1093	0	0
T31	0	444	0	0
T32	0	1035	0	0
T37	0	15	0	0
T38	0	6	0	0
T49	0	200	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	356085925	92185680	0	0
T3	14398	549	0	0
T4	2284	0	0	0
T5	967	0	0	0
T8	0	16	0	0
T10	1608	0	0	0
T11	1440	3	0	0
T16	2149	0	0	0
T17	2075	146	0	0
T18	1552	0	0	0
T19	1174	0	0	0
T22	2000	0	0	0
T26	0	1093	0	0
T31	0	444	0	0
T32	0	1035	0	0
T37	0	15	0	0
T38	0	6	0	0
T49	0	200	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	356085925	97984531	0	0
T3	14398	549	0	0
T4	2284	0	0	0
T5	967	0	0	0
T8	0	16	0	0
T10	1608	0	0	0
T11	1440	3	0	0
T16	2149	0	0	0
T17	2075	146	0	0
T18	1552	0	0	0
T19	1174	0	0	0
T22	2000	0	0	0
T26	0	1093	0	0
T31	0	444	0	0
T32	0	1240	0	0
T37	0	15	0	0
T38	0	6	0	0
T49	0	200	0	0

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	356085925	355255060	0	0
T1	3968	3880	0	0
T2	2197	2106	0	0
T3	14398	14311	0	0
T4	2284	2224	0	0
T5	967	871	0	0
T10	1608	1525	0	0
T16	2149	2059	0	0
T17	2075	1991	0	0
T18	1552	1490	0	0
T19	1174	1104	0	0

Line Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_host_arb.gen_input_bufs[1].gen_fixed_arbiter.u_arb

	Line No.	Total	Covered	Percent
TOTAL		16	14	87.50
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	87	1	0	0.00
CONT_ASSIGN	87	1	0	0.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	89	1	1	100.00
ALWAYS	105	6	6	100.00
CONT_ASSIGN	124	1	1	100.00
CONT_ASSIGN	128	1	1	100.00
CONT_ASSIGN	129	1	1	100.00
CONT_ASSIGN	132	1	1	100.00

84                                  // forward path
85         2/2                      assign req_tree[Pa]      = req_i[offset];
           Tests:       T2 T3 T4  | T1 T2 T3 
86                                  assign idx_tree[Pa]      = offset;
87         0/2     ==>              assign data_tree[Pa]     = data_i[offset];
88                                  // backward (grant) path
89         2/2                      assign gnt_o[offset]     = gnt_tree[Pa];
           Tests:       T2 T3 T4  | T1 T2 T3 
90                      
91                                end else begin : gen_tie_off
92                                  // forward path
93                                  assign req_tree[Pa]  = '0;
94                                  assign idx_tree[Pa]  = '0;
95                                  assign data_tree[Pa] = '0;
96                                  logic unused_sigs;
97                                  assign unused_sigs = gnt_tree[Pa];
98                                end
99                              // this creates the node assignments
100                             end else begin : gen_nodes
101                               // forward path
102                               logic sel; // local helper variable
103                               always_comb begin : p_node
104                                 // this always gives priority to the left child
105        1/1                      sel = ~req_tree[C0];
           Tests:       T1 T2 T3 
106                                 // propagate requests
107        1/1                      req_tree[Pa]  = req_tree[C0] | req_tree[C1];
           Tests:       T1 T2 T3 
108                                 // data and index muxes
109        1/1                      idx_tree[Pa]  = (sel) ? idx_tree[C1]  : idx_tree[C0];
           Tests:       T1 T2 T3 
110        1/1                      data_tree[Pa] = (sel) ? data_tree[C1] : data_tree[C0];
           Tests:       T1 T2 T3 
111                                 // propagate the grants back to the input
112        1/1                      gnt_tree[C0] = gnt_tree[Pa] & ~sel;
           Tests:       T1 T2 T3 
113        1/1                      gnt_tree[C1] = gnt_tree[Pa] &  sel;
           Tests:       T1 T2 T3 
114                               end
115                             end
116                           end : gen_level
117                         end : gen_tree
118                     
119                         // the results can be found at the tree root
120                         if (EnDataPort) begin : gen_data_port
121                           assign data_o      = data_tree[0];
122                         end else begin : gen_no_dataport
123                           logic [DW-1:0] unused_data;
124        1/1                assign unused_data = data_tree[0];
           Tests:       T2 T3 T4 
125                           assign data_o = '1;
126                         end
127                     
128        1/1              assign idx_o       = idx_tree[0];
           Tests:       T2 T3 T4 
129        1/1              assign valid_o     = req_tree[0];
           Tests:       T1 T2 T3 
130                     
131                         // this propagates a grant back to the input
132        1/1              assign gnt_tree[0] = valid_o & ready_i;
           Tests:       T1 T2 T3 

---

Cond Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_host_arb.gen_input_bufs[1].gen_fixed_arbiter.u_arb

	Total	Covered	Percent
Conditions	16	16	100.00
Logical	16	16	100.00
Non-Logical	0	0
Event	0	0

 LINE       107
 EXPRESSION (gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C0] | gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C1])
             ----------------------------------1----------------------------------   ----------------------------------2----------------------------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T3,T17,T8
1	0	Covered	T3,T11,T12

 LINE       109
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])

-1-	Status	Tests
0	Covered	T3,T11,T12
1	Covered	T1,T2,T3

 LINE       110
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])

-1-	Status	Tests
0	Covered	T3,T11,T12
1	Covered	T1,T2,T3

 LINE       112
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & ((~gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)))
             ----------------------------------1----------------------------------   -----------------------------2-----------------------------

-1-	-2-	Status	Tests
0	1	Covered	T11,T12,T32
1	0	Covered	T3,T17,T8
1	1	Covered	T3,T11,T12

 LINE       113
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)
             ----------------------------------1----------------------------------   ---------------------------2--------------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T3,T11,T12
1	1	Covered	T3,T17,T8

 LINE       132
 EXPRESSION (valid_o & ready_i)
             ---1---   ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T11,T12,T32
1	1	Covered	T3,T17,T11

---

Branch Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_host_arb.gen_input_bufs[1].gen_fixed_arbiter.u_arb

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
TERNARY	109	2	2	100.00
TERNARY	110	2	2	100.00

109                    idx_tree[Pa]  = (sel) ? idx_tree[C1]  : idx_tree[C0];
                                             -1-  
                                             ==>  
                                             ==>  

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T3,T11,T12

110                    data_tree[Pa] = (sel) ? data_tree[C1] : data_tree[C0];
                                             -1-  
                                             ==>  
                                             ==>  

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T3,T11,T12

---

Assert Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_host_arb.gen_input_bufs[1].gen_fixed_arbiter.u_arb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	13	13	100.00	13	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	13	13	100.00	13	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	356085925	355255060	0	0
CheckNGreaterZero_A	1047	1047	0	0
GntImpliesReady_A	356085925	92185626	0	0
GntImpliesValid_A	356085925	92185626	0	0
GrantKnown_A	356085925	355255060	0	0
IdxKnown_A	356085925	355255060	0	0
IndexIsCorrect_A	356085925	92185626	0	0
NoReadyValidNoGrant_A	356085925	40399024	0	0
Priority_A	356085925	97984524	0	0
ReadyAndValidImplyGrant_A	356085925	92185626	0	0
ReqAndReadyImplyGrant_A	356085925	92185626	0	0
ReqImpliesValid_A	356085925	97984524	0	0
ValidKnown_A	356085925	355255060	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	356085925	355255060	0	0
T1	3968	3880	0	0
T2	2197	2106	0	0
T3	14398	14311	0	0
T4	2284	2224	0	0
T5	967	871	0	0
T10	1608	1525	0	0
T16	2149	2059	0	0
T17	2075	1991	0	0
T18	1552	1490	0	0
T19	1174	1104	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1047	1047	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T10	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	356085925	92185626	0	0
T3	14398	549	0	0
T4	2284	0	0	0
T5	967	0	0	0
T8	0	16	0	0
T10	1608	0	0	0
T11	1440	3	0	0
T16	2149	0	0	0
T17	2075	146	0	0
T18	1552	0	0	0
T19	1174	0	0	0
T22	2000	0	0	0
T26	0	1093	0	0
T31	0	444	0	0
T32	0	965	0	0
T37	0	15	0	0
T38	0	6	0	0
T49	0	200	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	356085925	92185626	0	0
T3	14398	549	0	0
T4	2284	0	0	0
T5	967	0	0	0
T8	0	16	0	0
T10	1608	0	0	0
T11	1440	3	0	0
T16	2149	0	0	0
T17	2075	146	0	0
T18	1552	0	0	0
T19	1174	0	0	0
T22	2000	0	0	0
T26	0	1093	0	0
T31	0	444	0	0
T32	0	965	0	0
T37	0	15	0	0
T38	0	6	0	0
T49	0	200	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	356085925	355255060	0	0
T1	3968	3880	0	0
T2	2197	2106	0	0
T3	14398	14311	0	0
T4	2284	2224	0	0
T5	967	871	0	0
T10	1608	1525	0	0
T16	2149	2059	0	0
T17	2075	1991	0	0
T18	1552	1490	0	0
T19	1174	1104	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	356085925	355255060	0	0
T1	3968	3880	0	0
T2	2197	2106	0	0
T3	14398	14311	0	0
T4	2284	2224	0	0
T5	967	871	0	0
T10	1608	1525	0	0
T16	2149	2059	0	0
T17	2075	1991	0	0
T18	1552	1490	0	0
T19	1174	1104	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	356085925	92185626	0	0
T3	14398	549	0	0
T4	2284	0	0	0
T5	967	0	0	0
T8	0	16	0	0
T10	1608	0	0	0
T11	1440	3	0	0
T16	2149	0	0	0
T17	2075	146	0	0
T18	1552	0	0	0
T19	1174	0	0	0
T22	2000	0	0	0
T26	0	1093	0	0
T31	0	444	0	0
T32	0	965	0	0
T37	0	15	0	0
T38	0	6	0	0
T49	0	200	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	356085925	40399024	0	0
T3	14398	816	0	0
T4	2284	0	0	0
T5	967	0	0	0
T10	1608	0	0	0
T11	1440	6	0	0
T16	2149	0	0	0
T17	2075	365	0	0
T18	1552	0	0	0
T19	1174	0	0	0
T22	2000	0	0	0
T26	0	94	0	0
T32	0	493	0	0
T33	0	1578	0	0
T36	0	58	0	0
T37	0	39	0	0
T38	0	10	0	0
T49	0	452	0	0

Priority_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	356085925	97984524	0	0
T3	14398	549	0	0
T4	2284	0	0	0
T5	967	0	0	0
T8	0	16	0	0
T10	1608	0	0	0
T11	1440	3	0	0
T16	2149	0	0	0
T17	2075	146	0	0
T18	1552	0	0	0
T19	1174	0	0	0
T22	2000	0	0	0
T26	0	1093	0	0
T31	0	444	0	0
T32	0	1168	0	0
T37	0	15	0	0
T38	0	6	0	0
T49	0	200	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	356085925	92185626	0	0
T3	14398	549	0	0
T4	2284	0	0	0
T5	967	0	0	0
T8	0	16	0	0
T10	1608	0	0	0
T11	1440	3	0	0
T16	2149	0	0	0
T17	2075	146	0	0
T18	1552	0	0	0
T19	1174	0	0	0
T22	2000	0	0	0
T26	0	1093	0	0
T31	0	444	0	0
T32	0	965	0	0
T37	0	15	0	0
T38	0	6	0	0
T49	0	200	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	356085925	92185626	0	0
T3	14398	549	0	0
T4	2284	0	0	0
T5	967	0	0	0
T8	0	16	0	0
T10	1608	0	0	0
T11	1440	3	0	0
T16	2149	0	0	0
T17	2075	146	0	0
T18	1552	0	0	0
T19	1174	0	0	0
T22	2000	0	0	0
T26	0	1093	0	0
T31	0	444	0	0
T32	0	965	0	0
T37	0	15	0	0
T38	0	6	0	0
T49	0	200	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	356085925	97984524	0	0
T3	14398	549	0	0
T4	2284	0	0	0
T5	967	0	0	0
T8	0	16	0	0
T10	1608	0	0	0
T11	1440	3	0	0
T16	2149	0	0	0
T17	2075	146	0	0
T18	1552	0	0	0
T19	1174	0	0	0
T22	2000	0	0	0
T26	0	1093	0	0
T31	0	444	0	0
T32	0	1168	0	0
T37	0	15	0	0
T38	0	6	0	0
T49	0	200	0	0

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	356085925	355255060	0	0
T1	3968	3880	0	0
T2	2197	2106	0	0
T3	14398	14311	0	0
T4	2284	2224	0	0
T5	967	871	0	0
T10	1608	1525	0	0
T16	2149	2059	0	0
T17	2075	1991	0	0
T18	1552	1490	0	0
T19	1174	1104	0	0