Unified Coverage Report :: Module :: flash_mp_data_region_sel

Module : flash_mp_data_region_sel

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/default/sim-vcs/../src/lowrisc_opentitan_top_earlgrey_flash_ctrl_0.1/rtl/flash_mp_data_region_sel.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_flash_mp.u_sw_sel	100.00	100.00	100.00			100.00
tb.dut.u_flash_mp.u_hw_sel	100.00	100.00				100.00
tb.dut.u_eflash.u_region_sel	100.00	100.00	100.00			100.00

---

Module Instance : tb.dut.u_flash_mp.u_sw_sel

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.46	100.00	97.84			100.00	100.00	u_flash_mp

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_flash_mp.u_hw_sel

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.46	100.00	97.84			100.00	100.00	u_flash_mp

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_eflash.u_region_sel

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
94.56	97.67	86.00			100.00		u_eflash

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Module : flash_mp_data_region_sel ( parameter Regions=9 )
Line Coverage for Module self-instances :

SCORE	LINE
100.00	100.00

tb.dut.u_flash_mp.u_sw_sel

SCORE	LINE
100.00	100.00

tb.dut.u_eflash.u_region_sel

	Line No.	Total	Covered	Percent
TOTAL		16	16	100.00
CONT_ASSIGN	28	1	1	100.00
CONT_ASSIGN	30	1	1	100.00
CONT_ASSIGN	30	1	1	100.00
CONT_ASSIGN	30	1	1	100.00
CONT_ASSIGN	30	1	1	100.00
CONT_ASSIGN	30	1	1	100.00
CONT_ASSIGN	30	1	1	100.00
CONT_ASSIGN	30	1	1	100.00
CONT_ASSIGN	30	1	1	100.00
ALWAYS	35	0	0
ALWAYS	35	3	3	100.00
ALWAYS	49	4	4	100.00

27                        // decode for software interface region
28         1/1            assign region_sel[0] = region_match[0];
           Tests:       T1 T2 T3 
29                        for (genvar i = 1; i < Regions; i++) begin: gen_region_priority
30         8/8              assign region_sel[i] = region_match[i] & ~|region_match[i-1:0];
           Tests:       T1 T2 T3  | T1 T2 T3  | T1 T2 T3  | T1 T2 T3  | T1 T2 T3  | T1 T2 T3  | T1 T2 T3  | T1 T2 T3 
31                        end
32                      
33                        // check for region match
34                        always_comb begin
35         1/1              for (int i = 0; i < Regions; i++) begin: gen_region_comps
           Tests:       T1 T2 T3 
36         1/1                region_end[i] = {1'b0, region_attrs_i[i].cfg.base} + region_attrs_i[i].cfg.size;
           Tests:       T1 T2 T3 
37                      
38                            // region matches if address within range and if the partition matches
39         1/1                region_match[i] = addr_i >= region_attrs_i[i].cfg.base &
           Tests:       T1 T2 T3 
40                                              {1'b0, addr_i} < region_end[i] &
41                                              phase_i == region_attrs_i[i].phase &
42                                              mubi4_test_true_strict(region_attrs_i[i].cfg.en) &
43                                              req_i;
44                          end
45                        end
46                      
47                        // select appropriate region configuration
48                        always_comb begin
49         1/1              sel_cfg_o = '0;
           Tests:       T1 T2 T3 
50         1/1              for (int i = 0; i < Regions; i++) begin: gen_region_sel
           Tests:       T1 T2 T3 
51         1/1                if (region_sel[i]) begin
           Tests:       T1 T2 T3 
52         1/1                  sel_cfg_o = region_attrs_i[i].cfg;
           Tests:       T1 T2 T3 
53                            end
                        MISSING_ELSE

---

Line Coverage for Module : flash_mp_data_region_sel ( parameter Regions=1 )
Line Coverage for Module self-instances :

SCORE	LINE
100.00	100.00

tb.dut.u_flash_mp.u_hw_sel

	Line No.	Total	Covered	Percent
TOTAL		8	8	100.00
CONT_ASSIGN	28	1	1	100.00
ALWAYS	35	0	0
ALWAYS	35	3	3	100.00
ALWAYS	49	4	4	100.00

27                        // decode for software interface region
28         1/1            assign region_sel[0] = region_match[0];
           Tests:       T1 T2 T3 
29                        for (genvar i = 1; i < Regions; i++) begin: gen_region_priority
30                          assign region_sel[i] = region_match[i] & ~|region_match[i-1:0];
31                        end
32                      
33                        // check for region match
34                        always_comb begin
35         1/1              for (int i = 0; i < Regions; i++) begin: gen_region_comps
           Tests:       T1 T2 T3 
36         1/1                region_end[i] = {1'b0, region_attrs_i[i].cfg.base} + region_attrs_i[i].cfg.size;
           Tests:       T1 T2 T3 
37                      
38                            // region matches if address within range and if the partition matches
39         1/1                region_match[i] = addr_i >= region_attrs_i[i].cfg.base &
           Tests:       T1 T2 T3 
40                                              {1'b0, addr_i} < region_end[i] &
41                                              phase_i == region_attrs_i[i].phase &
42                                              mubi4_test_true_strict(region_attrs_i[i].cfg.en) &
43                                              req_i;
44                          end
45                        end
46                      
47                        // select appropriate region configuration
48                        always_comb begin
49         1/1              sel_cfg_o = '0;
           Tests:       T1 T2 T3 
50         1/1              for (int i = 0; i < Regions; i++) begin: gen_region_sel
           Tests:       T1 T2 T3 
51         1/1                if (region_sel[i]) begin
           Tests:       T1 T2 T3 
52         1/1                  sel_cfg_o = region_attrs_i[i].cfg;
           Tests:       T84 T134 T108 
53                            end
                        MISSING_ELSE

---

Cond Coverage for Module : flash_mp_data_region_sel

	Total	Covered	Percent
Conditions	24	24	100.00
Logical	24	24	100.00
Non-Logical	0	0
Event	0	0

 LINE       30
 EXPRESSION (region_match[1] & ((~|region_match[0])))
             -------1-------   ----------2----------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T201,T194,T65
1	1	Covered	T12,T8,T32

 LINE       30
 EXPRESSION (region_match[2] & ((~|region_match[(2 - 1):0])))
             -------1-------   --------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T50,T201,T62
1	1	Covered	T18,T11,T40

 LINE       30
 EXPRESSION (region_match[3] & ((~|region_match[(3 - 1):0])))
             -------1-------   --------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T201,T44,T97
1	1	Covered	T32,T26,T50

 LINE       30
 EXPRESSION (region_match[4] & ((~|region_match[(4 - 1):0])))
             -------1-------   --------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T32,T49,T201
1	1	Covered	T57,T66,T70

 LINE       30
 EXPRESSION (region_match[5] & ((~|region_match[(5 - 1):0])))
             -------1-------   --------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T8,T50,T201
1	1	Covered	T11,T26,T50

 LINE       30
 EXPRESSION (region_match[6] & ((~|region_match[(6 - 1):0])))
             -------1-------   --------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T8,T70,T71
1	1	Covered	T8,T37,T26

 LINE       30
 EXPRESSION (region_match[7] & ((~|region_match[(7 - 1):0])))
             -------1-------   --------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T37,T70,T201
1	1	Covered	T37,T26,T51

 LINE       30
 EXPRESSION (region_match[8] & ((~|region_match[(8 - 1):0])))
             -------1-------   --------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T18,T10,T11
1	1	Covered	T1,T2,T3

---

Branch Coverage for Module : flash_mp_data_region_sel

	Line No.	Total	Covered	Percent
Branches		2	2	100.00
IF	51	2	2	100.00

51               if (region_sel[i]) begin
                 -1-  
52                 sel_cfg_o = region_attrs_i[i].cfg;
                   ==>
53               end
                 MISSING_ELSE
                 ==>

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

Line Coverage for Instance : tb.dut.u_flash_mp.u_sw_sel

	Line No.	Total	Covered	Percent
TOTAL		16	16	100.00
CONT_ASSIGN	28	1	1	100.00
CONT_ASSIGN	30	1	1	100.00
CONT_ASSIGN	30	1	1	100.00
CONT_ASSIGN	30	1	1	100.00
CONT_ASSIGN	30	1	1	100.00
CONT_ASSIGN	30	1	1	100.00
CONT_ASSIGN	30	1	1	100.00
CONT_ASSIGN	30	1	1	100.00
CONT_ASSIGN	30	1	1	100.00
ALWAYS	35	0	0
ALWAYS	35	3	3	100.00
ALWAYS	49	4	4	100.00

27                        // decode for software interface region
28         1/1            assign region_sel[0] = region_match[0];
           Tests:       T1 T2 T3 
29                        for (genvar i = 1; i < Regions; i++) begin: gen_region_priority
30         8/8              assign region_sel[i] = region_match[i] & ~|region_match[i-1:0];
           Tests:       T1 T2 T3  | T1 T2 T3  | T1 T2 T3  | T1 T2 T3  | T1 T2 T3  | T1 T2 T3  | T1 T2 T3  | T1 T2 T3 
31                        end
32                      
33                        // check for region match
34                        always_comb begin
35         1/1              for (int i = 0; i < Regions; i++) begin: gen_region_comps
           Tests:       T1 T2 T3 
36         1/1                region_end[i] = {1'b0, region_attrs_i[i].cfg.base} + region_attrs_i[i].cfg.size;
           Tests:       T1 T2 T3 
37                      
38                            // region matches if address within range and if the partition matches
39         1/1                region_match[i] = addr_i >= region_attrs_i[i].cfg.base &
           Tests:       T1 T2 T3 
40                                              {1'b0, addr_i} < region_end[i] &
41                                              phase_i == region_attrs_i[i].phase &
42                                              mubi4_test_true_strict(region_attrs_i[i].cfg.en) &
43                                              req_i;
44                          end
45                        end
46                      
47                        // select appropriate region configuration
48                        always_comb begin
49         1/1              sel_cfg_o = '0;
           Tests:       T1 T2 T3 
50         1/1              for (int i = 0; i < Regions; i++) begin: gen_region_sel
           Tests:       T1 T2 T3 
51         1/1                if (region_sel[i]) begin
           Tests:       T1 T2 T3 
52         1/1                  sel_cfg_o = region_attrs_i[i].cfg;
           Tests:       T1 T2 T3 
53                            end
                        MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_flash_mp.u_sw_sel

	Total	Covered	Percent
Conditions	24	24	100.00
Logical	24	24	100.00
Non-Logical	0	0
Event	0	0

 LINE       30
 EXPRESSION (region_match[1] & ((~|region_match[0])))
             -------1-------   ----------2----------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T201,T88,T242
1	1	Covered	T12,T8,T50

 LINE       30
 EXPRESSION (region_match[2] & ((~|region_match[(2 - 1):0])))
             -------1-------   --------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T50,T201,T62
1	1	Covered	T18,T40,T51

 LINE       30
 EXPRESSION (region_match[3] & ((~|region_match[(3 - 1):0])))
             -------1-------   --------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T201,T97,T62
1	1	Covered	T26,T50,T40

 LINE       30
 EXPRESSION (region_match[4] & ((~|region_match[(4 - 1):0])))
             -------1-------   --------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T201,T82,T62
1	1	Covered	T66,T82,T260

 LINE       30
 EXPRESSION (region_match[5] & ((~|region_match[(5 - 1):0])))
             -------1-------   --------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T8,T50,T201
1	1	Covered	T50,T66,T70

 LINE       30
 EXPRESSION (region_match[6] & ((~|region_match[(6 - 1):0])))
             -------1-------   --------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T8,T70,T71
1	1	Covered	T8,T26,T51

 LINE       30
 EXPRESSION (region_match[7] & ((~|region_match[(7 - 1):0])))
             -------1-------   --------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T70,T201,T260
1	1	Covered	T37,T26,T51

 LINE       30
 EXPRESSION (region_match[8] & ((~|region_match[(8 - 1):0])))
             -------1-------   --------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T18,T12,T8
1	1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_flash_mp.u_sw_sel

	Line No.	Total	Covered	Percent
Branches		2	2	100.00
IF	51	2	2	100.00

51               if (region_sel[i]) begin
                 -1-  
52                 sel_cfg_o = region_attrs_i[i].cfg;
                   ==>
53               end
                 MISSING_ELSE
                 ==>

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

Line Coverage for Instance : tb.dut.u_flash_mp.u_hw_sel

	Line No.	Total	Covered	Percent
TOTAL		8	8	100.00
CONT_ASSIGN	28	1	1	100.00
ALWAYS	35	0	0
ALWAYS	35	3	3	100.00
ALWAYS	49	4	4	100.00

27                        // decode for software interface region
28         1/1            assign region_sel[0] = region_match[0];
           Tests:       T1 T2 T3 
29                        for (genvar i = 1; i < Regions; i++) begin: gen_region_priority
30                          assign region_sel[i] = region_match[i] & ~|region_match[i-1:0];
31                        end
32                      
33                        // check for region match
34                        always_comb begin
35         1/1              for (int i = 0; i < Regions; i++) begin: gen_region_comps
           Tests:       T1 T2 T3 
36         1/1                region_end[i] = {1'b0, region_attrs_i[i].cfg.base} + region_attrs_i[i].cfg.size;
           Tests:       T1 T2 T3 
37                      
38                            // region matches if address within range and if the partition matches
39         1/1                region_match[i] = addr_i >= region_attrs_i[i].cfg.base &
           Tests:       T1 T2 T3 
40                                              {1'b0, addr_i} < region_end[i] &
41                                              phase_i == region_attrs_i[i].phase &
42                                              mubi4_test_true_strict(region_attrs_i[i].cfg.en) &
43                                              req_i;
44                          end
45                        end
46                      
47                        // select appropriate region configuration
48                        always_comb begin
49         1/1              sel_cfg_o = '0;
           Tests:       T1 T2 T3 
50         1/1              for (int i = 0; i < Regions; i++) begin: gen_region_sel
           Tests:       T1 T2 T3 
51         1/1                if (region_sel[i]) begin
           Tests:       T1 T2 T3 
52         1/1                  sel_cfg_o = region_attrs_i[i].cfg;
           Tests:       T84 T134 T108 
53                            end
                        MISSING_ELSE

---

Branch Coverage for Instance : tb.dut.u_flash_mp.u_hw_sel

	Line No.	Total	Covered	Percent
Branches		2	2	100.00
IF	51	2	2	100.00

51               if (region_sel[i]) begin
                 -1-  
52                 sel_cfg_o = region_attrs_i[i].cfg;
                   ==>
53               end
                 MISSING_ELSE
                 ==>

Branches:

-1-	Status	Tests
1	Covered	T84,T134,T108
0	Covered	T1,T2,T3

Line Coverage for Instance : tb.dut.u_eflash.u_region_sel

	Line No.	Total	Covered	Percent
TOTAL		16	16	100.00
CONT_ASSIGN	28	1	1	100.00
CONT_ASSIGN	30	1	1	100.00
CONT_ASSIGN	30	1	1	100.00
CONT_ASSIGN	30	1	1	100.00
CONT_ASSIGN	30	1	1	100.00
CONT_ASSIGN	30	1	1	100.00
CONT_ASSIGN	30	1	1	100.00
CONT_ASSIGN	30	1	1	100.00
CONT_ASSIGN	30	1	1	100.00
ALWAYS	35	0	0
ALWAYS	35	3	3	100.00
ALWAYS	49	4	4	100.00

27                        // decode for software interface region
28         1/1            assign region_sel[0] = region_match[0];
           Tests:       T2 T3 T4 
29                        for (genvar i = 1; i < Regions; i++) begin: gen_region_priority
30         8/8              assign region_sel[i] = region_match[i] & ~|region_match[i-1:0];
           Tests:       T2 T3 T4  | T2 T3 T4  | T2 T3 T4  | T2 T3 T4  | T2 T3 T4  | T2 T3 T4  | T2 T3 T4  | T2 T3 T4 
31                        end
32                      
33                        // check for region match
34                        always_comb begin
35         1/1              for (int i = 0; i < Regions; i++) begin: gen_region_comps
           Tests:       T1 T2 T3 
36         1/1                region_end[i] = {1'b0, region_attrs_i[i].cfg.base} + region_attrs_i[i].cfg.size;
           Tests:       T1 T2 T3 
37                      
38                            // region matches if address within range and if the partition matches
39         1/1                region_match[i] = addr_i >= region_attrs_i[i].cfg.base &
           Tests:       T1 T2 T3 
40                                              {1'b0, addr_i} < region_end[i] &
41                                              phase_i == region_attrs_i[i].phase &
42                                              mubi4_test_true_strict(region_attrs_i[i].cfg.en) &
43                                              req_i;
44                          end
45                        end
46                      
47                        // select appropriate region configuration
48                        always_comb begin
49         1/1              sel_cfg_o = '0;
           Tests:       T1 T2 T3 
50         1/1              for (int i = 0; i < Regions; i++) begin: gen_region_sel
           Tests:       T1 T2 T3 
51         1/1                if (region_sel[i]) begin
           Tests:       T1 T2 T3 
52         1/1                  sel_cfg_o = region_attrs_i[i].cfg;
           Tests:       T3 T10 T11 
53                            end
                        MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_eflash.u_region_sel

	Total	Covered	Percent
Conditions	24	24	100.00
Logical	24	24	100.00
Non-Logical	0	0
Event	0	0

 LINE       30
 EXPRESSION (region_match[1] & ((~|region_match[0])))
             -------1-------   ----------2----------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T201,T194,T65
1	1	Covered	T12,T32,T49

 LINE       30
 EXPRESSION (region_match[2] & ((~|region_match[(2 - 1):0])))
             -------1-------   --------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T50,T201,T261
1	1	Covered	T11,T39,T54

 LINE       30
 EXPRESSION (region_match[3] & ((~|region_match[(3 - 1):0])))
             -------1-------   --------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T201,T44,T261
1	1	Covered	T32,T44,T116

 LINE       30
 EXPRESSION (region_match[4] & ((~|region_match[(4 - 1):0])))
             -------1-------   --------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T32,T49,T201
1	1	Covered	T57,T70,T198

 LINE       30
 EXPRESSION (region_match[5] & ((~|region_match[(5 - 1):0])))
             -------1-------   --------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T201,T261,T262
1	1	Covered	T11,T26,T50

 LINE       30
 EXPRESSION (region_match[6] & ((~|region_match[(6 - 1):0])))
             -------1-------   --------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T201,T263,T264
1	1	Covered	T37,T197,T156

 LINE       30
 EXPRESSION (region_match[7] & ((~|region_match[(7 - 1):0])))
             -------1-------   --------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T37,T201,T265
1	1	Covered	T26,T39,T116

 LINE       30
 EXPRESSION (region_match[8] & ((~|region_match[(8 - 1):0])))
             -------1-------   --------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T10,T11,T12
1	1	Covered	T3,T11,T12

---

Branch Coverage for Instance : tb.dut.u_eflash.u_region_sel

	Line No.	Total	Covered	Percent
Branches		2	2	100.00
IF	51	2	2	100.00

51               if (region_sel[i]) begin
                 -1-  
52                 sel_cfg_o = region_attrs_i[i].cfg;
                   ==>
53               end
                 MISSING_ELSE
                 ==>

Branches:

-1-	Status	Tests
1	Covered	T3,T10,T11
0	Covered	T1,T2,T3