Unified Coverage Report :: Group :: cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=5}

Group : cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=5}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
88.24	1	100	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

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Summary for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=5}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	10	0	10	100.00
Crosses	24	4	20	83.33

Variables for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=5}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	6	0	6	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=5}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_cg_cc	24	4	20	83.33	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	6	0	6	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	275983	1		T1	1		T2	2		T3	2
all_values[1]	275983	1		T1	1		T2	2		T3	2
all_values[2]	275983	1		T1	1		T2	2		T3	2
all_values[3]	275983	1		T1	1		T2	2		T3	2
all_values[4]	275983	1		T1	1		T2	2		T3	2
all_values[5]	275983	1		T1	1		T2	2		T3	2

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Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	558274	1		T1	6		T2	12		T3	12
auto[1]	1097624	1		T32	5992		T39	13120		T43	13104

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Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	814919	1		T1	4		T2	7		T3	7
auto[1]	840979	1		T1	2		T2	5		T3	5

---

Summary for Cross intr_cg_cc

Samples crossed: cp_intr cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	24	4	20	83.33	4

Automatically Generated Cross Bins for intr_cg_cc

Element holes

cp_intr	cp_intr_en	cp_intr_state	COUNT	AT LEAST	NUMBER
[all_values[0] , all_values[1]]	*	[auto[0]]	--	--	4

Covered bins

cp_intr	cp_intr_en	cp_intr_state	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[1]	275834	1		T1	1		T2	2		T3	2
all_values[0]	auto[1]	auto[1]	149	1		T242	2		T244	2		T305	5
all_values[1]	auto[0]	auto[1]	275836	1		T1	1		T2	2		T3	2
all_values[1]	auto[1]	auto[1]	147	1		T242	2		T243	1		T244	8
all_values[2]	auto[0]	auto[0]	1602	1		T1	1		T2	2		T3	2
all_values[2]	auto[0]	auto[1]	58	1		T243	1		T244	1		T306	2
all_values[2]	auto[1]	auto[0]	274276	1		T32	1498		T39	3280		T43	3276
all_values[2]	auto[1]	auto[1]	47	1		T242	2		T243	2		T306	1
all_values[3]	auto[0]	auto[0]	1591	1		T1	1		T2	2		T3	2
all_values[3]	auto[0]	auto[1]	61	1		T243	1		T244	1		T305	1
all_values[3]	auto[1]	auto[0]	80089	1		T32	1498		T39	1640		T43	1638
all_values[3]	auto[1]	auto[1]	194242	1		T39	1640		T43	1638		T44	390
all_values[4]	auto[0]	auto[0]	1127	1		T1	1		T2	1		T3	1
all_values[4]	auto[0]	auto[1]	521	1		T2	1		T3	1		T11	1
all_values[4]	auto[1]	auto[0]	180437	1		T32	1		T39	1640		T43	1638
all_values[4]	auto[1]	auto[1]	93898	1		T32	1497		T39	1640		T43	1638
all_values[5]	auto[0]	auto[0]	1530	1		T1	1		T2	2		T3	2
all_values[5]	auto[0]	auto[1]	114	1		T45	1		T46	1		T47	1
all_values[5]	auto[1]	auto[0]	274267	1		T32	1498		T39	3280		T43	3276
all_values[5]	auto[1]	auto[1]	72	1		T242	1		T243	2		T244	4