Detail Report for Assertions

Assertions Uncovered:

ASSERTIONS	CATEGORY	SEVERITY	ATTEMPTS	REAL SUCCESSES	FAILURES	INCOMPLETE	SRC
tb.dut.FpvSecCmEflashReqFifoRptrCheck_A	0	0	394250859	0	0	0
tb.dut.FpvSecCmEflashReqFifoWptrCheck_A	0	0	394250859	0	0	0
tb.dut.FpvSecCmEflashRspFifoRptrCheck_A	0	0	394250859	0	0	0
tb.dut.FpvSecCmEflashRspFifoWptrCheck_A	0	0	394250859	0	0	0
tb.dut.FpvSecCmEflashSramReqFifoRptrCheck_A	0	0	394250859	0	0	0
tb.dut.FpvSecCmEflashSramReqFifoWptrCheck_A	0	0	394250859	0	0	0
tb.dut.FpvSecCmRdReqFifoRptrCheck_A	0	0	394250859	0	0	0
tb.dut.FpvSecCmRdReqFifoWptrCheck_A	0	0	394250859	0	0	0
tb.dut.FpvSecCmRdSramReqFifoRptrCheck_A	0	0	394250859	0	0	0
tb.dut.FpvSecCmRdSramReqFifoWptrCheck_A	0	0	394250859	0	0	0
tb.dut.PrimRspPayLoad_A	0	0	394250859	0	0	0
tb.dut.u_eflash.gen_flash_cores[0].u_core.u_rd.u_valid_random.LockArbDecision_A	0	0	394250859	0	0	0
tb.dut.u_eflash.gen_flash_cores[0].u_core.u_rd.u_valid_random.ReqStaysHighUntilGranted0_M	0	0	394250859	0	0	0
tb.dut.u_eflash.gen_flash_cores[0].u_core.u_rd.u_valid_random.RoundRobin_A	0	0	394250859	0	0	1040
tb.dut.u_eflash.gen_flash_cores[1].u_core.u_rd.u_valid_random.LockArbDecision_A	0	0	394250859	0	0	0
tb.dut.u_eflash.gen_flash_cores[1].u_core.u_rd.u_valid_random.ReqStaysHighUntilGranted0_M	0	0	394250859	0	0	0
tb.dut.u_eflash.gen_flash_cores[1].u_core.u_rd.u_valid_random.RoundRobin_A	0	0	394250859	0	0	1040
tb.dut.u_eflash.u_scramble.u_prim_arbiter_tree_calc.gen_input_bufs[0].gen_rr_arbiter.u_arb.RoundRobin_A	0	0	394250859	0	0	1040
tb.dut.u_eflash.u_scramble.u_prim_arbiter_tree_calc.gen_input_bufs[1].gen_rr_arbiter.u_arb.RoundRobin_A	0	0	394250859	0	0	1040
tb.dut.u_eflash.u_scramble.u_prim_arbiter_tree_op.gen_input_bufs[0].gen_rr_arbiter.u_arb.RoundRobin_A	0	0	394250859	0	0	1040
tb.dut.u_eflash.u_scramble.u_prim_arbiter_tree_op.gen_input_bufs[1].gen_rr_arbiter.u_arb.RoundRobin_A	0	0	394250859	0	0	1040
tb.dut.u_prog_tl_gate.OutStandingOvfl_A	0	0	394250859	0	0	0
tb.dut.u_tl_gate.OutStandingOvfl_A	0	0	394250859	0	0	0
tb.dut.u_to_prog_fifo.rvalidHighReqFifoEmpty	0	0	394250859	0	0	0
tb.dut.u_to_prog_fifo.rvalidHighWhenRspFifoFull	0	0	394250859	0	0	0
tb.dut.u_to_prog_fifo.u_rspfifo.DataKnown_A	0	0	394250859	0	0	0
tb.dut.u_to_prog_fifo.u_rspfifo.gen_normal_fifo.depthShallNotExceedParamDepth	0	0	394250859	0	0	0
tb.dut.u_to_prog_fifo.u_sramreqfifo.DataKnown_A	0	0	394250859	0	0	0
tb.dut.u_to_prog_fifo.u_sramreqfifo.gen_normal_fifo.depthShallNotExceedParamDepth	0	0	394250859	0	0	0

Assertions Success:

ASSERTIONS	CATEGORY	SEVERITY	ATTEMPTS	REAL SUCCESSES	FAILURES	INCOMPLETE	SRC
tb.dut.FifoDepthCheck_A	0	0	1043	1043	0	0
tb.dut.FlashAddrKnown_A	0	0	394250859	263818409	0	0
tb.dut.FlashAddrKnown_AKnownEnable	0	0	394250859	393379073	0	0
tb.dut.FlashKnownO_A	0	0	394250859	393379073	0	0
tb.dut.FlashProgKnown_A	0	0	394250859	157776538	0	0
tb.dut.FlashProgKnown_AKnownEnable	0	0	394250859	393379073	0	0
tb.dut.FpvSecCmAddrCntAlertCheck_A	0	0	394250859	50	0	0
tb.dut.FpvSecCmArbFsmCheck_A	0	0	394250859	50	0	0
tb.dut.FpvSecCmLcCtrlFsmCheck_A	0	0	394250859	50	0	0
tb.dut.FpvSecCmLcCtrlRmaFsmCheck_A	0	0	394250859	50	0	0
tb.dut.FpvSecCmPageCntAlertCheck_A	0	0	394250859	50	0	0
tb.dut.FpvSecCmProgCnt_A	0	0	394250859	50	0	0
tb.dut.FpvSecCmRdCnt_A	0	0	394250859	50	0	0
tb.dut.FpvSecCmRdRspFifoRptrCheck_A	0	0	394250859	50	0	0
tb.dut.FpvSecCmRdRspFifoWptrCheck_A	0	0	394250859	50	0	0
tb.dut.FpvSecCmRegWeOnehotCheck_A	0	0	394250859	50	0	0
tb.dut.FpvSecCmSeedCntAlertCheck_A	0	0	394250859	50	0	0
tb.dut.FpvSecCmTlLcGateFsm_A	0	0	394250859	50	0	0
tb.dut.FpvSecCmTlProgLcGateFsm_A	0	0	394250859	50	0	0
tb.dut.FpvSecCmWipeIdx_A	0	0	394250859	50	0	0
tb.dut.FpvSecCmWordCntAlertCheck_A	0	0	394250859	50	0	0
tb.dut.IntrErrO_A	0	0	394250859	393379073	0	0
tb.dut.IntrOpDoneKnownO_A	0	0	394250859	393379073	0	0
tb.dut.IntrProgEmptyKnownO_A	0	0	394250859	393379073	0	0
tb.dut.IntrProgLvlKnownO_A	0	0	394250859	393379073	0	0
tb.dut.IntrProgRdFullKnownO_A	0	0	394250859	393379073	0	0
tb.dut.IntrRdLvlKnownO_A	0	0	394250859	393379073	0	0
tb.dut.MemRspPayLoad_A	0	0	394250859	5077597	0	0
tb.dut.MemRspPayLoad_AKnownEnable	0	0	394250859	393379073	0	0
tb.dut.MemTlAReadyKnownO_A	0	0	394250859	393379073	0	0
tb.dut.MemTlDValidKnownO_A	0	0	394250859	393379073	0	0
tb.dut.PrimRspPayLoad_AKnownEnable	0	0	394250859	393379073	0	0
tb.dut.PrimTlAReadyKnownO_A	0	0	394250859	393379073	0	0
tb.dut.PrimTlDValidKnownO_A	0	0	394250859	393379073	0	0
tb.dut.RspPayLoad_A	0	0	394100769	42740751	0	0
tb.dut.RspPayLoad_AKnownEnable	0	0	394250859	393379073	0	0
tb.dut.TdoEnIsOne_A	0	0	394250859	393379073	0	0
tb.dut.TdoKnown_A	0	0	394250859	393379073	0	0
tb.dut.TlAReadyKnownO_A	0	0	394250859	393379073	0	0
tb.dut.TlDValidKnownO_A	0	0	394250859	393379073	0	0
tb.dut.flash_ctrl_core_csr_assert.TlulOOBAddrErr_A	0	0	396824248	4171	0	0
tb.dut.flash_ctrl_core_csr_assert.addr_rd_A	0	0	396824248	1279	0	0
tb.dut.flash_ctrl_core_csr_assert.bank0_info0_page_cfg_0_rd_A	0	0	396824248	2903	0	0
tb.dut.flash_ctrl_core_csr_assert.bank0_info0_page_cfg_1_rd_A	0	0	396824248	2934	0	0
tb.dut.flash_ctrl_core_csr_assert.bank0_info0_page_cfg_2_rd_A	0	0	396824248	2614	0	0
tb.dut.flash_ctrl_core_csr_assert.bank0_info0_page_cfg_3_rd_A	0	0	396824248	2741	0	0
tb.dut.flash_ctrl_core_csr_assert.bank0_info0_page_cfg_4_rd_A	0	0	396824248	2832	0	0
tb.dut.flash_ctrl_core_csr_assert.bank0_info0_page_cfg_5_rd_A	0	0	396824248	2788	0	0
tb.dut.flash_ctrl_core_csr_assert.bank0_info0_page_cfg_6_rd_A	0	0	396824248	2854	0	0
tb.dut.flash_ctrl_core_csr_assert.bank0_info0_page_cfg_7_rd_A	0	0	396824248	3143	0	0
tb.dut.flash_ctrl_core_csr_assert.bank0_info0_page_cfg_8_rd_A	0	0	396824248	2654	0	0
tb.dut.flash_ctrl_core_csr_assert.bank0_info0_page_cfg_9_rd_A	0	0	396824248	2862	0	0
tb.dut.flash_ctrl_core_csr_assert.bank0_info0_regwen_0_rd_A	0	0	396824248	1330	0	0
tb.dut.flash_ctrl_core_csr_assert.bank0_info0_regwen_1_rd_A	0	0	396824248	1253	0	0
tb.dut.flash_ctrl_core_csr_assert.bank0_info0_regwen_2_rd_A	0	0	396824248	1162	0	0
tb.dut.flash_ctrl_core_csr_assert.bank0_info0_regwen_3_rd_A	0	0	396824248	1136	0	0
tb.dut.flash_ctrl_core_csr_assert.bank0_info0_regwen_4_rd_A	0	0	396824248	939	0	0
tb.dut.flash_ctrl_core_csr_assert.bank0_info0_regwen_5_rd_A	0	0	396824248	1352	0	0
tb.dut.flash_ctrl_core_csr_assert.bank0_info0_regwen_6_rd_A	0	0	396824248	1206	0	0
tb.dut.flash_ctrl_core_csr_assert.bank0_info0_regwen_7_rd_A	0	0	396824248	1200	0	0
tb.dut.flash_ctrl_core_csr_assert.bank0_info0_regwen_8_rd_A	0	0	396824248	1264	0	0
tb.dut.flash_ctrl_core_csr_assert.bank0_info0_regwen_9_rd_A	0	0	396824248	1291	0	0
tb.dut.flash_ctrl_core_csr_assert.bank0_info1_page_cfg_rd_A	0	0	396824248	2580	0	0
tb.dut.flash_ctrl_core_csr_assert.bank0_info1_regwen_rd_A	0	0	396824248	903	0	0
tb.dut.flash_ctrl_core_csr_assert.bank0_info2_page_cfg_0_rd_A	0	0	396824248	3004	0	0
tb.dut.flash_ctrl_core_csr_assert.bank0_info2_page_cfg_1_rd_A	0	0	396824248	2745	0	0
tb.dut.flash_ctrl_core_csr_assert.bank0_info2_regwen_0_rd_A	0	0	396824248	1257	0	0
tb.dut.flash_ctrl_core_csr_assert.bank0_info2_regwen_1_rd_A	0	0	396824248	1388	0	0
tb.dut.flash_ctrl_core_csr_assert.bank1_info0_page_cfg_0_rd_A	0	0	396824248	2473	0	0
tb.dut.flash_ctrl_core_csr_assert.bank1_info0_page_cfg_1_rd_A	0	0	396824248	2739	0	0
tb.dut.flash_ctrl_core_csr_assert.bank1_info0_page_cfg_2_rd_A	0	0	396824248	2985	0	0
tb.dut.flash_ctrl_core_csr_assert.bank1_info0_page_cfg_3_rd_A	0	0	396824248	3135	0	0
tb.dut.flash_ctrl_core_csr_assert.bank1_info0_page_cfg_4_rd_A	0	0	396824248	2827	0	0
tb.dut.flash_ctrl_core_csr_assert.bank1_info0_page_cfg_5_rd_A	0	0	396824248	3104	0	0
tb.dut.flash_ctrl_core_csr_assert.bank1_info0_page_cfg_6_rd_A	0	0	396824248	2832	0	0
tb.dut.flash_ctrl_core_csr_assert.bank1_info0_page_cfg_7_rd_A	0	0	396824248	2495	0	0
tb.dut.flash_ctrl_core_csr_assert.bank1_info0_page_cfg_8_rd_A	0	0	396824248	3165	0	0
tb.dut.flash_ctrl_core_csr_assert.bank1_info0_page_cfg_9_rd_A	0	0	396824248	2486	0	0
tb.dut.flash_ctrl_core_csr_assert.bank1_info0_regwen_0_rd_A	0	0	396824248	1295	0	0
tb.dut.flash_ctrl_core_csr_assert.bank1_info0_regwen_1_rd_A	0	0	396824248	1325	0	0
tb.dut.flash_ctrl_core_csr_assert.bank1_info0_regwen_2_rd_A	0	0	396824248	1391	0	0
tb.dut.flash_ctrl_core_csr_assert.bank1_info0_regwen_3_rd_A	0	0	396824248	1290	0	0
tb.dut.flash_ctrl_core_csr_assert.bank1_info0_regwen_4_rd_A	0	0	396824248	1133	0	0
tb.dut.flash_ctrl_core_csr_assert.bank1_info0_regwen_5_rd_A	0	0	396824248	1297	0	0
tb.dut.flash_ctrl_core_csr_assert.bank1_info0_regwen_6_rd_A	0	0	396824248	1355	0	0
tb.dut.flash_ctrl_core_csr_assert.bank1_info0_regwen_7_rd_A	0	0	396824248	1363	0	0
tb.dut.flash_ctrl_core_csr_assert.bank1_info0_regwen_8_rd_A	0	0	396824248	1323	0	0
tb.dut.flash_ctrl_core_csr_assert.bank1_info0_regwen_9_rd_A	0	0	396824248	1306	0	0
tb.dut.flash_ctrl_core_csr_assert.bank1_info1_page_cfg_rd_A	0	0	396824248	2830	0	0
tb.dut.flash_ctrl_core_csr_assert.bank1_info1_regwen_rd_A	0	0	396824248	1258	0	0
tb.dut.flash_ctrl_core_csr_assert.bank1_info2_page_cfg_0_rd_A	0	0	396824248	2950	0	0
tb.dut.flash_ctrl_core_csr_assert.bank1_info2_page_cfg_1_rd_A	0	0	396824248	2685	0	0
tb.dut.flash_ctrl_core_csr_assert.bank1_info2_regwen_0_rd_A	0	0	396824248	1135	0	0
tb.dut.flash_ctrl_core_csr_assert.bank1_info2_regwen_1_rd_A	0	0	396824248	1270	0	0
tb.dut.flash_ctrl_core_csr_assert.bank_cfg_regwen_rd_A	0	0	396824248	1167	0	0
tb.dut.flash_ctrl_core_csr_assert.default_region_rd_A	0	0	396824248	2436	0	0
tb.dut.flash_ctrl_core_csr_assert.exec_rd_A	0	0	396824248	1133	0	0
tb.dut.flash_ctrl_core_csr_assert.fifo_lvl_rd_A	0	0	396824248	1501	0	0
tb.dut.flash_ctrl_core_csr_assert.fifo_rst_rd_A	0	0	396824248	1266	0	0
tb.dut.flash_ctrl_core_csr_assert.hw_info_cfg_override_rd_A	0	0	396824248	1533	0	0
tb.dut.flash_ctrl_core_csr_assert.intr_enable_rd_A	0	0	396824248	2409	0	0
tb.dut.flash_ctrl_core_csr_assert.mp_region_0_rd_A	0	0	396824248	1301	0	0
tb.dut.flash_ctrl_core_csr_assert.mp_region_1_rd_A	0	0	396824248	1539	0	0
tb.dut.flash_ctrl_core_csr_assert.mp_region_2_rd_A	0	0	396824248	1567	0	0
tb.dut.flash_ctrl_core_csr_assert.mp_region_3_rd_A	0	0	396824248	1485	0	0
tb.dut.flash_ctrl_core_csr_assert.mp_region_4_rd_A	0	0	396824248	1339	0	0
tb.dut.flash_ctrl_core_csr_assert.mp_region_5_rd_A	0	0	396824248	1512	0	0
tb.dut.flash_ctrl_core_csr_assert.mp_region_6_rd_A	0	0	396824248	1444	0	0
tb.dut.flash_ctrl_core_csr_assert.mp_region_7_rd_A	0	0	396824248	1628	0	0
tb.dut.flash_ctrl_core_csr_assert.mp_region_cfg_0_rd_A	0	0	396824248	2765	0	0
tb.dut.flash_ctrl_core_csr_assert.mp_region_cfg_1_rd_A	0	0	396824248	2748	0	0
tb.dut.flash_ctrl_core_csr_assert.mp_region_cfg_2_rd_A	0	0	396824248	2608	0	0
tb.dut.flash_ctrl_core_csr_assert.mp_region_cfg_3_rd_A	0	0	396824248	2629	0	0
tb.dut.flash_ctrl_core_csr_assert.mp_region_cfg_4_rd_A	0	0	396824248	3000	0	0
tb.dut.flash_ctrl_core_csr_assert.mp_region_cfg_5_rd_A	0	0	396824248	2805	0	0
tb.dut.flash_ctrl_core_csr_assert.mp_region_cfg_6_rd_A	0	0	396824248	2667	0	0
tb.dut.flash_ctrl_core_csr_assert.mp_region_cfg_7_rd_A	0	0	396824248	2821	0	0
tb.dut.flash_ctrl_core_csr_assert.phy_alert_cfg_rd_A	0	0	396824248	464	0	0
tb.dut.flash_ctrl_core_csr_assert.region_cfg_regwen_0_rd_A	0	0	396824248	1250	0	0
tb.dut.flash_ctrl_core_csr_assert.region_cfg_regwen_1_rd_A	0	0	396824248	1336	0	0
tb.dut.flash_ctrl_core_csr_assert.region_cfg_regwen_2_rd_A	0	0	396824248	1307	0	0
tb.dut.flash_ctrl_core_csr_assert.region_cfg_regwen_3_rd_A	0	0	396824248	1042	0	0
tb.dut.flash_ctrl_core_csr_assert.region_cfg_regwen_4_rd_A	0	0	396824248	1353	0	0
tb.dut.flash_ctrl_core_csr_assert.region_cfg_regwen_5_rd_A	0	0	396824248	1240	0	0
tb.dut.flash_ctrl_core_csr_assert.region_cfg_regwen_6_rd_A	0	0	396824248	903	0	0
tb.dut.flash_ctrl_core_csr_assert.region_cfg_regwen_7_rd_A	0	0	396824248	1283	0	0
tb.dut.flash_ctrl_core_csr_assert.scratch_rd_A	0	0	396824248	987	0	0
tb.dut.gen_phy_assertions[0].FpvSecCmPhyFsmCheck_A	0	0	394250859	50	0	0
tb.dut.gen_phy_assertions[0].FpvSecCmPhyProgFsmCheck_A	0	0	394250859	50	0	0
tb.dut.gen_phy_assertions[1].FpvSecCmPhyFsmCheck_A	0	0	394250859	50	0	0
tb.dut.gen_phy_assertions[1].FpvSecCmPhyProgFsmCheck_A	0	0	394250859	50	0	0
tb.dut.gen_phy_cnt_errs[0].FpvSecCmPhyHostCnt_A	0	0	394250859	50	0	0
tb.dut.gen_phy_cnt_errs[0].FpvSecCmPhyRdDataFifoRPtr_A	0	0	394250859	50	0	0
tb.dut.gen_phy_cnt_errs[0].FpvSecCmPhyRdDataFifoWPtr_A	0	0	394250859	50	0	0
tb.dut.gen_phy_cnt_errs[0].FpvSecCmPhyRdRspFifoRPtr_A	0	0	394250859	50	0	0
tb.dut.gen_phy_cnt_errs[0].FpvSecCmPhyRdRspFifoWPtr_A	0	0	394250859	50	0	0
tb.dut.gen_phy_cnt_errs[0].FpvSecCmPhyRspFifoRPtr_A	0	0	394250859	50	0	0
tb.dut.gen_phy_cnt_errs[0].FpvSecCmPhyRspFifoWPtr_A	0	0	394250859	50	0	0
tb.dut.gen_phy_cnt_errs[1].FpvSecCmPhyHostCnt_A	0	0	394250859	50	0	0
tb.dut.gen_phy_cnt_errs[1].FpvSecCmPhyRdDataFifoRPtr_A	0	0	394250859	50	0	0
tb.dut.gen_phy_cnt_errs[1].FpvSecCmPhyRdDataFifoWPtr_A	0	0	394250859	50	0	0
tb.dut.gen_phy_cnt_errs[1].FpvSecCmPhyRdRspFifoRPtr_A	0	0	394250859	50	0	0
tb.dut.gen_phy_cnt_errs[1].FpvSecCmPhyRdRspFifoWPtr_A	0	0	394250859	50	0	0
tb.dut.gen_phy_cnt_errs[1].FpvSecCmPhyRspFifoRPtr_A	0	0	394250859	50	0	0
tb.dut.gen_phy_cnt_errs[1].FpvSecCmPhyRspFifoWPtr_A	0	0	394250859	50	0	0
tb.dut.gen_reg_we_assert_generic.FpvSecCmPrimRegWeOnehotCheck_A	0	0	394250859	24	0	0
tb.dut.tlul_assert_device.aKnown_A	0	0	396824202	35950232	0	0
tb.dut.tlul_assert_device.aKnown_AKnownEnable	0	0	396824202	395867354	0	0
tb.dut.tlul_assert_device.aReadyKnown_A	0	0	396824202	395867354	0	0
tb.dut.tlul_assert_device.dKnown_A	0	0	396824202	43494178	0	0
tb.dut.tlul_assert_device.dKnown_AKnownEnable	0	0	396824202	395867354	0	0
tb.dut.tlul_assert_device.dReadyKnown_A	0	0	396824202	395867354	0	0
tb.dut.tlul_assert_device.gen_assert_final[0].noOutstandingReqsAtEndOfSim_A	0	0	1255	1255	0	0
tb.dut.tlul_assert_device.gen_assert_final[100].noOutstandingReqsAtEndOfSim_A	0	0	1255	1255	0	0
tb.dut.tlul_assert_device.gen_assert_final[101].noOutstandingReqsAtEndOfSim_A	0	0	1255	1255	0	0
tb.dut.tlul_assert_device.gen_assert_final[102].noOutstandingReqsAtEndOfSim_A	0	0	1255	1255	0	0
tb.dut.tlul_assert_device.gen_assert_final[103].noOutstandingReqsAtEndOfSim_A	0	0	1255	1255	0	0
tb.dut.tlul_assert_device.gen_assert_final[104].noOutstandingReqsAtEndOfSim_A	0	0	1255	1255	0	0
tb.dut.tlul_assert_device.gen_assert_final[105].noOutstandingReqsAtEndOfSim_A	0	0	1255	1255	0	0
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