Tests
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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
96.02 95.22 93.82 98.31 92.52 97.12 96.99 98.15


Total tests in report: 1258
Tests are in graded order

Scores are accumulated (Total) and incremental (Incr) for each test.

SCORE LINE COND TOGGLE FSM BRANCH ASSERT GROUP  
TOTAL INCRTOTALINCRTOTALINCRTOTALINCRTOTALINCRTOTALINCRTOTALINCRTOTALINCRNAME
63.56 63.56 86.86 86.86 68.82 68.82 46.08 46.08 53.74 53.74 83.18 83.18 80.71 80.71 25.49 25.49 /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default/0.flash_ctrl_mid_op_rst.2467602662
71.23 7.67 88.99 2.14 78.11 9.28 62.75 16.67 60.54 6.80 86.30 3.12 83.25 2.54 38.66 13.16 /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default/0.flash_ctrl_rw_serr.333857502
77.18 5.95 92.03 3.04 83.93 5.82 65.00 2.25 60.54 0.00 92.03 5.73 91.63 8.37 55.12 16.46 /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/cover_reg_top/0.flash_ctrl_csr_mem_rw_with_rand_reset.3150807015
80.84 3.66 92.86 0.83 84.61 0.69 70.69 5.69 77.55 17.01 93.16 1.13 91.82 0.19 55.21 0.09 /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default/0.flash_ctrl_hw_rma_reset.1711548754
84.39 3.55 93.14 0.28 85.24 0.63 73.35 2.67 77.55 0.00 93.46 0.30 92.29 0.47 75.71 20.50 /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default/0.flash_ctrl_mp_regions.1099436274
87.15 2.76 93.57 0.44 86.72 1.48 89.29 15.93 77.55 0.00 93.59 0.13 92.38 0.09 76.97 1.26 /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default/0.flash_ctrl_hw_sec_otp.3783799148
88.66 1.50 93.75 0.18 87.54 0.82 93.24 3.95 78.91 1.36 94.34 0.75 95.58 3.20 77.25 0.28 /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default/0.flash_ctrl_sec_cm.2541033743
89.71 1.05 93.75 0.00 88.11 0.57 93.24 0.00 78.91 0.00 94.34 0.00 96.14 0.56 83.48 6.23 /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/cover_reg_top/3.flash_ctrl_csr_mem_rw_with_rand_reset.2531051348
90.53 0.82 93.87 0.12 88.40 0.30 93.88 0.64 82.31 3.40 94.51 0.17 96.33 0.19 84.43 0.96 /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default/0.flash_ctrl_erase_suspend.2230307686
90.94 0.40 94.13 0.26 89.21 0.81 94.52 0.64 82.31 0.00 95.30 0.79 96.33 0.00 84.74 0.31 /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default/0.flash_ctrl_rw_evict_all_en.1371639107
91.32 0.39 94.13 0.00 89.27 0.06 94.52 0.00 82.31 0.00 95.30 0.00 96.33 0.00 87.39 2.65 /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/cover_reg_top/1.flash_ctrl_csr_bit_bash.2708960698
91.62 0.30 94.14 0.02 89.29 0.02 94.52 0.00 84.35 2.04 95.34 0.04 96.33 0.00 87.39 0.00 /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default/50.flash_ctrl_otp_reset.572710968
91.93 0.30 94.31 0.17 89.59 0.30 95.18 0.66 85.03 0.68 95.56 0.21 96.33 0.00 87.48 0.09 /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default/0.flash_ctrl_rma_err.1594722586
92.23 0.30 94.31 0.00 89.62 0.03 95.18 0.00 87.07 2.04 95.56 0.00 96.33 0.00 87.52 0.03 /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default/3.flash_ctrl_otp_reset.2013004297
92.48 0.26 94.36 0.04 89.94 0.32 95.66 0.48 87.07 0.00 95.71 0.15 96.33 0.00 88.32 0.80 /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default/0.flash_ctrl_fetch_code.1315220989
92.72 0.23 94.36 0.00 89.94 0.00 95.66 0.00 87.07 0.00 95.71 0.00 96.33 0.00 89.95 1.63 /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/cover_reg_top/9.flash_ctrl_intr_test.2592878063
92.93 0.21 94.43 0.07 90.12 0.17 95.78 0.11 87.07 0.00 95.88 0.17 96.33 0.00 90.91 0.96 /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default/0.flash_ctrl_intr_rd_slow_flash.2973900780
93.12 0.19 94.43 0.00 90.12 0.00 95.78 0.00 88.44 1.36 95.88 0.00 96.33 0.00 90.91 0.00 /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default/2.flash_ctrl_mid_op_rst.683651058
93.31 0.19 94.44 0.01 90.17 0.06 95.81 0.03 88.44 0.00 95.90 0.02 96.33 0.00 92.11 1.20 /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/cover_reg_top/7.flash_ctrl_tl_intg_err.123692840
93.50 0.19 94.55 0.11 90.38 0.21 95.89 0.08 89.12 0.68 96.09 0.19 96.33 0.00 92.14 0.03 /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default/0.flash_ctrl_hw_prog_rma_wipe_err.3306483176
93.68 0.18 94.55 0.00 90.43 0.05 95.89 0.00 89.12 0.00 96.09 0.00 96.43 0.09 93.25 1.11 /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/cover_reg_top/1.flash_ctrl_csr_rw.1589179429
93.85 0.17 94.62 0.07 90.60 0.17 95.97 0.08 89.80 0.68 96.22 0.13 96.43 0.00 93.31 0.06 /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default/2.flash_ctrl_wr_intg.3442718529
94.00 0.15 94.77 0.15 91.47 0.87 95.97 0.00 89.80 0.00 96.22 0.00 96.43 0.00 93.37 0.06 /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/cover_reg_top/4.flash_ctrl_tl_errors.3262125934
94.14 0.14 94.84 0.07 91.70 0.23 96.19 0.22 89.80 0.00 96.35 0.13 96.52 0.09 93.59 0.22 /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default/0.flash_ctrl_invalid_op.4148568260
94.28 0.14 94.89 0.05 91.81 0.11 96.55 0.35 89.80 0.00 96.47 0.13 96.52 0.00 93.90 0.31 /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default/9.flash_ctrl_sec_info_access.3330855518
94.40 0.12 94.89 0.00 92.18 0.37 96.56 0.02 89.80 0.00 96.50 0.02 96.61 0.09 94.24 0.34 /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default/0.flash_ctrl_rw_derr.385491600
94.52 0.12 94.89 0.00 92.18 0.00 96.72 0.16 90.48 0.68 96.50 0.00 96.61 0.00 94.24 0.00 /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default/1.flash_ctrl_host_ctrl_arb.1620019104
94.64 0.12 94.99 0.10 92.29 0.10 97.17 0.45 90.48 0.00 96.50 0.00 96.61 0.00 94.42 0.18 /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default/0.flash_ctrl_alert_test.2142559370
94.75 0.11 94.99 0.00 92.30 0.01 97.17 0.00 91.16 0.68 96.50 0.00 96.61 0.00 94.51 0.09 /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default/4.flash_ctrl_derr_detect.774424558
94.86 0.11 94.99 0.00 92.31 0.01 97.24 0.06 91.84 0.68 96.52 0.02 96.61 0.00 94.51 0.00 /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default/2.flash_ctrl_otp_reset.2184913215
94.96 0.10 94.99 0.00 92.31 0.00 97.24 0.00 92.52 0.68 96.52 0.00 96.61 0.00 94.54 0.03 /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default/46.flash_ctrl_otp_reset.1812234444
95.02 0.06 94.99 0.00 92.38 0.08 97.29 0.05 92.52 0.00 96.54 0.02 96.61 0.00 94.79 0.25 /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default/0.flash_ctrl_re_evict.797826618
95.07 0.06 94.99 0.00 92.40 0.02 97.29 0.00 92.52 0.00 96.54 0.00 96.61 0.00 95.16 0.37 /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default/13.flash_ctrl_intr_rd.224353833
95.12 0.05 95.01 0.02 92.44 0.04 97.41 0.13 92.52 0.00 96.62 0.09 96.61 0.00 95.22 0.06 /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default/3.flash_ctrl_hw_prog_rma_wipe_err.2778060718
95.17 0.05 95.02 0.01 92.49 0.05 97.61 0.19 92.52 0.00 96.67 0.04 96.61 0.00 95.25 0.03 /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default/0.flash_ctrl_lcmgr_intg.2017805374
95.21 0.04 95.05 0.03 92.51 0.02 97.61 0.00 92.52 0.00 96.69 0.02 96.71 0.09 95.38 0.12 /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default/1.flash_ctrl_mp_regions.4211033874
95.25 0.04 95.05 0.00 92.51 0.00 97.61 0.00 92.52 0.00 96.69 0.00 96.99 0.28 95.38 0.00 /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/cover_reg_top/1.flash_ctrl_mem_partial_access.1517381830
95.29 0.04 95.05 0.00 92.51 0.00 97.61 0.00 92.52 0.00 96.69 0.00 96.99 0.00 95.65 0.28 /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/cover_reg_top/8.flash_ctrl_tl_intg_err.2984270213
95.33 0.04 95.05 0.00 92.59 0.09 97.67 0.06 92.52 0.00 96.69 0.00 96.99 0.00 95.78 0.12 /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default/0.flash_ctrl_oversize_error.299151715
95.36 0.04 95.05 0.00 92.67 0.08 97.85 0.18 92.52 0.00 96.69 0.00 96.99 0.00 95.78 0.00 /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default/4.flash_ctrl_hw_sec_otp.4279128077
95.39 0.03 95.05 0.01 92.81 0.14 97.85 0.00 92.52 0.00 96.73 0.04 96.99 0.00 95.81 0.03 /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default/3.flash_ctrl_phy_arb_redun.1263649715
95.43 0.03 95.07 0.02 92.84 0.03 97.85 0.00 92.52 0.00 96.82 0.09 96.99 0.00 95.90 0.09 /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default/3.flash_ctrl_hw_read_seed_err.3237475264
95.46 0.03 95.13 0.05 92.86 0.02 97.91 0.06 92.52 0.00 96.86 0.04 96.99 0.00 95.93 0.03 /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default/6.flash_ctrl_disable.1318121222
95.48 0.03 95.13 0.00 92.98 0.12 97.91 0.00 92.52 0.00 96.86 0.00 96.99 0.00 95.99 0.06 /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/cover_reg_top/7.flash_ctrl_tl_errors.568852472
95.51 0.03 95.13 0.00 93.06 0.08 97.93 0.02 92.52 0.00 96.86 0.00 96.99 0.00 96.09 0.09 /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default/0.flash_ctrl_ro_derr.3608882933
95.53 0.02 95.13 0.00 93.08 0.02 97.98 0.05 92.52 0.00 96.86 0.00 96.99 0.00 96.18 0.09 /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default/0.flash_ctrl_intr_rd.233608578
95.55 0.02 95.13 0.00 93.08 0.00 97.98 0.00 92.52 0.00 96.86 0.00 96.99 0.00 96.33 0.15 /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/cover_reg_top/0.flash_ctrl_csr_bit_bash.1391635218
95.58 0.02 95.13 0.00 93.08 0.00 97.98 0.00 92.52 0.00 96.86 0.00 96.99 0.00 96.49 0.15 /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default/7.flash_ctrl_re_evict.2013922260
95.60 0.02 95.13 0.01 93.14 0.07 97.98 0.00 92.52 0.00 96.90 0.04 96.99 0.00 96.52 0.03 /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default/2.flash_ctrl_phy_ack_consistency.562532590
95.62 0.02 95.15 0.02 93.22 0.08 97.98 0.00 92.52 0.00 96.94 0.04 96.99 0.00 96.52 0.00 /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default/0.flash_ctrl_access_after_disable.332295653
95.63 0.02 95.15 0.00 93.31 0.09 97.98 0.00 92.52 0.00 96.99 0.04 96.99 0.00 96.52 0.00 /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default/2.flash_ctrl_fetch_code.133324180
95.65 0.02 95.16 0.01 93.33 0.02 97.98 0.00 92.52 0.00 97.01 0.02 96.99 0.00 96.58 0.06 /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default/1.flash_ctrl_phy_host_grant_err.4267073199
95.67 0.01 95.16 0.00 93.33 0.01 98.01 0.03 92.52 0.00 97.01 0.00 96.99 0.00 96.64 0.06 /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default/0.flash_ctrl_rw_evict.1231927835
95.68 0.01 95.16 0.00 93.34 0.01 98.01 0.00 92.52 0.00 97.01 0.00 96.99 0.00 96.73 0.09 /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/cover_reg_top/0.flash_ctrl_tl_intg_err.3990181715
95.69 0.01 95.16 0.00 93.34 0.00 98.10 0.10 92.52 0.00 97.01 0.00 96.99 0.00 96.73 0.00 /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default/12.flash_ctrl_lcmgr_intg.3020074660
95.71 0.01 95.16 0.00 93.34 0.00 98.10 0.00 92.52 0.00 97.01 0.00 96.99 0.00 96.82 0.09 /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/cover_reg_top/11.flash_ctrl_intr_test.3931373919
95.72 0.01 95.17 0.01 93.35 0.01 98.10 0.00 92.52 0.00 97.05 0.04 96.99 0.00 96.86 0.03 /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default/0.flash_ctrl_hw_read_seed_err.3473143158
95.73 0.01 95.18 0.01 93.36 0.01 98.10 0.00 92.52 0.00 97.09 0.04 96.99 0.00 96.89 0.03 /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default/1.flash_ctrl_hw_prog_rma_wipe_err.2723084756
95.75 0.01 95.22 0.04 93.36 0.00 98.12 0.02 92.52 0.00 97.09 0.00 96.99 0.00 96.92 0.03 /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default/0.flash_ctrl_connect.2133240114
95.76 0.01 95.22 0.00 93.42 0.06 98.12 0.00 92.52 0.00 97.09 0.00 96.99 0.00 96.95 0.03 /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default/2.flash_ctrl_rw.2709915280
95.77 0.01 95.22 0.00 93.47 0.05 98.12 0.00 92.52 0.00 97.09 0.00 96.99 0.00 96.98 0.03 /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default/0.flash_ctrl_error_prog_type.2982907950
95.78 0.01 95.22 0.00 93.48 0.01 98.19 0.06 92.52 0.00 97.09 0.00 96.99 0.00 96.98 0.00 /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default/0.flash_ctrl_error_prog_win.1253576780
95.79 0.01 95.22 0.00 93.50 0.02 98.22 0.03 92.52 0.00 97.12 0.02 96.99 0.00 96.98 0.00 /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default/3.flash_ctrl_hw_rma_reset.2170981678
95.80 0.01 95.22 0.00 93.51 0.01 98.22 0.00 92.52 0.00 97.12 0.00 96.99 0.00 97.04 0.06 /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default/0.flash_ctrl_fs_sup.2988282676
95.81 0.01 95.22 0.00 93.52 0.01 98.22 0.00 92.52 0.00 97.12 0.00 96.99 0.00 97.10 0.06 /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default/8.flash_ctrl_re_evict.1727011582
95.82 0.01 95.22 0.00 93.52 0.00 98.28 0.06 92.52 0.00 97.12 0.00 96.99 0.00 97.10 0.00 /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default/1.flash_ctrl_sec_cm.859243433
95.83 0.01 95.22 0.00 93.52 0.00 98.28 0.00 92.52 0.00 97.12 0.00 96.99 0.00 97.16 0.06 /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/cover_reg_top/11.flash_ctrl_tl_intg_err.1876402755
95.84 0.01 95.22 0.00 93.52 0.00 98.28 0.00 92.52 0.00 97.12 0.00 96.99 0.00 97.23 0.06 /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/cover_reg_top/14.flash_ctrl_tl_intg_err.2263987491
95.85 0.01 95.22 0.00 93.52 0.00 98.28 0.00 92.52 0.00 97.12 0.00 96.99 0.00 97.29 0.06 /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default/10.flash_ctrl_re_evict.95269151
95.86 0.01 95.22 0.00 93.52 0.00 98.28 0.00 92.52 0.00 97.12 0.00 96.99 0.00 97.35 0.06 /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default/10.flash_ctrl_sec_info_access.2281169117
95.86 0.01 95.22 0.00 93.52 0.00 98.28 0.00 92.52 0.00 97.12 0.00 96.99 0.00 97.41 0.06 /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default/14.flash_ctrl_sec_info_access.3285474283
95.87 0.01 95.22 0.00 93.52 0.00 98.28 0.00 92.52 0.00 97.12 0.00 96.99 0.00 97.47 0.06 /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default/18.flash_ctrl_sec_info_access.2074310429
95.88 0.01 95.22 0.00 93.52 0.00 98.28 0.00 92.52 0.00 97.12 0.00 96.99 0.00 97.53 0.06 /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default/28.flash_ctrl_rw_evict_all_en.2036784077
95.89 0.01 95.22 0.00 93.52 0.00 98.28 0.00 92.52 0.00 97.12 0.00 96.99 0.00 97.60 0.06 /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default/41.flash_ctrl_sec_info_access.3000930557
95.90 0.01 95.22 0.00 93.57 0.06 98.28 0.00 92.52 0.00 97.12 0.00 96.99 0.00 97.60 0.00 /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default/1.flash_ctrl_rd_intg.2561685904
95.91 0.01 95.22 0.00 93.62 0.05 98.28 0.00 92.52 0.00 97.12 0.00 96.99 0.00 97.60 0.00 /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default/0.flash_ctrl_phy_arb_redun.3977410483
95.91 0.01 95.22 0.00 93.63 0.01 98.28 0.00 92.52 0.00 97.12 0.00 96.99 0.00 97.63 0.03 /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/cover_reg_top/15.flash_ctrl_tl_errors.2655165902
95.92 0.01 95.22 0.00 93.64 0.01 98.28 0.00 92.52 0.00 97.12 0.00 96.99 0.00 97.66 0.03 /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/cover_reg_top/2.flash_ctrl_intr_test.1939940751
95.92 0.01 95.22 0.00 93.65 0.01 98.28 0.00 92.52 0.00 97.12 0.00 96.99 0.00 97.69 0.03 /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default/19.flash_ctrl_rw_evict.15937201
95.93 0.01 95.22 0.00 93.66 0.01 98.28 0.00 92.52 0.00 97.12 0.00 96.99 0.00 97.72 0.03 /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default/2.flash_ctrl_error_mp.2989159040
95.93 0.01 95.22 0.00 93.70 0.04 98.28 0.00 92.52 0.00 97.12 0.00 96.99 0.00 97.72 0.00 /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default/4.flash_ctrl_phy_arb_redun.2536001606
95.94 0.01 95.22 0.00 93.70 0.00 98.31 0.03 92.52 0.00 97.12 0.00 96.99 0.00 97.72 0.00 /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default/0.flash_ctrl_otp_reset.2934197652
95.94 0.01 95.22 0.00 93.70 0.00 98.31 0.00 92.52 0.00 97.12 0.00 96.99 0.00 97.75 0.03 /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/cover_reg_top/15.flash_ctrl_tl_intg_err.1156469350
95.95 0.01 95.22 0.00 93.70 0.00 98.31 0.00 92.52 0.00 97.12 0.00 96.99 0.00 97.78 0.03 /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/cover_reg_top/17.flash_ctrl_tl_intg_err.729279780
95.95 0.01 95.22 0.00 93.70 0.00 98.31 0.00 92.52 0.00 97.12 0.00 96.99 0.00 97.81 0.03 /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default/0.flash_ctrl_config_regwen.2190368723
95.96 0.01 95.22 0.00 93.70 0.00 98.31 0.00 92.52 0.00 97.12 0.00 96.99 0.00 97.84 0.03 /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default/0.flash_ctrl_disable.1569273664
95.96 0.01 95.22 0.00 93.70 0.00 98.31 0.00 92.52 0.00 97.12 0.00 96.99 0.00 97.87 0.03 /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default/1.flash_ctrl_disable.2291310558
95.97 0.01 95.22 0.00 93.70 0.00 98.31 0.00 92.52 0.00 97.12 0.00 96.99 0.00 97.90 0.03 /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default/1.flash_ctrl_hw_rma_reset.3287703478
95.97 0.01 95.22 0.00 93.70 0.00 98.31 0.00 92.52 0.00 97.12 0.00 96.99 0.00 97.93 0.03 /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default/1.flash_ctrl_rw_evict_all_en.2963505282
95.97 0.01 95.22 0.00 93.70 0.00 98.31 0.00 92.52 0.00 97.12 0.00 96.99 0.00 97.97 0.03 /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default/11.flash_ctrl_rw_evict_all_en.1538632203
95.98 0.01 95.22 0.00 93.70 0.00 98.31 0.00 92.52 0.00 97.12 0.00 96.99 0.00 98.00 0.03 /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default/13.flash_ctrl_re_evict.4228070590
95.98 0.01 95.22 0.00 93.70 0.00 98.31 0.00 92.52 0.00 97.12 0.00 96.99 0.00 98.03 0.03 /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default/15.flash_ctrl_sec_info_access.935337526
95.99 0.01 95.22 0.00 93.70 0.00 98.31 0.00 92.52 0.00 97.12 0.00 96.99 0.00 98.06 0.03 /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default/17.flash_ctrl_disable.1797762860
95.99 0.01 95.22 0.00 93.70 0.00 98.31 0.00 92.52 0.00 97.12 0.00 96.99 0.00 98.09 0.03 /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default/19.flash_ctrl_disable.3597860579
96.00 0.01 95.22 0.00 93.70 0.00 98.31 0.00 92.52 0.00 97.12 0.00 96.99 0.00 98.12 0.03 /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default/21.flash_ctrl_disable.4179771433
96.00 0.01 95.22 0.00 93.70 0.00 98.31 0.00 92.52 0.00 97.12 0.00 96.99 0.00 98.15 0.03 /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default/23.flash_ctrl_disable.3923813954
96.00 0.01 95.22 0.00 93.73 0.03 98.31 0.00 92.52 0.00 97.12 0.00 96.99 0.00 98.15 0.00 /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default/0.flash_ctrl_intr_wr.4195374985
96.01 0.01 95.22 0.00 93.74 0.02 98.31 0.00 92.52 0.00 97.12 0.00 96.99 0.00 98.15 0.00 /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default/1.flash_ctrl_phy_ack_consistency.3395379378
96.01 0.01 95.22 0.00 93.76 0.02 98.31 0.00 92.52 0.00 97.12 0.00 96.99 0.00 98.15 0.00 /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default/11.flash_ctrl_rw.3393425776
96.01 0.01 95.22 0.00 93.77 0.01 98.31 0.00 92.52 0.00 97.12 0.00 96.99 0.00 98.15 0.00 /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default/0.flash_ctrl_host_ctrl_arb.4207193962
96.01 0.01 95.22 0.00 93.78 0.01 98.31 0.00 92.52 0.00 97.12 0.00 96.99 0.00 98.15 0.00 /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default/1.flash_ctrl_host_dir_rd.3643636202
96.01 0.01 95.22 0.00 93.79 0.01 98.31 0.00 92.52 0.00 97.12 0.00 96.99 0.00 98.15 0.00 /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default/2.flash_ctrl_access_after_disable.1430416810
96.02 0.01 95.22 0.00 93.80 0.01 98.31 0.00 92.52 0.00 97.12 0.00 96.99 0.00 98.15 0.00 /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default/5.flash_ctrl_ro_derr.762291863
96.02 0.01 95.22 0.00 93.81 0.01 98.31 0.00 92.52 0.00 97.12 0.00 96.99 0.00 98.15 0.00 /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default/7.flash_ctrl_rw_derr.576687754
96.02 0.01 95.22 0.00 93.82 0.01 98.31 0.00 92.52 0.00 97.12 0.00 96.99 0.00 98.15 0.00 /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default/9.flash_ctrl_ro_serr.3914422711

Tests that do not contribute to grading

Name
/workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/cover_reg_top/0.flash_ctrl_csr_aliasing.1090960426
/workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/cover_reg_top/0.flash_ctrl_csr_hw_reset.3803032990
/workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/cover_reg_top/0.flash_ctrl_csr_rw.3794187592
/workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/cover_reg_top/0.flash_ctrl_intr_test.214722897
/workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/cover_reg_top/0.flash_ctrl_mem_partial_access.513661652
/workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/cover_reg_top/0.flash_ctrl_mem_walk.2271515953
/workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/cover_reg_top/0.flash_ctrl_same_csr_outstanding.2773485973
/workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/cover_reg_top/0.flash_ctrl_shadow_reg_errors.3421707932
/workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/cover_reg_top/0.flash_ctrl_shadow_reg_errors_with_csr_rw.746065697
/workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/cover_reg_top/0.flash_ctrl_tl_errors.4169734088
/workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/cover_reg_top/1.flash_ctrl_csr_aliasing.3827173029
/workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/cover_reg_top/1.flash_ctrl_csr_hw_reset.1928728843
/workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/cover_reg_top/1.flash_ctrl_csr_mem_rw_with_rand_reset.3548048011
/workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/cover_reg_top/1.flash_ctrl_intr_test.1397306468
/workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/cover_reg_top/1.flash_ctrl_mem_walk.4055884636
/workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/cover_reg_top/1.flash_ctrl_same_csr_outstanding.3764980231
/workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/cover_reg_top/1.flash_ctrl_shadow_reg_errors.2435159909
/workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/cover_reg_top/1.flash_ctrl_shadow_reg_errors_with_csr_rw.560539192
/workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/cover_reg_top/1.flash_ctrl_tl_errors.2420659361
/workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/cover_reg_top/1.flash_ctrl_tl_intg_err.122770950
/workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/cover_reg_top/10.flash_ctrl_csr_mem_rw_with_rand_reset.688565505
/workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/cover_reg_top/10.flash_ctrl_csr_rw.1642102740
/workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/cover_reg_top/10.flash_ctrl_intr_test.2569195700
/workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/cover_reg_top/10.flash_ctrl_same_csr_outstanding.763534728
/workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/cover_reg_top/10.flash_ctrl_shadow_reg_errors.2577547062
/workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/cover_reg_top/10.flash_ctrl_shadow_reg_errors_with_csr_rw.1683859580
/workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/cover_reg_top/10.flash_ctrl_tl_errors.1553356300
/workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/cover_reg_top/10.flash_ctrl_tl_intg_err.3667890924
/workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/cover_reg_top/11.flash_ctrl_csr_mem_rw_with_rand_reset.1724038004
/workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/cover_reg_top/11.flash_ctrl_csr_rw.4198078671
/workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/cover_reg_top/11.flash_ctrl_same_csr_outstanding.1550721450
/workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/cover_reg_top/11.flash_ctrl_shadow_reg_errors.3929688799
/workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/cover_reg_top/11.flash_ctrl_shadow_reg_errors_with_csr_rw.2336557389
/workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/cover_reg_top/11.flash_ctrl_tl_errors.1006019162
/workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/cover_reg_top/12.flash_ctrl_csr_mem_rw_with_rand_reset.4014616435
/workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/cover_reg_top/12.flash_ctrl_csr_rw.1426288686
/workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/cover_reg_top/12.flash_ctrl_intr_test.3330162473
/workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/cover_reg_top/12.flash_ctrl_same_csr_outstanding.1146411096
/workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/cover_reg_top/12.flash_ctrl_shadow_reg_errors.3229948108
/workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/cover_reg_top/12.flash_ctrl_shadow_reg_errors_with_csr_rw.2301433028
/workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/cover_reg_top/12.flash_ctrl_tl_errors.518417560
/workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/cover_reg_top/12.flash_ctrl_tl_intg_err.880758982
/workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/cover_reg_top/13.flash_ctrl_csr_mem_rw_with_rand_reset.1588615427
/workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/cover_reg_top/13.flash_ctrl_csr_rw.2084028337
/workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/cover_reg_top/13.flash_ctrl_intr_test.616921876
/workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/cover_reg_top/13.flash_ctrl_same_csr_outstanding.1563009858
/workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/cover_reg_top/13.flash_ctrl_shadow_reg_errors.2331632848
/workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/cover_reg_top/13.flash_ctrl_shadow_reg_errors_with_csr_rw.3930784015
/workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/cover_reg_top/13.flash_ctrl_tl_errors.1633743430
/workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/cover_reg_top/13.flash_ctrl_tl_intg_err.857045643
/workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/cover_reg_top/14.flash_ctrl_csr_mem_rw_with_rand_reset.2463269681
/workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/cover_reg_top/14.flash_ctrl_csr_rw.1406497994
/workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/cover_reg_top/14.flash_ctrl_intr_test.1347286220
/workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/cover_reg_top/14.flash_ctrl_same_csr_outstanding.2362792968
/workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/cover_reg_top/14.flash_ctrl_shadow_reg_errors.1126992482
/workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/cover_reg_top/14.flash_ctrl_shadow_reg_errors_with_csr_rw.4118350020
/workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/cover_reg_top/14.flash_ctrl_tl_errors.2138410110
/workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/cover_reg_top/15.flash_ctrl_csr_mem_rw_with_rand_reset.4153311702
/workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/cover_reg_top/15.flash_ctrl_csr_rw.4263313316
/workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/cover_reg_top/15.flash_ctrl_intr_test.545328526
/workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/cover_reg_top/15.flash_ctrl_same_csr_outstanding.725681240
/workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/cover_reg_top/15.flash_ctrl_shadow_reg_errors.3784771971
/workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/cover_reg_top/15.flash_ctrl_shadow_reg_errors_with_csr_rw.3440639436
/workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/cover_reg_top/16.flash_ctrl_csr_mem_rw_with_rand_reset.2881715722
/workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/cover_reg_top/16.flash_ctrl_csr_rw.2909225648
/workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/cover_reg_top/16.flash_ctrl_intr_test.458326130
/workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/cover_reg_top/16.flash_ctrl_same_csr_outstanding.2399121928
/workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/cover_reg_top/16.flash_ctrl_shadow_reg_errors.344820960
/workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/cover_reg_top/16.flash_ctrl_shadow_reg_errors_with_csr_rw.4150474225
/workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/cover_reg_top/16.flash_ctrl_tl_errors.983398815
/workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/cover_reg_top/16.flash_ctrl_tl_intg_err.657249235
/workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/cover_reg_top/17.flash_ctrl_csr_mem_rw_with_rand_reset.3386429217
/workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/cover_reg_top/17.flash_ctrl_csr_rw.2118412463
/workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/cover_reg_top/17.flash_ctrl_intr_test.2783453313
/workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/cover_reg_top/17.flash_ctrl_same_csr_outstanding.109315400
/workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/cover_reg_top/17.flash_ctrl_shadow_reg_errors.592758634
/workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/cover_reg_top/17.flash_ctrl_shadow_reg_errors_with_csr_rw.3121788022
/workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/cover_reg_top/17.flash_ctrl_tl_errors.4221187106
/workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/cover_reg_top/18.flash_ctrl_csr_mem_rw_with_rand_reset.2328077105
/workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/cover_reg_top/18.flash_ctrl_csr_rw.543431629
/workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/cover_reg_top/18.flash_ctrl_intr_test.2287425852
/workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/cover_reg_top/18.flash_ctrl_same_csr_outstanding.17625016
/workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/cover_reg_top/18.flash_ctrl_shadow_reg_errors.402998615
/workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/cover_reg_top/18.flash_ctrl_shadow_reg_errors_with_csr_rw.4231640000
/workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/cover_reg_top/18.flash_ctrl_tl_errors.3772704976
/workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/cover_reg_top/18.flash_ctrl_tl_intg_err.148681204
/workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/cover_reg_top/19.flash_ctrl_csr_mem_rw_with_rand_reset.2040878249
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Total test records in report: 1258
tests.html | tests1.html | tests2.html | tests3.html | tests4.html | tests5.html | tests6.html | tests7.html | tests8.html | tests9.html | tests10.html | tests11.html | tests12.html | tests13.html | tests14.html | tests15.html | tests16.html | tests17.html | tests18.html | tests19.html | tests20.html | tests21.html | tests22.html | tests23.html | tests24.html | tests25.html | tests26.html
TEST NOTEST LOCATIONTEST NAMESTATUSSTARTEDFINISHEDSIMULATION TIME
T1 /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default/0.flash_ctrl_smoke_hw.3877036004 Oct 03 07:04:58 AM UTC 24 Oct 03 07:05:41 AM UTC 24 24858300 ps
T2 /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default/0.flash_ctrl_sw_op.2071150480 Oct 03 07:04:59 AM UTC 24 Oct 03 07:05:42 AM UTC 24 52188200 ps
T3 /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default/0.flash_ctrl_fetch_code.1315220989 Oct 03 07:05:43 AM UTC 24 Oct 03 07:06:21 AM UTC 24 303245500 ps
T10 /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default/0.flash_ctrl_hw_sec_otp.3783799148 Oct 03 07:05:01 AM UTC 24 Oct 03 07:07:09 AM UTC 24 3470743000 ps
T11 /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default/0.flash_ctrl_host_dir_rd.2721266304 Oct 03 07:04:59 AM UTC 24 Oct 03 07:07:56 AM UTC 24 65254100 ps
T16 /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default/0.flash_ctrl_rd_buff_evict.1564749490 Oct 03 07:04:59 AM UTC 24 Oct 03 07:08:02 AM UTC 24 5174285900 ps
T4 /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default/0.flash_ctrl_otp_reset.2934197652 Oct 03 07:05:08 AM UTC 24 Oct 03 07:08:10 AM UTC 24 582161100 ps
T17 /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default/0.flash_ctrl_smoke.2704958611 Oct 03 07:04:57 AM UTC 24 Oct 03 07:09:21 AM UTC 24 62963700 ps
T18 /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default/0.flash_ctrl_invalid_op.4148568260 Oct 03 07:08:03 AM UTC 24 Oct 03 07:09:33 AM UTC 24 5446843500 ps
T19 /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default/0.flash_ctrl_mid_op_rst.2467602662 Oct 03 07:08:10 AM UTC 24 Oct 03 07:09:54 AM UTC 24 2585929600 ps
T59 /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default/0.flash_ctrl_write_word_sweep.2740653881 Oct 03 07:09:35 AM UTC 24 Oct 03 07:09:59 AM UTC 24 41622700 ps
T58 /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default/0.flash_ctrl_read_word_sweep.2215506411 Oct 03 07:09:55 AM UTC 24 Oct 03 07:10:18 AM UTC 24 29607300 ps
T67 /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default/0.flash_ctrl_wo.2430873485 Oct 03 07:09:21 AM UTC 24 Oct 03 07:11:39 AM UTC 24 9093085200 ps
T12 /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default/0.flash_ctrl_ro.1251542247 Oct 03 07:10:01 AM UTC 24 Oct 03 07:12:07 AM UTC 24 1460737300 ps
T65 /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default/0.flash_ctrl_read_word_sweep_serr.966542496 Oct 03 07:11:40 AM UTC 24 Oct 03 07:12:14 AM UTC 24 159125000 ps
T28 /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default/0.flash_ctrl_rand_ops.533546685 Oct 03 07:04:59 AM UTC 24 Oct 03 07:12:21 AM UTC 24 87750200 ps
T26 /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default/0.flash_ctrl_erase_suspend.2230307686 Oct 03 07:05:04 AM UTC 24 Oct 03 07:13:25 AM UTC 24 6318445900 ps
T45 /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default/0.flash_ctrl_serr_counter.3270505286 Oct 03 07:12:21 AM UTC 24 Oct 03 07:13:44 AM UTC 24 565739900 ps
T64 /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default/0.flash_ctrl_read_word_sweep_derr.3246602832 Oct 03 07:13:46 AM UTC 24 Oct 03 07:14:20 AM UTC 24 32515900 ps
T27 /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default/0.flash_ctrl_phy_arb.3065359183 Oct 03 07:05:00 AM UTC 24 Oct 03 07:14:26 AM UTC 24 1634962300 ps
T46 /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default/0.flash_ctrl_ro_serr.3152686624 Oct 03 07:12:07 AM UTC 24 Oct 03 07:14:34 AM UTC 24 2517024400 ps
T66 /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default/0.flash_ctrl_serr_address.3171643358 Oct 03 07:13:27 AM UTC 24 Oct 03 07:15:14 AM UTC 24 890669100 ps
T47 /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default/0.flash_ctrl_rw_serr.333857502 Oct 03 07:12:15 AM UTC 24 Oct 03 07:16:26 AM UTC 24 1761748500 ps
T53 /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default/0.flash_ctrl_ro_derr.3608882933 Oct 03 07:14:22 AM UTC 24 Oct 03 07:16:48 AM UTC 24 2563236600 ps
T78 /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default/0.flash_ctrl_mp_regions.1099436274 Oct 03 07:05:42 AM UTC 24 Oct 03 07:17:31 AM UTC 24 15801857800 ps
T54 /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default/0.flash_ctrl_rw_derr.385491600 Oct 03 07:14:27 AM UTC 24 Oct 03 07:17:51 AM UTC 24 5301191300 ps
T69 /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default/0.flash_ctrl_rw.4157374027 Oct 03 07:10:19 AM UTC 24 Oct 03 07:18:07 AM UTC 24 3414177100 ps
T32 /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default/0.flash_ctrl_intr_wr.4195374985 Oct 03 07:16:48 AM UTC 24 Oct 03 07:18:18 AM UTC 24 4927471800 ps
T33 /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default/0.flash_ctrl_rw_evict.1231927835 Oct 03 07:18:19 AM UTC 24 Oct 03 07:19:06 AM UTC 24 29839100 ps
T50 /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default/0.flash_ctrl_oversize_error.299151715 Oct 03 07:15:11 AM UTC 24 Oct 03 07:19:08 AM UTC 24 1581774100 ps
T34 /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default/0.flash_ctrl_rw_evict_all_en.1371639107 Oct 03 07:19:07 AM UTC 24 Oct 03 07:19:56 AM UTC 24 201779500 ps
T36 /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default/0.flash_ctrl_re_evict.797826618 Oct 03 07:19:09 AM UTC 24 Oct 03 07:19:59 AM UTC 24 181150200 ps
T39 /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default/0.flash_ctrl_intr_rd.233608578 Oct 03 07:16:26 AM UTC 24 Oct 03 07:20:14 AM UTC 24 1982284200 ps
T5 /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default/0.flash_ctrl_disable.1569273664 Oct 03 07:19:57 AM UTC 24 Oct 03 07:20:31 AM UTC 24 37399200 ps
T135 /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default/0.flash_ctrl_prog_reset.1400417032 Oct 03 07:18:08 AM UTC 24 Oct 03 07:20:43 AM UTC 24 3603620000 ps
T6 /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default/0.flash_ctrl_hw_rma_reset.1711548754 Oct 03 07:05:05 AM UTC 24 Oct 03 07:20:56 AM UTC 24 100146828100 ps
T23 /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default/0.flash_ctrl_connect.2133240114 Oct 03 07:20:44 AM UTC 24 Oct 03 07:21:09 AM UTC 24 16380500 ps
T7 /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default/0.flash_ctrl_wr_intg.1107654185 Oct 03 07:21:10 AM UTC 24 Oct 03 07:21:34 AM UTC 24 164137600 ps
T40 /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default/0.flash_ctrl_sec_info_access.4268532121 Oct 03 07:20:15 AM UTC 24 Oct 03 07:21:40 AM UTC 24 2399883300 ps
T55 /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default/0.flash_ctrl_rd_intg.1684492617 Oct 03 07:20:57 AM UTC 24 Oct 03 07:21:46 AM UTC 24 162022700 ps
T8 /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default/0.flash_ctrl_access_after_disable.332295653 Oct 03 07:21:35 AM UTC 24 Oct 03 07:21:58 AM UTC 24 33799700 ps
T100 /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default/0.flash_ctrl_phy_arb_redun.3977410483 Oct 03 07:21:47 AM UTC 24 Oct 03 07:22:13 AM UTC 24 719291300 ps
T104 /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default/0.flash_ctrl_fs_sup.2988282676 Oct 03 07:21:40 AM UTC 24 Oct 03 07:22:28 AM UTC 24 1299536100 ps
T194 /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default/0.flash_ctrl_config_regwen.2190368723 Oct 03 07:22:22 AM UTC 24 Oct 03 07:22:45 AM UTC 24 57089400 ps
T133 /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default/0.flash_ctrl_lcmgr_intg.2017805374 Oct 03 07:22:37 AM UTC 24 Oct 03 07:22:59 AM UTC 24 48461600 ps
T123 /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default/0.flash_ctrl_hw_read_seed_err.3473143158 Oct 03 07:22:46 AM UTC 24 Oct 03 07:23:08 AM UTC 24 15534900 ps
T43 /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default/0.flash_ctrl_intr_rd_slow_flash.2973900780 Oct 03 07:17:33 AM UTC 24 Oct 03 07:23:16 AM UTC 24 172527534400 ps
T131 /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default/0.flash_ctrl_host_addr_infection.3878430332 Oct 03 07:23:17 AM UTC 24 Oct 03 07:24:01 AM UTC 24 27754500 ps
T401 /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default/0.flash_ctrl_rd_ooo.3764321285 Oct 03 07:23:09 AM UTC 24 Oct 03 07:24:17 AM UTC 24 99626900 ps
T113 /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default/0.flash_ctrl_alert_test.2142559370 Oct 03 07:24:02 AM UTC 24 Oct 03 07:24:25 AM UTC 24 121548400 ps
T438 /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default/1.flash_ctrl_smoke_hw.1619797413 Oct 03 07:24:25 AM UTC 24 Oct 03 07:25:05 AM UTC 24 39216400 ps
T143 /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default/0.flash_ctrl_integrity.1805505701 Oct 03 07:15:15 AM UTC 24 Oct 03 07:26:13 AM UTC 24 58709705100 ps
T105 /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default/0.flash_ctrl_hw_prog_rma_wipe_err.3306483176 Oct 03 07:23:01 AM UTC 24 Oct 03 07:26:26 AM UTC 24 10020510400 ps
T132 /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default/1.flash_ctrl_sw_op.3551353858 Oct 03 07:26:14 AM UTC 24 Oct 03 07:26:56 AM UTC 24 28081600 ps
T201 /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default/0.flash_ctrl_error_prog_win.1253576780 Oct 03 07:07:10 AM UTC 24 Oct 03 07:27:39 AM UTC 24 586885600 ps
T222 /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default/1.flash_ctrl_host_dir_rd.3643636202 Oct 03 07:26:26 AM UTC 24 Oct 03 07:27:55 AM UTC 24 219979500 ps
T117 /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default/1.flash_ctrl_hw_sec_otp.687919214 Oct 03 07:27:56 AM UTC 24 Oct 03 07:29:26 AM UTC 24 2011683100 ps
T223 /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default/1.flash_ctrl_smoke.483248151 Oct 03 07:24:18 AM UTC 24 Oct 03 07:30:04 AM UTC 24 90702300 ps
T68 /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default/1.flash_ctrl_rd_buff_evict.1108612134 Oct 03 07:26:58 AM UTC 24 Oct 03 07:30:27 AM UTC 24 1376609300 ps
T91 /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default/1.flash_ctrl_rand_ops.752712819 Oct 03 07:25:05 AM UTC 24 Oct 03 07:34:45 AM UTC 24 87272800 ps
T60 /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default/1.flash_ctrl_erase_suspend.3694350886 Oct 03 07:29:27 AM UTC 24 Oct 03 07:36:38 AM UTC 24 773572500 ps
T82 /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default/1.flash_ctrl_otp_reset.1826058527 Oct 03 07:34:47 AM UTC 24 Oct 03 07:38:15 AM UTC 24 51742100 ps
T49 /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default/1.flash_ctrl_fetch_code.4287852936 Oct 03 07:38:41 AM UTC 24 Oct 03 07:39:10 AM UTC 24 227913800 ps
T399 /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default/1.flash_ctrl_read_word_sweep_serr.3356737718 Oct 03 07:38:54 AM UTC 24 Oct 03 07:39:30 AM UTC 24 39281500 ps
T29 /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default/0.flash_ctrl_rma_err.1594722586 Oct 03 07:22:28 AM UTC 24 Oct 03 07:39:32 AM UTC 24 79029375400 ps
T398 /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default/1.flash_ctrl_read_word_sweep_derr.2367060930 Oct 03 07:39:05 AM UTC 24 Oct 03 07:39:40 AM UTC 24 124718400 ps
T83 /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default/1.flash_ctrl_prog_reset.2665047045 Oct 03 07:39:23 AM UTC 24 Oct 03 07:39:45 AM UTC 24 20236400 ps
T118 /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default/1.flash_ctrl_disable.2291310558 Oct 03 07:39:32 AM UTC 24 Oct 03 07:40:07 AM UTC 24 16862000 ps
T260 /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default/1.flash_ctrl_serr_counter.3171811199 Oct 03 07:39:01 AM UTC 24 Oct 03 07:40:07 AM UTC 24 2294219100 ps
T24 /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default/1.flash_ctrl_connect.2569092386 Oct 03 07:39:45 AM UTC 24 Oct 03 07:40:12 AM UTC 24 15693100 ps
T144 /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default/1.flash_ctrl_invalid_op.4271985281 Oct 03 07:38:50 AM UTC 24 Oct 03 07:40:13 AM UTC 24 3417184700 ps
T9 /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default/1.flash_ctrl_access_after_disable.2978022573 Oct 03 07:39:48 AM UTC 24 Oct 03 07:40:13 AM UTC 24 18112600 ps
T35 /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default/1.flash_ctrl_rw_evict.2722865060 Oct 03 07:39:26 AM UTC 24 Oct 03 07:40:15 AM UTC 24 32166900 ps
T20 /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default/1.flash_ctrl_wr_intg.2468916285 Oct 03 07:39:48 AM UTC 24 Oct 03 07:40:16 AM UTC 24 581480800 ps
T48 /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default/1.flash_ctrl_rw_evict_all_en.2963505282 Oct 03 07:39:27 AM UTC 24 Oct 03 07:40:17 AM UTC 24 80664500 ps
T195 /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default/1.flash_ctrl_phy_host_grant_err.4267073199 Oct 03 07:40:00 AM UTC 24 Oct 03 07:40:22 AM UTC 24 20820500 ps
T258 /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default/1.flash_ctrl_re_evict.354102470 Oct 03 07:39:31 AM UTC 24 Oct 03 07:40:25 AM UTC 24 728997800 ps
T215 /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default/1.flash_ctrl_config_regwen.38844776 Oct 03 07:40:08 AM UTC 24 Oct 03 07:40:30 AM UTC 24 51803700 ps
T197 /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default/1.flash_ctrl_phy_ack_consistency.3395379378 Oct 03 07:40:08 AM UTC 24 Oct 03 07:40:31 AM UTC 24 88730600 ps
T206 /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default/1.flash_ctrl_ro.935287200 Oct 03 07:38:52 AM UTC 24 Oct 03 07:40:59 AM UTC 24 963392100 ps
T30 /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default/0.flash_ctrl_hw_rma.963337031 Oct 03 07:05:04 AM UTC 24 Oct 03 07:40:35 AM UTC 24 543603759900 ps
T97 /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default/1.flash_ctrl_phy_arb_redun.298056034 Oct 03 07:39:58 AM UTC 24 Oct 03 07:40:37 AM UTC 24 835255500 ps
T75 /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default/1.flash_ctrl_mid_op_rst.708297360 Oct 03 07:38:51 AM UTC 24 Oct 03 07:40:37 AM UTC 24 3294362900 ps
T84 /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default/1.flash_ctrl_hw_read_seed_err.3705813224 Oct 03 07:40:13 AM UTC 24 Oct 03 07:40:38 AM UTC 24 50340200 ps
T202 /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default/1.flash_ctrl_rd_intg.2561685904 Oct 03 07:39:46 AM UTC 24 Oct 03 07:40:38 AM UTC 24 69156600 ps
T175 /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default/1.flash_ctrl_lcmgr_intg.2767695049 Oct 03 07:40:13 AM UTC 24 Oct 03 07:40:38 AM UTC 24 99480000 ps
T145 /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default/1.flash_ctrl_fs_sup.784913135 Oct 03 07:39:54 AM UTC 24 Oct 03 07:40:41 AM UTC 24 1220412400 ps
T114 /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default/1.flash_ctrl_alert_test.4032540416 Oct 03 07:40:19 AM UTC 24 Oct 03 07:40:41 AM UTC 24 36297100 ps
T37 /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default/1.flash_ctrl_intr_wr.1526915490 Oct 03 07:39:15 AM UTC 24 Oct 03 07:40:53 AM UTC 24 10841481500 ps
T407 /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default/1.flash_ctrl_serr_address.372830027 Oct 03 07:39:02 AM UTC 24 Oct 03 07:40:54 AM UTC 24 3466470400 ps
T409 /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default/1.flash_ctrl_host_addr_infection.1635992464 Oct 03 07:40:17 AM UTC 24 Oct 03 07:41:04 AM UTC 24 28062900 ps
T165 /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default/1.flash_ctrl_sec_info_access.1736535771 Oct 03 07:39:39 AM UTC 24 Oct 03 07:41:08 AM UTC 24 1783941400 ps
T439 /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default/2.flash_ctrl_smoke_hw.366907065 Oct 03 07:40:24 AM UTC 24 Oct 03 07:41:12 AM UTC 24 16453200 ps
T440 /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default/2.flash_ctrl_sw_op.2835422147 Oct 03 07:40:31 AM UTC 24 Oct 03 07:41:17 AM UTC 24 37027300 ps
T51 /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default/2.flash_ctrl_fetch_code.133324180 Oct 03 07:40:43 AM UTC 24 Oct 03 07:41:21 AM UTC 24 525379000 ps
T116 /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default/1.flash_ctrl_ro_serr.1909326468 Oct 03 07:38:57 AM UTC 24 Oct 03 07:41:22 AM UTC 24 594855300 ps
T31 /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default/1.flash_ctrl_phy_arb.2199439927 Oct 03 07:27:40 AM UTC 24 Oct 03 07:41:42 AM UTC 24 2851767900 ps
T405 /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default/2.flash_ctrl_read_word_sweep_serr.3254721386 Oct 03 07:41:17 AM UTC 24 Oct 03 07:41:52 AM UTC 24 59818500 ps
T411 /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default/2.flash_ctrl_read_word_sweep_derr.3453386618 Oct 03 07:41:22 AM UTC 24 Oct 03 07:41:56 AM UTC 24 23368300 ps
T396 /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default/1.flash_ctrl_wo.41020645 Oct 03 07:38:52 AM UTC 24 Oct 03 07:41:58 AM UTC 24 2373990400 ps
T199 /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default/1.flash_ctrl_ro_derr.2850575365 Oct 03 07:39:07 AM UTC 24 Oct 03 07:42:13 AM UTC 24 1269571600 ps
T166 /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default/1.flash_ctrl_hw_prog_rma_wipe_err.2723084756 Oct 03 07:40:16 AM UTC 24 Oct 03 07:42:14 AM UTC 24 10019788900 ps
T44 /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default/1.flash_ctrl_intr_rd_slow_flash.3872416113 Oct 03 07:39:20 AM UTC 24 Oct 03 07:42:19 AM UTC 24 6094608300 ps
T404 /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default/2.flash_ctrl_serr_address.2595006985 Oct 03 07:41:21 AM UTC 24 Oct 03 07:42:37 AM UTC 24 3038210500 ps
T441 /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default/2.flash_ctrl_host_dir_rd.3247765472 Oct 03 07:40:32 AM UTC 24 Oct 03 07:42:37 AM UTC 24 62921000 ps
T406 /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default/2.flash_ctrl_serr_counter.4098746368 Oct 03 07:41:19 AM UTC 24 Oct 03 07:42:39 AM UTC 24 424955400 ps
T237 /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default/1.flash_ctrl_rw_derr.365275221 Oct 03 07:39:07 AM UTC 24 Oct 03 07:42:40 AM UTC 24 4265921800 ps
T73 /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default/2.flash_ctrl_disable.1947917389 Oct 03 07:42:16 AM UTC 24 Oct 03 07:42:49 AM UTC 24 57655900 ps
T146 /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default/2.flash_ctrl_invalid_op.1650831211 Oct 03 07:40:57 AM UTC 24 Oct 03 07:42:53 AM UTC 24 3429730700 ps
T208 /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default/2.flash_ctrl_rw_evict_all_en.1837281938 Oct 03 07:42:14 AM UTC 24 Oct 03 07:43:01 AM UTC 24 37338200 ps
T442 /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default/2.flash_ctrl_rw_evict.237813024 Oct 03 07:42:00 AM UTC 24 Oct 03 07:43:01 AM UTC 24 28615700 ps
T61 /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default/2.flash_ctrl_mid_op_rst.683651058 Oct 03 07:41:00 AM UTC 24 Oct 03 07:43:03 AM UTC 24 1898435200 ps
T147 /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default/2.flash_ctrl_re_evict.4048062275 Oct 03 07:42:14 AM UTC 24 Oct 03 07:43:03 AM UTC 24 118213000 ps
T25 /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default/2.flash_ctrl_connect.915976422 Oct 03 07:42:40 AM UTC 24 Oct 03 07:43:08 AM UTC 24 43559400 ps
T207 /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default/2.flash_ctrl_ro.2666289360 Oct 03 07:41:09 AM UTC 24 Oct 03 07:43:13 AM UTC 24 639718800 ps
T275 /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default/1.flash_ctrl_oversize_error.1653945234 Oct 03 07:39:10 AM UTC 24 Oct 03 07:43:21 AM UTC 24 4506501000 ps
T21 /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default/2.flash_ctrl_wr_intg.3442718529 Oct 03 07:42:50 AM UTC 24 Oct 03 07:43:22 AM UTC 24 69923300 ps
T22 /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default/2.flash_ctrl_access_after_disable.1430416810 Oct 03 07:42:54 AM UTC 24 Oct 03 07:43:22 AM UTC 24 38458200 ps
T301 /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default/2.flash_ctrl_wo.1018686846 Oct 03 07:41:05 AM UTC 24 Oct 03 07:47:06 AM UTC 24 25528113600 ps
T38 /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default/2.flash_ctrl_intr_wr.673581278 Oct 03 07:41:55 AM UTC 24 Oct 03 07:43:28 AM UTC 24 7841810400 ps
T322 /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default/1.flash_ctrl_intr_rd.2278812609 Oct 03 07:39:13 AM UTC 24 Oct 03 07:43:30 AM UTC 24 6759524500 ps
T204 /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default/2.flash_ctrl_rd_intg.3906596672 Oct 03 07:42:40 AM UTC 24 Oct 03 07:43:30 AM UTC 24 137681100 ps
T63 /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default/2.flash_ctrl_phy_ack_consistency.562532590 Oct 03 07:43:05 AM UTC 24 Oct 03 07:43:30 AM UTC 24 107365400 ps
T216 /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default/1.flash_ctrl_rw_serr.1790623598 Oct 03 07:38:59 AM UTC 24 Oct 03 07:43:31 AM UTC 24 4203659500 ps
T98 /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default/2.flash_ctrl_phy_arb_redun.4012198552 Oct 03 07:43:02 AM UTC 24 Oct 03 07:43:33 AM UTC 24 666709300 ps
T370 /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default/2.flash_ctrl_config_regwen.665302011 Oct 03 07:43:09 AM UTC 24 Oct 03 07:43:37 AM UTC 24 38816900 ps
T174 /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default/2.flash_ctrl_hw_read_seed_err.651437044 Oct 03 07:43:23 AM UTC 24 Oct 03 07:43:47 AM UTC 24 15011200 ps
T415 /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default/2.flash_ctrl_ro_serr.3017780108 Oct 03 07:41:17 AM UTC 24 Oct 03 07:43:47 AM UTC 24 2867004700 ps
T176 /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default/2.flash_ctrl_lcmgr_intg.2169033730 Oct 03 07:43:22 AM UTC 24 Oct 03 07:43:48 AM UTC 24 30018100 ps
T115 /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default/2.flash_ctrl_alert_test.786225700 Oct 03 07:43:28 AM UTC 24 Oct 03 07:43:50 AM UTC 24 76649200 ps
T128 /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default/2.flash_ctrl_otp_reset.2184913215 Oct 03 07:40:41 AM UTC 24 Oct 03 07:43:53 AM UTC 24 43490800 ps
T259 /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default/2.flash_ctrl_fs_sup.1122742893 Oct 03 07:43:02 AM UTC 24 Oct 03 07:44:11 AM UTC 24 1703219100 ps
T436 /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default/2.flash_ctrl_phy_arb.708682792 Oct 03 07:40:37 AM UTC 24 Oct 03 07:44:15 AM UTC 24 122656400 ps
T443 /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default/3.flash_ctrl_smoke_hw.1901587325 Oct 03 07:43:32 AM UTC 24 Oct 03 07:44:16 AM UTC 24 13130000 ps
T162 /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default/2.flash_ctrl_sec_info_access.676097989 Oct 03 07:42:39 AM UTC 24 Oct 03 07:44:19 AM UTC 24 2392129100 ps
T444 /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default/3.flash_ctrl_sw_op.2353573758 Oct 03 07:43:32 AM UTC 24 Oct 03 07:44:20 AM UTC 24 82491000 ps
T238 /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default/2.flash_ctrl_rd_buff_evict.1894054805 Oct 03 07:40:35 AM UTC 24 Oct 03 07:44:21 AM UTC 24 702203200 ps
T41 /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default/2.flash_ctrl_intr_rd.4150344138 Oct 03 07:41:53 AM UTC 24 Oct 03 07:44:25 AM UTC 24 579287800 ps
T402 /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default/2.flash_ctrl_host_addr_infection.3624431974 Oct 03 07:43:28 AM UTC 24 Oct 03 07:44:26 AM UTC 24 98248900 ps
T200 /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default/2.flash_ctrl_ro_derr.1852556755 Oct 03 07:41:23 AM UTC 24 Oct 03 07:44:27 AM UTC 24 7354467800 ps
T77 /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default/1.flash_ctrl_intr_wr_slow_flash.3587129414 Oct 03 07:39:22 AM UTC 24 Oct 03 07:44:42 AM UTC 24 80720790700 ps
T397 /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default/2.flash_ctrl_smoke.1365869459 Oct 03 07:40:23 AM UTC 24 Oct 03 07:44:46 AM UTC 24 69612100 ps
T400 /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default/3.flash_ctrl_smoke.3323889219 Oct 03 07:43:30 AM UTC 24 Oct 03 07:44:51 AM UTC 24 38186200 ps
T52 /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default/3.flash_ctrl_fetch_code.2159050870 Oct 03 07:44:17 AM UTC 24 Oct 03 07:44:53 AM UTC 24 132959600 ps
T445 /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default/2.flash_ctrl_intr_rd_slow_flash.2891404420 Oct 03 07:41:55 AM UTC 24 Oct 03 07:44:55 AM UTC 24 15763296200 ps
T122 /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default/2.flash_ctrl_hw_sec_otp.381119245 Oct 03 07:40:39 AM UTC 24 Oct 03 07:45:00 AM UTC 24 3294577900 ps
T446 /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default/2.flash_ctrl_prog_reset.2591128605 Oct 03 07:41:58 AM UTC 24 Oct 03 07:45:06 AM UTC 24 4078087700 ps
T414 /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default/2.flash_ctrl_rw_serr.888374974 Oct 03 07:41:18 AM UTC 24 Oct 03 07:45:11 AM UTC 24 7588412400 ps
T410 /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default/2.flash_ctrl_oversize_error.218051685 Oct 03 07:41:44 AM UTC 24 Oct 03 07:45:13 AM UTC 24 1916535600 ps
T412 /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default/3.flash_ctrl_read_word_sweep_serr.2367200269 Oct 03 07:44:54 AM UTC 24 Oct 03 07:45:29 AM UTC 24 114921200 ps
T447 /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default/3.flash_ctrl_host_dir_rd.1139921162 Oct 03 07:43:34 AM UTC 24 Oct 03 07:45:47 AM UTC 24 171362600 ps
T403 /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default/3.flash_ctrl_read_word_sweep_derr.2293775137 Oct 03 07:45:13 AM UTC 24 Oct 03 07:45:48 AM UTC 24 150768800 ps
T148 /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default/3.flash_ctrl_invalid_op.3222691646 Oct 03 07:44:26 AM UTC 24 Oct 03 07:46:15 AM UTC 24 6213050300 ps
T448 /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default/3.flash_ctrl_serr_address.1507198804 Oct 03 07:45:11 AM UTC 24 Oct 03 07:46:29 AM UTC 24 428773200 ps
T76 /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default/3.flash_ctrl_mid_op_rst.3069247656 Oct 03 07:44:28 AM UTC 24 Oct 03 07:46:33 AM UTC 24 645964600 ps
T257 /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default/3.flash_ctrl_rd_buff_evict.246661382 Oct 03 07:43:37 AM UTC 24 Oct 03 07:46:40 AM UTC 24 97487400 ps
T449 /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default/3.flash_ctrl_serr_counter.389931919 Oct 03 07:45:07 AM UTC 24 Oct 03 07:46:41 AM UTC 24 6533934600 ps
T209 /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default/2.flash_ctrl_rw_derr.3046749289 Oct 03 07:41:31 AM UTC 24 Oct 03 07:46:42 AM UTC 24 5064937300 ps
T130 /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default/1.flash_ctrl_hw_rma_reset.3287703478 Oct 03 07:30:27 AM UTC 24 Oct 03 07:46:48 AM UTC 24 40121594700 ps
T413 /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default/3.flash_ctrl_prog_reset.2143794207 Oct 03 07:46:49 AM UTC 24 Oct 03 07:47:05 AM UTC 24 80096500 ps
T450 /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default/3.flash_ctrl_phy_arb.2349594250 Oct 03 07:43:47 AM UTC 24 Oct 03 07:47:21 AM UTC 24 39996400 ps
T214 /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default/3.flash_ctrl_ro.3228677342 Oct 03 07:44:48 AM UTC 24 Oct 03 07:47:23 AM UTC 24 672598900 ps
T408 /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default/3.flash_ctrl_ro_serr.3532347593 Oct 03 07:44:56 AM UTC 24 Oct 03 07:47:30 AM UTC 24 725128800 ps
T92 /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default/3.flash_ctrl_otp_reset.2013004297 Oct 03 07:43:53 AM UTC 24 Oct 03 07:47:42 AM UTC 24 40276100 ps
T451 /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default/3.flash_ctrl_hw_sec_otp.3804132221 Oct 03 07:43:48 AM UTC 24 Oct 03 07:47:47 AM UTC 24 13704603700 ps
T452 /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default/3.flash_ctrl_rw_evict_all_en.572270066 Oct 03 07:47:07 AM UTC 24 Oct 03 07:47:47 AM UTC 24 35772600 ps
T289 /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default/3.flash_ctrl_rw_evict.201119089 Oct 03 07:47:06 AM UTC 24 Oct 03 07:47:54 AM UTC 24 39253600 ps
T453 /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default/3.flash_ctrl_disable.701320827 Oct 03 07:47:24 AM UTC 24 Oct 03 07:47:54 AM UTC 24 12861000 ps
T79 /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default/2.flash_ctrl_mp_regions.314243706 Oct 03 07:40:42 AM UTC 24 Oct 03 07:48:07 AM UTC 24 45563931400 ps
T155 /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default/3.flash_ctrl_intr_wr.1507633518 Oct 03 07:46:41 AM UTC 24 Oct 03 07:48:11 AM UTC 24 37236584400 ps
T156 /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default/3.flash_ctrl_connect.552349761 Oct 03 07:47:48 AM UTC 24 Oct 03 07:48:12 AM UTC 24 38582300 ps
T101 /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default/0.flash_ctrl_host_ctrl_arb.4207193962 Oct 03 07:05:08 AM UTC 24 Oct 03 07:48:12 AM UTC 24 301638530000 ps
T80 /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default/1.flash_ctrl_mp_regions.4211033874 Oct 03 07:38:15 AM UTC 24 Oct 03 07:48:12 AM UTC 24 145892506300 ps
T157 /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default/3.flash_ctrl_re_evict.2077333574 Oct 03 07:47:22 AM UTC 24 Oct 03 07:48:18 AM UTC 24 562469600 ps
T158 /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default/3.flash_ctrl_ro_derr.1496357862 Oct 03 07:45:30 AM UTC 24 Oct 03 07:48:23 AM UTC 24 1314230400 ps
T99 /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default/3.flash_ctrl_phy_arb_redun.1263649715 Oct 03 07:47:55 AM UTC 24 Oct 03 07:48:24 AM UTC 24 895714600 ps
T159 /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default/3.flash_ctrl_phy_host_grant_err.155775627 Oct 03 07:48:09 AM UTC 24 Oct 03 07:48:28 AM UTC 24 14084800 ps
T160 /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default/3.flash_ctrl_config_regwen.2660963814 Oct 03 07:48:13 AM UTC 24 Oct 03 07:48:32 AM UTC 24 21533900 ps
T454 /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default/3.flash_ctrl_wo.1029450400 Oct 03 07:44:42 AM UTC 24 Oct 03 07:48:34 AM UTC 24 4385146600 ps
T270 /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default/3.flash_ctrl_lcmgr_intg.1010370575 Oct 03 07:48:13 AM UTC 24 Oct 03 07:48:34 AM UTC 24 69154500 ps
T262 /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default/3.flash_ctrl_hw_read_seed_err.3237475264 Oct 03 07:48:13 AM UTC 24 Oct 03 07:48:40 AM UTC 24 15527800 ps
T455 /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default/3.flash_ctrl_fs_sup.2254284713 Oct 03 07:47:55 AM UTC 24 Oct 03 07:48:45 AM UTC 24 901628600 ps
T456 /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default/3.flash_ctrl_alert_test.4003712586 Oct 03 07:48:25 AM UTC 24 Oct 03 07:48:52 AM UTC 24 44637100 ps
T437 /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default/3.flash_ctrl_rw_serr.3856933705 Oct 03 07:45:01 AM UTC 24 Oct 03 07:48:53 AM UTC 24 5194965900 ps
T106 /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default/2.flash_ctrl_hw_prog_rma_wipe_err.1885883548 Oct 03 07:43:23 AM UTC 24 Oct 03 07:49:08 AM UTC 24 10011587900 ps
T457 /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default/3.flash_ctrl_oversize_error.3650377572 Oct 03 07:46:15 AM UTC 24 Oct 03 07:49:08 AM UTC 24 4828717000 ps
T458 /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default/4.flash_ctrl_sw_op.558319654 Oct 03 07:48:35 AM UTC 24 Oct 03 07:49:11 AM UTC 24 34789900 ps
T299 /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default/4.flash_ctrl_smoke_hw.1943935038 Oct 03 07:48:29 AM UTC 24 Oct 03 07:49:14 AM UTC 24 22550100 ps
T217 /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default/1.flash_ctrl_rw.4073608959 Oct 03 07:38:54 AM UTC 24 Oct 03 07:49:19 AM UTC 24 12001333500 ps
T379 /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default/3.flash_ctrl_sec_info_access.1130560540 Oct 03 07:47:42 AM UTC 24 Oct 03 07:49:33 AM UTC 24 13453656400 ps
T459 /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default/4.flash_ctrl_fetch_code.3651615931 Oct 03 07:49:20 AM UTC 24 Oct 03 07:49:56 AM UTC 24 198259600 ps
T188 /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default/3.flash_ctrl_hw_prog_rma_wipe_err.2778060718 Oct 03 07:48:18 AM UTC 24 Oct 03 07:50:01 AM UTC 24 10032815300 ps
T320 /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default/3.flash_ctrl_intr_rd_slow_flash.4277687055 Oct 03 07:46:43 AM UTC 24 Oct 03 07:50:08 AM UTC 24 5867397500 ps
T205 /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default/3.flash_ctrl_rw_derr.4003544015 Oct 03 07:45:48 AM UTC 24 Oct 03 07:50:08 AM UTC 24 1856950400 ps
T321 /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default/3.flash_ctrl_intr_rd.1005397958 Oct 03 07:46:34 AM UTC 24 Oct 03 07:50:10 AM UTC 24 1754995500 ps
T81 /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default/2.flash_ctrl_erase_suspend.1532184532 Oct 03 07:40:39 AM UTC 24 Oct 03 07:50:17 AM UTC 24 8874149000 ps
T90 /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default/3.flash_ctrl_mp_regions.3908081345 Oct 03 07:44:16 AM UTC 24 Oct 03 07:50:24 AM UTC 24 23993616700 ps
T302 /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default/4.flash_ctrl_smoke.241154031 Oct 03 07:48:25 AM UTC 24 Oct 03 07:50:34 AM UTC 24 39866200 ps
T460 /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default/4.flash_ctrl_phy_arb.1350042900 Oct 03 07:48:46 AM UTC 24 Oct 03 07:50:38 AM UTC 24 27440000 ps
T461 /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default/1.flash_ctrl_integrity.1508691879 Oct 03 07:39:13 AM UTC 24 Oct 03 07:50:43 AM UTC 24 17024440500 ps
T213 /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default/2.flash_ctrl_rw.2709915280 Oct 03 07:41:13 AM UTC 24 Oct 03 07:50:44 AM UTC 24 7274110400 ps
T462 /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default/2.flash_ctrl_intr_wr_slow_flash.3234115482 Oct 03 07:41:57 AM UTC 24 Oct 03 07:50:55 AM UTC 24 305046229400 ps
T300 /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default/3.flash_ctrl_stress_all.1130025110 Oct 03 07:47:48 AM UTC 24 Oct 03 07:51:00 AM UTC 24 199059200 ps
T463 /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default/4.flash_ctrl_host_dir_rd.2060977329 Oct 03 07:48:35 AM UTC 24 Oct 03 07:51:04 AM UTC 24 110878600 ps
T464 /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default/4.flash_ctrl_read_word_sweep_serr.52498103 Oct 03 07:50:39 AM UTC 24 Oct 03 07:51:05 AM UTC 24 27048600 ps
T220 /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default/2.flash_ctrl_integrity.3292823753 Oct 03 07:41:47 AM UTC 24 Oct 03 07:51:17 AM UTC 24 2975607900 ps
T465 /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default/4.flash_ctrl_read_word_sweep_derr.638906743 Oct 03 07:51:05 AM UTC 24 Oct 03 07:51:36 AM UTC 24 18968700 ps
T466 /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default/3.flash_ctrl_intr_wr_slow_flash.531721309 Oct 03 07:46:43 AM UTC 24 Oct 03 07:51:41 AM UTC 24 20276704700 ps
T86 /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default/4.flash_ctrl_mid_op_rst.2103948753 Oct 03 07:50:11 AM UTC 24 Oct 03 07:51:42 AM UTC 24 1139570200 ps
T161 /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default/4.flash_ctrl_invalid_op.3314295515 Oct 03 07:50:08 AM UTC 24 Oct 03 07:51:54 AM UTC 24 4148378700 ps
T467 /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default/4.flash_ctrl_mp_regions.3537855354 Oct 03 07:49:15 AM UTC 24 Oct 03 07:52:13 AM UTC 24 1724345100 ps
T288 /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default/4.flash_ctrl_hw_sec_otp.4279128077 Oct 03 07:48:53 AM UTC 24 Oct 03 07:52:14 AM UTC 24 27222035600 ps
T468 /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default/4.flash_ctrl_rd_buff_evict.1008521913 Oct 03 07:48:40 AM UTC 24 Oct 03 07:52:15 AM UTC 24 750933800 ps
T218 /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default/4.flash_ctrl_ro.3013094038 Oct 03 07:50:26 AM UTC 24 Oct 03 07:52:29 AM UTC 24 644902900 ps
T93 /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default/4.flash_ctrl_otp_reset.3189987264 Oct 03 07:49:10 AM UTC 24 Oct 03 07:52:34 AM UTC 24 45949700 ps
T469 /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default/0.flash_ctrl_stress_all.1633656564 Oct 03 07:20:33 AM UTC 24 Oct 03 07:52:46 AM UTC 24 309982900 ps
T470 /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default/4.flash_ctrl_serr_counter.4228986562 Oct 03 07:50:56 AM UTC 24 Oct 03 07:52:54 AM UTC 24 3060025600 ps
T471 /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default/4.flash_ctrl_serr_address.1119231178 Oct 03 07:51:01 AM UTC 24 Oct 03 07:52:55 AM UTC 24 3445371100 ps
T472 /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default/4.flash_ctrl_ro_derr.3964413927 Oct 03 07:51:05 AM UTC 24 Oct 03 07:53:14 AM UTC 24 2736124000 ps
T473 /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default/4.flash_ctrl_ro_serr.1424485892 Oct 03 07:50:44 AM UTC 24 Oct 03 07:53:27 AM UTC 24 12237741500 ps
T474 /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default/4.flash_ctrl_intr_wr.985916554 Oct 03 07:52:14 AM UTC 24 Oct 03 07:53:28 AM UTC 24 2080889600 ps
T475 /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default/4.flash_ctrl_re_evict.1046206574 Oct 03 07:52:54 AM UTC 24 Oct 03 07:53:35 AM UTC 24 128095300 ps
T74 /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default/4.flash_ctrl_disable.2412208806 Oct 03 07:52:56 AM UTC 24 Oct 03 07:53:40 AM UTC 24 11975100 ps
T345 /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default/4.flash_ctrl_rw_evict_all_en.2576510558 Oct 03 07:52:46 AM UTC 24 Oct 03 07:53:44 AM UTC 24 28325900 ps
T476 /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default/4.flash_ctrl_connect.2587916837 Oct 03 07:53:32 AM UTC 24 Oct 03 07:53:56 AM UTC 24 49390100 ps
T198 /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default/4.flash_ctrl_phy_arb_redun.2536001606 Oct 03 07:53:41 AM UTC 24 Oct 03 07:54:08 AM UTC 24 766580000 ps
T196 /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default/4.flash_ctrl_phy_host_grant_err.3096997153 Oct 03 07:53:44 AM UTC 24 Oct 03 07:54:12 AM UTC 24 44518100 ps
T294 /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default/3.flash_ctrl_rw.1221819813 Oct 03 07:44:52 AM UTC 24 Oct 03 07:54:16 AM UTC 24 18468318900 ps
T477 /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default/4.flash_ctrl_wo.1045418639 Oct 03 07:50:18 AM UTC 24 Oct 03 07:54:22 AM UTC 24 2236402800 ps
T314 /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default/4.flash_ctrl_intr_rd.997417293 Oct 03 07:51:56 AM UTC 24 Oct 03 07:54:29 AM UTC 24 2490205600 ps
T478 /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default/4.flash_ctrl_fs_sup.1087770517 Oct 03 07:53:36 AM UTC 24 Oct 03 07:54:36 AM UTC 24 902799200 ps
T263 /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default/4.flash_ctrl_hw_read_seed_err.219623377 Oct 03 07:54:17 AM UTC 24 Oct 03 07:54:36 AM UTC 24 15372400 ps
T271 /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default/4.flash_ctrl_lcmgr_intg.3246737754 Oct 03 07:54:13 AM UTC 24 Oct 03 07:54:38 AM UTC 24 35636800 ps
T479 /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default/4.flash_ctrl_config_regwen.1249149908 Oct 03 07:54:09 AM UTC 24 Oct 03 07:54:39 AM UTC 24 96972800 ps
T480 /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default/4.flash_ctrl_oversize_error.2081061140 Oct 03 07:51:42 AM UTC 24 Oct 03 07:54:44 AM UTC 24 1974240900 ps
T481 /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default/4.flash_ctrl_alert_test.371999775 Oct 03 07:54:26 AM UTC 24 Oct 03 07:54:53 AM UTC 24 53090700 ps
T191 /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default/2.flash_ctrl_hw_rma_reset.3536548330 Oct 03 07:40:39 AM UTC 24 Oct 03 07:54:57 AM UTC 24 80138748300 ps
T482 /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default/4.flash_ctrl_prog_reset.3713271552 Oct 03 07:52:30 AM UTC 24 Oct 03 07:55:04 AM UTC 24 4749015400 ps
T394 /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default/4.flash_ctrl_sec_info_access.380095253 Oct 03 07:53:28 AM UTC 24 Oct 03 07:55:26 AM UTC 24 11712601300 ps
T483 /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default/4.flash_ctrl_rw_derr.2983595819 Oct 03 07:51:18 AM UTC 24 Oct 03 07:55:32 AM UTC 24 29651341000 ps
T484 /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default/3.flash_ctrl_erase_suspend.781046236 Oct 03 07:43:49 AM UTC 24 Oct 03 07:55:38 AM UTC 24 4166668400 ps
T56 /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default/5.flash_ctrl_fetch_code.2168667783 Oct 03 07:54:54 AM UTC 24 Oct 03 07:55:50 AM UTC 24 1770821700 ps
T485 /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default/4.flash_ctrl_intr_wr_slow_flash.3790657105 Oct 03 07:52:16 AM UTC 24 Oct 03 07:55:58 AM UTC 24 44141862800 ps
T85 /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default/4.flash_ctrl_derr_detect.774424558 Oct 03 07:51:37 AM UTC 24 Oct 03 07:56:03 AM UTC 24 1112656500 ps
T434 /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default/3.flash_ctrl_integrity.705705934 Oct 03 07:46:30 AM UTC 24 Oct 03 07:56:29 AM UTC 24 3734884400 ps
T486 /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default/5.flash_ctrl_invalid_op.3419041406 Oct 03 07:55:27 AM UTC 24 Oct 03 07:56:33 AM UTC 24 6436326600 ps
T149 /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default/0.flash_ctrl_full_mem_access.4267781958 Oct 03 07:06:06 AM UTC 24 Oct 03 07:56:34 AM UTC 24 575344182100 ps
T487 /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default/5.flash_ctrl_hw_sec_otp.673214461 Oct 03 07:54:38 AM UTC 24 Oct 03 07:56:36 AM UTC 24 8390717600 ps
T192 /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default/4.flash_ctrl_hw_prog_rma_wipe_err.1121096895 Oct 03 07:54:23 AM UTC 24 Oct 03 07:56:48 AM UTC 24 10012509500 ps
T179 /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default/3.flash_ctrl_hw_rma_reset.2170981678 Oct 03 07:43:51 AM UTC 24 Oct 03 07:57:28 AM UTC 24 160170714900 ps
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