Unified Coverage Report :: Group :: flash_ctrl_env_pkg::flash_ctrl_env_cov::control_cg

Group : flash_ctrl_env_pkg::flash_ctrl_env_cov::control_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
96.77	1	100	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/default/sim-vcs/../src/lowrisc_dv_flash_ctrl_env_0.1/flash_ctrl_env_cov.sv

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Summary for Group flash_ctrl_env_pkg::flash_ctrl_env_cov::control_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	15	0	15	100.00
Crosses	16	1	15	93.75

Variables for Group flash_ctrl_env_pkg::flash_ctrl_env_cov::control_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
erase_cp	2	0	2	100.00	100	1	1	0
op_cp	4	0	4	100.00	100	1	1	0
op_evict_cp	5	0	5	100.00	100	1	1	0
part_cp	4	0	4	100.00	100	1	1	0

Crosses for Group flash_ctrl_env_pkg::flash_ctrl_env_cov::control_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
op_part_cross	16	1	15	93.75	100	1	1	0

Summary for Variable erase_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for erase_cp

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[FlashErasePage]	235914	1		T2	4		T3	54		T10	990
auto[FlashEraseBank]	263031	1		T3	6		T11	12		T16	5

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Summary for Variable op_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for op_cp

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[FlashOpRead]	247609	1		T2	2		T3	60		T10	490
auto[FlashOpProgram]	231273	1		T2	1		T10	250		T11	9
auto[FlashOpErase]	16063	1		T2	1		T10	250		T16	4
auto[FlashOpInvalid]	4000	1		T18	200		T144	200		T146	200

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Summary for Variable op_evict_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	5	0	5	100.00

User Defined Bins for op_evict_cp

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
op[FlashOpRead]	247609	1		T2	2		T3	60		T10	490
op[FlashOpProgram]	231273	1		T2	1		T10	250		T11	9
op[FlashOpErase]	16063	1		T2	1		T10	250		T16	4
read_erase_read	534	1		T16	2		T28	1		T78	6
read_prog_read	850	1		T11	8		T16	1		T17	1

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Summary for Variable part_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for part_cp

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[FlashPartData]	352522	1		T2	4		T3	60		T11	18
auto[FlashPartInfo]	138395	1		T10	990		T18	132		T67	188
auto[FlashPartInfo1]	2070	1		T18	56		T12	2		T28	5
auto[FlashPartInfo2]	5958	1		T18	60		T67	22		T12	7

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Summary for Cross op_part_cross

Samples crossed: part_cp op_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	1	15	93.75	1

Automatically Generated Cross Bins for op_part_cross

Uncovered bins

part_cp	op_cp	COUNT	AT LEAST	NUMBER
[auto[FlashPartInfo1]]	[auto[FlashOpErase]]	0	1	1

Covered bins

part_cp	op_cp	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[FlashPartData]	auto[FlashOpRead]	176154	1		T2	2		T3	60		T11	9
auto[FlashPartData]	auto[FlashOpProgram]	171796	1		T2	1		T11	9		T16	4
auto[FlashPartData]	auto[FlashOpErase]	2594	1		T2	1		T16	4		T18	54
auto[FlashPartData]	auto[FlashOpInvalid]	1978	1		T18	108		T144	106		T146	90
auto[FlashPartInfo]	auto[FlashOpRead]	67234	1		T10	490		T18	44		T12	227
auto[FlashPartInfo]	auto[FlashOpProgram]	57400	1		T10	250		T18	22		T67	188
auto[FlashPartInfo]	auto[FlashOpErase]	13083	1		T10	250		T18	22		T28	1
auto[FlashPartInfo]	auto[FlashOpInvalid]	678	1		T18	44		T144	28		T146	38
auto[FlashPartInfo1]	auto[FlashOpRead]	1288	1		T18	28		T12	2		T28	5
auto[FlashPartInfo1]	auto[FlashOpProgram]	162	1		T149	32		T139	32		T330	1
auto[FlashPartInfo1]	auto[FlashOpInvalid]	620	1		T18	28		T144	28		T146	34
auto[FlashPartInfo2]	auto[FlashOpRead]	2933	1		T18	20		T12	7		T28	2
auto[FlashPartInfo2]	auto[FlashOpProgram]	1915	1		T18	10		T67	22		T28	2
auto[FlashPartInfo2]	auto[FlashOpErase]	386	1		T18	10		T36	4		T91	1
auto[FlashPartInfo2]	auto[FlashOpInvalid]	724	1		T18	20		T144	38		T146	38