Unified Coverage Report :: Group :: flash_ctrl_env_pkg::flash_ctrl_env_cov::eviction_cg

Group : flash_ctrl_env_pkg::flash_ctrl_env_cov::eviction_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
97.62	1	100	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/default/sim-vcs/../src/lowrisc_dv_flash_ctrl_env_0.1/flash_ctrl_env_cov.sv

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Summary for Group flash_ctrl_env_pkg::flash_ctrl_env_cov::eviction_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	10	0	10	100.00
Crosses	32	1	31	96.88

Variables for Group flash_ctrl_env_pkg::flash_ctrl_env_cov::eviction_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
evic_cfg_cp	4	0	4	100.00	100	1	1	4
evic_idx_cp	4	0	4	100.00	100	1	1	0
evic_op_cp	2	0	2	100.00	100	1	1	0

Crosses for Group flash_ctrl_env_pkg::flash_ctrl_env_cov::eviction_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
evic_all_cross	32	1	31	96.88	100	1	1	0

Summary for Variable evic_cfg_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for evic_cfg_cp

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	31257	1		T2	4		T10	520		T11	36
auto[1]	24	1		T36	2		T104	4		T259	1
auto[2]	47	1		T33	2		T48	1		T81	12
auto[3]	296	1		T34	1		T36	1		T258	10

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Summary for Variable evic_idx_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for evic_idx_cp

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
evic_idx[0]	7911	1		T2	1		T10	130		T11	9
evic_idx[1]	7910	1		T2	1		T10	130		T11	9
evic_idx[2]	7902	1		T2	1		T10	130		T11	9
evic_idx[3]	7901	1		T2	1		T10	130		T11	9

---

Summary for Variable evic_op_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for evic_op_cp

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
evic_op[1]	30689	1		T2	4		T10	520		T16	12
evic_op[2]	338	1		T11	36		T16	16		T27	1

---

Summary for Cross evic_all_cross

Samples crossed: evic_idx_cp evic_op_cp evic_cfg_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	32	1	31	96.88	1

Automatically Generated Cross Bins for evic_all_cross

Uncovered bins

evic_idx_cp	evic_op_cp	evic_cfg_cp	COUNT	AT LEAST	NUMBER
[evic_idx[0]]	[evic_op[2]]	[auto[1]]	0	1	1

Covered bins

evic_idx_cp	evic_op_cp	evic_cfg_cp	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
evic_idx[0]	evic_op[1]	auto[0]	7603	1		T2	1		T10	130		T16	3
evic_idx[0]	evic_op[1]	auto[1]	3	1		T36	1		T331	2		-	-
evic_idx[0]	evic_op[1]	auto[2]	1	1		T212	1		-	-		-	-
evic_idx[0]	evic_op[1]	auto[3]	66	1		T258	1		T147	1		T157	3
evic_idx[0]	evic_op[2]	auto[0]	72	1		T11	9		T16	4		T27	1
evic_idx[0]	evic_op[2]	auto[2]	2	1		T48	1		T332	1		-	-
evic_idx[0]	evic_op[2]	auto[3]	14	1		T34	1		T333	1		T334	1
evic_idx[1]	evic_op[1]	auto[0]	7606	1		T2	1		T10	130		T16	3
evic_idx[1]	evic_op[1]	auto[1]	4	1		T331	3		T335	1		-	-
evic_idx[1]	evic_op[1]	auto[2]	3	1		T336	1		T337	1		T212	1
evic_idx[1]	evic_op[1]	auto[3]	64	1		T258	2		T147	2		T157	2
evic_idx[1]	evic_op[2]	auto[0]	70	1		T11	9		T16	4		T78	1
evic_idx[1]	evic_op[2]	auto[1]	3	1		T338	1		T339	1		T340	1
evic_idx[1]	evic_op[2]	auto[2]	2	1		T341	2		-	-		-	-
evic_idx[1]	evic_op[2]	auto[3]	9	1		T213	1		T342	1		T343	1
evic_idx[2]	evic_op[1]	auto[0]	7605	1		T2	1		T10	130		T16	3
evic_idx[2]	evic_op[1]	auto[1]	3	1		T331	3		-	-		-	-
evic_idx[2]	evic_op[1]	auto[2]	1	1		T337	1		-	-		-	-
evic_idx[2]	evic_op[1]	auto[3]	62	1		T36	1		T258	3		T147	5
evic_idx[2]	evic_op[2]	auto[0]	67	1		T11	9		T16	4		T78	1
evic_idx[2]	evic_op[2]	auto[1]	3	1		T104	2		T259	1		-	-
evic_idx[2]	evic_op[2]	auto[2]	4	1		T33	1		T344	1		T332	1
evic_idx[2]	evic_op[2]	auto[3]	8	1		T345	1		T346	1		T347	1
evic_idx[3]	evic_op[1]	auto[0]	7601	1		T2	1		T10	130		T16	3
evic_idx[3]	evic_op[1]	auto[1]	4	1		T36	1		T331	3		-	-
evic_idx[3]	evic_op[1]	auto[2]	1	1		T337	1		-	-		-	-
evic_idx[3]	evic_op[1]	auto[3]	62	1		T258	4		T147	1		T157	2
evic_idx[3]	evic_op[2]	auto[0]	68	1		T11	9		T16	4		T78	1
evic_idx[3]	evic_op[2]	auto[1]	4	1		T104	2		T348	1		T349	1
evic_idx[3]	evic_op[2]	auto[2]	1	1		T33	1		-	-		-	-
evic_idx[3]	evic_op[2]	auto[3]	11	1		T110	1		T350	1		T351	1