Summary for Variable instr_type_cp
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | 
| User Defined Bins | 
3 | 
0 | 
3 | 
100.00 | 
User Defined Bins for instr_type_cp
Bins
| NAME | COUNT | AT LEAST |  | TEST | COUNT |  | TEST | COUNT |  | TEST | COUNT | 
| others | 
4264 | 
1 | 
 | 
T3 | 
90 | 
 | 
T49 | 
125 | 
 | 
T51 | 
114 | 
| instr_types[0] | 
5277 | 
1 | 
 | 
T3 | 
336 | 
 | 
T49 | 
158 | 
 | 
T51 | 
191 | 
| instr_types[1] | 
4001860 | 
1 | 
 | 
T1 | 
10 | 
 | 
T3 | 
318 | 
 | 
T11 | 
212 | 
Summary for Variable key_cp
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | 
| Automatically Generated Bins | 
2 | 
0 | 
2 | 
100.00 | 
Automatically Generated Bins for key_cp
Bins
| NAME | COUNT | AT LEAST |  | TEST | COUNT |  | TEST | COUNT |  | TEST | COUNT | 
| auto[0] | 
4009569 | 
1 | 
 | 
T1 | 
10 | 
 | 
T3 | 
462 | 
 | 
T11 | 
212 | 
| auto[1] | 
1832 | 
1 | 
 | 
T3 | 
282 | 
 | 
T49 | 
142 | 
 | 
T51 | 
120 | 
Summary for Cross key_instr_cross
Samples crossed: key_cp instr_type_cp
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING | 
| Automatically Generated Cross Bins | 
6 | 
0 | 
6 | 
100.00 | 
 | 
Automatically Generated Cross Bins for key_instr_cross
Bins
| key_cp | instr_type_cp | COUNT | AT LEAST |  | TEST | COUNT |  | TEST | COUNT |  | TEST | COUNT | 
| auto[0] | 
others | 
3903 | 
1 | 
 | 
T3 | 
50 | 
 | 
T49 | 
90 | 
 | 
T51 | 
75 | 
| auto[0] | 
instr_types[0] | 
4542 | 
1 | 
 | 
T3 | 
198 | 
 | 
T49 | 
88 | 
 | 
T51 | 
152 | 
| auto[0] | 
instr_types[1] | 
4001124 | 
1 | 
 | 
T1 | 
10 | 
 | 
T3 | 
214 | 
 | 
T11 | 
212 | 
| auto[1] | 
others | 
361 | 
1 | 
 | 
T3 | 
40 | 
 | 
T49 | 
35 | 
 | 
T51 | 
39 | 
| auto[1] | 
instr_types[0] | 
735 | 
1 | 
 | 
T3 | 
138 | 
 | 
T49 | 
70 | 
 | 
T51 | 
39 | 
| auto[1] | 
instr_types[1] | 
736 | 
1 | 
 | 
T3 | 
104 | 
 | 
T49 | 
37 | 
 | 
T51 | 
42 |