Unified Coverage Report :: Group :: flash_ctrl_env_pkg::flash_ctrl_env_cov::msgfifo_level_cg

Group : flash_ctrl_env_pkg::flash_ctrl_env_cov::msgfifo_level_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
83.33	1	100	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/default/sim-vcs/../src/lowrisc_dv_flash_ctrl_env_0.1/flash_ctrl_env_cov.sv

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Summary for Group flash_ctrl_env_pkg::flash_ctrl_env_cov::msgfifo_level_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	18	3	15	83.33

Variables for Group flash_ctrl_env_pkg::flash_ctrl_env_cov::msgfifo_level_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
prog_lvl_cp	3	3	0	0.00	100	1	1	0
rd_lvl_cp	15	0	15	100.00	100	1	1	0

Summary for Variable prog_lvl_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	3	0	0.00

User Defined Bins for prog_lvl_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER
prog_lvl[1]	0	1	1
prog_lvl[2]	0	1	1
prog_lvl[3]	0	1	1

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Summary for Variable rd_lvl_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	15	0	15	100.00

User Defined Bins for rd_lvl_cp

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
rd_lvl[1]	20570	1		T314	1922		T315	1986		T316	898
rd_lvl[2]	19345	1		T314	818		T317	2989		T315	880
rd_lvl[3]	11990	1		T44	286		T314	316		T318	853
rd_lvl[4]	27209	1		T44	104		T314	438		T318	169
rd_lvl[5]	17342	1		T314	274		T318	2		T319	1054
rd_lvl[6]	29408	1		T320	95		T314	2		T318	1
rd_lvl[7]	9313	1		T320	19		T321	1804		T314	258
rd_lvl[8]	6752	1		T322	2844		T321	1506		T314	256
rd_lvl[9]	1974	1		T322	368		T41	246		T314	397
rd_lvl[10]	3605	1		T41	129		T314	117		T323	1184
rd_lvl[11]	1529	1		T314	112		T324	172		T325	645
rd_lvl[12]	6018	1		T43	1255		T41	165		T314	3
rd_lvl[13]	4026	1		T43	383		T314	1		T326	66
rd_lvl[14]	7809	1		T314	110		T326	14		T327	1106
rd_lvl[15]	2412	1		T39	485		T42	3		T328	232