Unified Coverage Report :: Group :: cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=5}

Group : cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=5}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

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Summary for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=5}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	10	0	10	100.00
Crosses	24	0	24	100.00

Variables for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=5}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr_pin	6	0	6	100.00	100	1	1	0
cp_intr_pin_value	4	0	4	100.00	100	1	1	0

Crosses for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=5}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_intr_pins_all_values	24	0	24	100.00	100	1	1	0

Summary for Variable cp_intr_pin

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	6	0	6	100.00

User Defined Bins for cp_intr_pin

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	275983	1		T1	1		T2	2		T3	2
all_pins[1]	275983	1		T1	1		T2	2		T3	2
all_pins[2]	275983	1		T1	1		T2	2		T3	2
all_pins[3]	275983	1		T1	1		T2	2		T3	2
all_pins[4]	275983	1		T1	1		T2	2		T3	2
all_pins[5]	275983	1		T1	1		T2	2		T3	2

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Summary for Variable cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for cp_intr_pin_value

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x0]	1380393	1		T1	6		T2	12		T3	12
values[0x1]	275505	1		T32	1497		T39	5590		T43	3276
transitions[0x0=>0x1]	252263	1		T32	1497		T39	3280		T43	3276
transitions[0x1=>0x0]	252253	1		T32	1497		T39	3280		T43	3276

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Summary for Cross cp_intr_pins_all_values

Samples crossed: cp_intr_pin cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	24	0	24	100.00

Automatically Generated Cross Bins for cp_intr_pins_all_values

Bins

cp_intr_pin	cp_intr_pin_value	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	values[0x0]	275834	1		T1	1		T2	2		T3	2
all_pins[0]	values[0x1]	149	1		T242	2		T244	2		T305	5
all_pins[0]	transitions[0x0=>0x1]	83	1		T305	4		T306	1		T310	5
all_pins[0]	transitions[0x1=>0x0]	81	1		T243	1		T244	6		T306	5
all_pins[1]	values[0x0]	275836	1		T1	1		T2	2		T3	2
all_pins[1]	values[0x1]	147	1		T242	2		T243	1		T244	8
all_pins[1]	transitions[0x0=>0x1]	129	1		T242	1		T243	1		T244	8
all_pins[1]	transitions[0x1=>0x0]	2305	1		T39	1155		T328	1		T352	2
all_pins[2]	values[0x0]	273660	1		T1	1		T2	2		T3	2
all_pins[2]	values[0x1]	2323	1		T39	1155		T328	1		T352	2
all_pins[2]	transitions[0x0=>0x1]	38	1		T242	1		T243	2		T306	1
all_pins[2]	transitions[0x1=>0x0]	169341	1		T39	485		T43	1638		T44	390
all_pins[3]	values[0x0]	104357	1		T1	1		T2	2		T3	2
all_pins[3]	values[0x1]	171626	1		T39	1640		T43	1638		T44	390
all_pins[3]	transitions[0x0=>0x1]	150811	1		T39	485		T43	1638		T44	370
all_pins[3]	transitions[0x1=>0x0]	80373	1		T32	1497		T39	1640		T43	1638
all_pins[4]	values[0x0]	174795	1		T1	1		T2	2		T3	2
all_pins[4]	values[0x1]	101188	1		T32	1497		T39	2795		T43	1638
all_pins[4]	transitions[0x0=>0x1]	101173	1		T32	1497		T39	2795		T43	1638
all_pins[4]	transitions[0x1=>0x0]	57	1		T242	1		T244	4		T306	3
all_pins[5]	values[0x0]	275911	1		T1	1		T2	2		T3	2
all_pins[5]	values[0x1]	72	1		T242	1		T243	2		T244	4
all_pins[5]	transitions[0x0=>0x1]	29	1		T243	2		T244	3		T306	1
all_pins[5]	transitions[0x1=>0x0]	96	1		T242	1		T244	1		T305	4