Unified Coverage Report :: Group :: cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=5}

Group : cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=5}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
83.33	1	100	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=5}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	12	0	12	100.00
Crosses	36	8	28	77.78

Variables for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=5}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	6	0	6	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2
cp_intr_test	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=5}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_test_cg_cc	36	8	28	77.78	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	6	0	6	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	269	1		T242	4		T243	4		T244	7
all_values[1]	269	1		T242	4		T243	4		T244	7
all_values[2]	269	1		T242	4		T243	4		T244	7
all_values[3]	269	1		T242	4		T243	4		T244	7
all_values[4]	269	1		T242	4		T243	4		T244	7
all_values[5]	269	1		T242	4		T243	4		T244	7

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	934	1		T242	8		T243	17		T244	18
auto[1]	680	1		T242	16		T243	7		T244	24

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	506	1		T242	11		T243	6		T244	15
auto[1]	1108	1		T242	13		T243	18		T244	27

---

Summary for Variable cp_intr_test

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_test

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	962	1		T242	17		T243	13		T244	28
auto[1]	652	1		T242	7		T243	11		T244	14

---

Summary for Cross intr_test_cg_cc

Samples crossed: cp_intr cp_intr_test cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	36	8	28	77.78	8
Automatically Generated Cross Bins	36	8	28	77.78	8
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for intr_test_cg_cc

Element holes

cp_intr	cp_intr_test	cp_intr_en	cp_intr_state	COUNT	AT LEAST	NUMBER
[all_values[0] , all_values[1]]	[auto[0]]	*	[auto[0]]	--	--	4
[all_values[2] , all_values[3]]	[auto[0]]	*	[auto[1]]	--	--	4

Covered bins

cp_intr	cp_intr_test	cp_intr_en	cp_intr_state	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	auto[1]	94	1		T242	2		T243	2		T244	4
all_values[0]	auto[0]	auto[1]	auto[1]	76	1		T242	2		T244	2		T305	2
all_values[0]	auto[1]	auto[0]	auto[1]	51	1		T243	2		T244	1		T306	1
all_values[0]	auto[1]	auto[1]	auto[1]	48	1		T305	2		T306	1		T307	1
all_values[1]	auto[0]	auto[0]	auto[1]	89	1		T242	1		T243	2		T305	2
all_values[1]	auto[0]	auto[1]	auto[1]	71	1		T242	1		T244	3		T305	1
all_values[1]	auto[1]	auto[0]	auto[1]	66	1		T242	1		T243	2		T244	1
all_values[1]	auto[1]	auto[1]	auto[1]	43	1		T242	1		T244	3		T307	2
all_values[2]	auto[0]	auto[0]	auto[0]	98	1		T244	4		T306	3		T307	1
all_values[2]	auto[0]	auto[1]	auto[0]	66	1		T242	2		T243	1		T244	2
all_values[2]	auto[1]	auto[0]	auto[1]	60	1		T243	1		T244	1		T306	3
all_values[2]	auto[1]	auto[1]	auto[1]	45	1		T242	2		T243	2		T307	1
all_values[3]	auto[0]	auto[0]	auto[0]	95	1		T242	2		T243	3		T244	1
all_values[3]	auto[0]	auto[1]	auto[0]	65	1		T242	1		T244	4		T305	1
all_values[3]	auto[1]	auto[0]	auto[1]	67	1		T243	1		T305	1		T306	1
all_values[3]	auto[1]	auto[1]	auto[1]	42	1		T242	1		T244	2		T306	1
all_values[4]	auto[0]	auto[0]	auto[0]	62	1		T243	2		T244	2		T306	2
all_values[4]	auto[0]	auto[0]	auto[1]	28	1		T305	2		T308	1		T309	1
all_values[4]	auto[0]	auto[1]	auto[0]	38	1		T242	3		T244	2		T305	1
all_values[4]	auto[0]	auto[1]	auto[1]	29	1		T243	1		T306	1		T307	3
all_values[4]	auto[1]	auto[0]	auto[1]	66	1		T244	3		T305	1		T306	4
all_values[4]	auto[1]	auto[1]	auto[1]	46	1		T242	1		T243	1		T310	2
all_values[5]	auto[0]	auto[0]	auto[0]	41	1		T242	1		T306	1		T307	1
all_values[5]	auto[0]	auto[0]	auto[1]	34	1		T305	2		T307	1		T310	1
all_values[5]	auto[0]	auto[1]	auto[0]	41	1		T242	2		T311	1		T312	1
all_values[5]	auto[0]	auto[1]	auto[1]	35	1		T243	2		T244	4		T306	3
all_values[5]	auto[1]	auto[0]	auto[1]	83	1		T242	1		T243	2		T244	1
all_values[5]	auto[1]	auto[1]	auto[1]	35	1		T244	2		T306	1		T313	1

User Defined Cross Bins for intr_test_cg_cc

Excluded/Illegal bins

NAME	COUNT	STATUS
test_1_state_0	0	Illegal