Detail Report for Assertions

Assertions Uncovered:

ASSERTIONS	CATEGORY	SEVERITY	ATTEMPTS	REAL SUCCESSES	FAILURES	INCOMPLETE	SRC
tb.dut.FpvSecCmEflashReqFifoRptrCheck_A	0	0	365919510	0	0	0
tb.dut.FpvSecCmEflashReqFifoWptrCheck_A	0	0	365919510	0	0	0
tb.dut.FpvSecCmEflashRspFifoRptrCheck_A	0	0	365919510	0	0	0
tb.dut.FpvSecCmEflashRspFifoWptrCheck_A	0	0	365919510	0	0	0
tb.dut.FpvSecCmEflashSramReqFifoRptrCheck_A	0	0	365919510	0	0	0
tb.dut.FpvSecCmEflashSramReqFifoWptrCheck_A	0	0	365919510	0	0	0
tb.dut.FpvSecCmRdReqFifoRptrCheck_A	0	0	365919510	0	0	0
tb.dut.FpvSecCmRdReqFifoWptrCheck_A	0	0	365919510	0	0	0
tb.dut.FpvSecCmRdSramReqFifoRptrCheck_A	0	0	365919510	0	0	0
tb.dut.FpvSecCmRdSramReqFifoWptrCheck_A	0	0	365919510	0	0	0
tb.dut.PrimRspPayLoad_A	0	0	365919510	0	0	0
tb.dut.u_eflash.gen_flash_cores[0].u_core.u_rd.u_valid_random.LockArbDecision_A	0	0	365919510	0	0	0
tb.dut.u_eflash.gen_flash_cores[0].u_core.u_rd.u_valid_random.ReqStaysHighUntilGranted0_M	0	0	365919510	0	0	0
tb.dut.u_eflash.gen_flash_cores[0].u_core.u_rd.u_valid_random.RoundRobin_A	0	0	365919510	0	0	1053
tb.dut.u_eflash.gen_flash_cores[1].u_core.u_rd.u_valid_random.LockArbDecision_A	0	0	365919510	0	0	0
tb.dut.u_eflash.gen_flash_cores[1].u_core.u_rd.u_valid_random.ReqStaysHighUntilGranted0_M	0	0	365919510	0	0	0
tb.dut.u_eflash.gen_flash_cores[1].u_core.u_rd.u_valid_random.RoundRobin_A	0	0	365919510	0	0	1053
tb.dut.u_eflash.u_scramble.u_prim_arbiter_tree_calc.gen_input_bufs[0].gen_rr_arbiter.u_arb.RoundRobin_A	0	0	365919510	0	0	1053
tb.dut.u_eflash.u_scramble.u_prim_arbiter_tree_calc.gen_input_bufs[1].gen_rr_arbiter.u_arb.RoundRobin_A	0	0	365919510	0	0	1053
tb.dut.u_eflash.u_scramble.u_prim_arbiter_tree_op.gen_input_bufs[0].gen_rr_arbiter.u_arb.RoundRobin_A	0	0	365919510	0	0	1053
tb.dut.u_eflash.u_scramble.u_prim_arbiter_tree_op.gen_input_bufs[1].gen_rr_arbiter.u_arb.RoundRobin_A	0	0	365919510	0	0	1053
tb.dut.u_prog_tl_gate.OutStandingOvfl_A	0	0	365919510	0	0	0
tb.dut.u_tl_gate.OutStandingOvfl_A	0	0	365919510	0	0	0
tb.dut.u_to_prog_fifo.rvalidHighReqFifoEmpty	0	0	365919510	0	0	0
tb.dut.u_to_prog_fifo.rvalidHighWhenRspFifoFull	0	0	365919510	0	0	0
tb.dut.u_to_prog_fifo.u_rspfifo.DataKnown_A	0	0	365919510	0	0	0
tb.dut.u_to_prog_fifo.u_rspfifo.gen_normal_fifo.depthShallNotExceedParamDepth	0	0	365919510	0	0	0
tb.dut.u_to_prog_fifo.u_sramreqfifo.DataKnown_A	0	0	365919510	0	0	0
tb.dut.u_to_prog_fifo.u_sramreqfifo.gen_normal_fifo.depthShallNotExceedParamDepth	0	0	365919510	0	0	0

Assertions Success:

ASSERTIONS	CATEGORY	SEVERITY	ATTEMPTS	REAL SUCCESSES	FAILURES	INCOMPLETE	SRC
tb.dut.FifoDepthCheck_A	0	0	1058	1058	0	0
tb.dut.FlashAddrKnown_A	0	0	365919510	261924428	0	0
tb.dut.FlashAddrKnown_AKnownEnable	0	0	365919510	365174210	0	0
tb.dut.FlashKnownO_A	0	0	365919510	365174210	0	0
tb.dut.FlashProgKnown_A	0	0	365919510	155189042	0	0
tb.dut.FlashProgKnown_AKnownEnable	0	0	365919510	365174210	0	0
tb.dut.FpvSecCmAddrCntAlertCheck_A	0	0	365919510	50	0	0
tb.dut.FpvSecCmArbFsmCheck_A	0	0	365919510	50	0	0
tb.dut.FpvSecCmLcCtrlFsmCheck_A	0	0	365919510	50	0	0
tb.dut.FpvSecCmLcCtrlRmaFsmCheck_A	0	0	365919510	50	0	0
tb.dut.FpvSecCmPageCntAlertCheck_A	0	0	365919510	50	0	0
tb.dut.FpvSecCmProgCnt_A	0	0	365919510	50	0	0
tb.dut.FpvSecCmRdCnt_A	0	0	365919510	50	0	0
tb.dut.FpvSecCmRdRspFifoRptrCheck_A	0	0	365919510	50	0	0
tb.dut.FpvSecCmRdRspFifoWptrCheck_A	0	0	365919510	50	0	0
tb.dut.FpvSecCmRegWeOnehotCheck_A	0	0	365919510	50	0	0
tb.dut.FpvSecCmSeedCntAlertCheck_A	0	0	365919510	50	0	0
tb.dut.FpvSecCmTlLcGateFsm_A	0	0	365919510	50	0	0
tb.dut.FpvSecCmTlProgLcGateFsm_A	0	0	365919510	50	0	0
tb.dut.FpvSecCmWipeIdx_A	0	0	365919510	50	0	0
tb.dut.FpvSecCmWordCntAlertCheck_A	0	0	365919510	50	0	0
tb.dut.IntrErrO_A	0	0	365919510	365174210	0	0
tb.dut.IntrOpDoneKnownO_A	0	0	365919510	365174210	0	0
tb.dut.IntrProgEmptyKnownO_A	0	0	365919510	365174210	0	0
tb.dut.IntrProgLvlKnownO_A	0	0	365919510	365174210	0	0
tb.dut.IntrProgRdFullKnownO_A	0	0	365919510	365174210	0	0
tb.dut.IntrRdLvlKnownO_A	0	0	365919510	365174210	0	0
tb.dut.MemRspPayLoad_A	0	0	365919510	4877890	0	0
tb.dut.MemRspPayLoad_AKnownEnable	0	0	365919510	365174210	0	0
tb.dut.MemTlAReadyKnownO_A	0	0	365919510	365174210	0	0
tb.dut.MemTlDValidKnownO_A	0	0	365919510	365174210	0	0
tb.dut.PrimRspPayLoad_AKnownEnable	0	0	365919510	365174210	0	0
tb.dut.PrimTlAReadyKnownO_A	0	0	365919510	365174210	0	0
tb.dut.PrimTlDValidKnownO_A	0	0	365919510	365174210	0	0
tb.dut.RspPayLoad_A	0	0	365681025	38183571	0	0
tb.dut.RspPayLoad_AKnownEnable	0	0	365919510	365174210	0	0
tb.dut.TdoEnIsOne_A	0	0	365919510	365174210	0	0
tb.dut.TdoKnown_A	0	0	365919510	365174210	0	0
tb.dut.TlAReadyKnownO_A	0	0	365919510	365174210	0	0
tb.dut.TlDValidKnownO_A	0	0	365919510	365174210	0	0
tb.dut.flash_ctrl_core_csr_assert.TlulOOBAddrErr_A	0	0	368358938	4067	0	0
tb.dut.flash_ctrl_core_csr_assert.addr_rd_A	0	0	368358938	1635	0	0
tb.dut.flash_ctrl_core_csr_assert.bank0_info0_page_cfg_0_rd_A	0	0	368358938	3840	0	0
tb.dut.flash_ctrl_core_csr_assert.bank0_info0_page_cfg_1_rd_A	0	0	368358938	3121	0	0
tb.dut.flash_ctrl_core_csr_assert.bank0_info0_page_cfg_2_rd_A	0	0	368358938	3115	0	0
tb.dut.flash_ctrl_core_csr_assert.bank0_info0_page_cfg_3_rd_A	0	0	368358938	3165	0	0
tb.dut.flash_ctrl_core_csr_assert.bank0_info0_page_cfg_4_rd_A	0	0	368358938	2387	0	0
tb.dut.flash_ctrl_core_csr_assert.bank0_info0_page_cfg_5_rd_A	0	0	368358938	2088	0	0
tb.dut.flash_ctrl_core_csr_assert.bank0_info0_page_cfg_6_rd_A	0	0	368358938	3078	0	0
tb.dut.flash_ctrl_core_csr_assert.bank0_info0_page_cfg_7_rd_A	0	0	368358938	3713	0	0
tb.dut.flash_ctrl_core_csr_assert.bank0_info0_page_cfg_8_rd_A	0	0	368358938	3634	0	0
tb.dut.flash_ctrl_core_csr_assert.bank0_info0_page_cfg_9_rd_A	0	0	368358938	3163	0	0
tb.dut.flash_ctrl_core_csr_assert.bank0_info0_regwen_0_rd_A	0	0	368358938	2645	0	0
tb.dut.flash_ctrl_core_csr_assert.bank0_info0_regwen_1_rd_A	0	0	368358938	2262	0	0
tb.dut.flash_ctrl_core_csr_assert.bank0_info0_regwen_2_rd_A	0	0	368358938	2027	0	0
tb.dut.flash_ctrl_core_csr_assert.bank0_info0_regwen_3_rd_A	0	0	368358938	2710	0	0
tb.dut.flash_ctrl_core_csr_assert.bank0_info0_regwen_4_rd_A	0	0	368358938	1771	0	0
tb.dut.flash_ctrl_core_csr_assert.bank0_info0_regwen_5_rd_A	0	0	368358938	1727	0	0
tb.dut.flash_ctrl_core_csr_assert.bank0_info0_regwen_6_rd_A	0	0	368358938	2290	0	0
tb.dut.flash_ctrl_core_csr_assert.bank0_info0_regwen_7_rd_A	0	0	368358938	2240	0	0
tb.dut.flash_ctrl_core_csr_assert.bank0_info0_regwen_8_rd_A	0	0	368358938	2541	0	0
tb.dut.flash_ctrl_core_csr_assert.bank0_info0_regwen_9_rd_A	0	0	368358938	2094	0	0
tb.dut.flash_ctrl_core_csr_assert.bank0_info1_page_cfg_rd_A	0	0	368358938	3688	0	0
tb.dut.flash_ctrl_core_csr_assert.bank0_info1_regwen_rd_A	0	0	368358938	2200	0	0
tb.dut.flash_ctrl_core_csr_assert.bank0_info2_page_cfg_0_rd_A	0	0	368358938	3509	0	0
tb.dut.flash_ctrl_core_csr_assert.bank0_info2_page_cfg_1_rd_A	0	0	368358938	3203	0	0
tb.dut.flash_ctrl_core_csr_assert.bank0_info2_regwen_0_rd_A	0	0	368358938	1742	0	0
tb.dut.flash_ctrl_core_csr_assert.bank0_info2_regwen_1_rd_A	0	0	368358938	2661	0	0
tb.dut.flash_ctrl_core_csr_assert.bank1_info0_page_cfg_0_rd_A	0	0	368358938	3702	0	0
tb.dut.flash_ctrl_core_csr_assert.bank1_info0_page_cfg_1_rd_A	0	0	368358938	2621	0	0
tb.dut.flash_ctrl_core_csr_assert.bank1_info0_page_cfg_2_rd_A	0	0	368358938	3206	0	0
tb.dut.flash_ctrl_core_csr_assert.bank1_info0_page_cfg_3_rd_A	0	0	368358938	2681	0	0
tb.dut.flash_ctrl_core_csr_assert.bank1_info0_page_cfg_4_rd_A	0	0	368358938	3489	0	0
tb.dut.flash_ctrl_core_csr_assert.bank1_info0_page_cfg_5_rd_A	0	0	368358938	1604	0	0
tb.dut.flash_ctrl_core_csr_assert.bank1_info0_page_cfg_6_rd_A	0	0	368358938	3101	0	0
tb.dut.flash_ctrl_core_csr_assert.bank1_info0_page_cfg_7_rd_A	0	0	368358938	3532	0	0
tb.dut.flash_ctrl_core_csr_assert.bank1_info0_page_cfg_8_rd_A	0	0	368358938	3575	0	0
tb.dut.flash_ctrl_core_csr_assert.bank1_info0_page_cfg_9_rd_A	0	0	368358938	2306	0	0
tb.dut.flash_ctrl_core_csr_assert.bank1_info0_regwen_0_rd_A	0	0	368358938	2727	0	0
tb.dut.flash_ctrl_core_csr_assert.bank1_info0_regwen_1_rd_A	0	0	368358938	2734	0	0
tb.dut.flash_ctrl_core_csr_assert.bank1_info0_regwen_2_rd_A	0	0	368358938	2722	0	0
tb.dut.flash_ctrl_core_csr_assert.bank1_info0_regwen_3_rd_A	0	0	368358938	1166	0	0
tb.dut.flash_ctrl_core_csr_assert.bank1_info0_regwen_4_rd_A	0	0	368358938	2596	0	0
tb.dut.flash_ctrl_core_csr_assert.bank1_info0_regwen_5_rd_A	0	0	368358938	2593	0	0
tb.dut.flash_ctrl_core_csr_assert.bank1_info0_regwen_6_rd_A	0	0	368358938	2196	0	0
tb.dut.flash_ctrl_core_csr_assert.bank1_info0_regwen_7_rd_A	0	0	368358938	2725	0	0
tb.dut.flash_ctrl_core_csr_assert.bank1_info0_regwen_8_rd_A	0	0	368358938	1994	0	0
tb.dut.flash_ctrl_core_csr_assert.bank1_info0_regwen_9_rd_A	0	0	368358938	2293	0	0
tb.dut.flash_ctrl_core_csr_assert.bank1_info1_page_cfg_rd_A	0	0	368358938	3040	0	0
tb.dut.flash_ctrl_core_csr_assert.bank1_info1_regwen_rd_A	0	0	368358938	2098	0	0
tb.dut.flash_ctrl_core_csr_assert.bank1_info2_page_cfg_0_rd_A	0	0	368358938	2906	0	0
tb.dut.flash_ctrl_core_csr_assert.bank1_info2_page_cfg_1_rd_A	0	0	368358938	3115	0	0
tb.dut.flash_ctrl_core_csr_assert.bank1_info2_regwen_0_rd_A	0	0	368358938	2886	0	0
tb.dut.flash_ctrl_core_csr_assert.bank1_info2_regwen_1_rd_A	0	0	368358938	1564	0	0
tb.dut.flash_ctrl_core_csr_assert.bank_cfg_regwen_rd_A	0	0	368358938	2174	0	0
tb.dut.flash_ctrl_core_csr_assert.default_region_rd_A	0	0	368358938	2517	0	0
tb.dut.flash_ctrl_core_csr_assert.exec_rd_A	0	0	368358938	2305	0	0
tb.dut.flash_ctrl_core_csr_assert.fifo_lvl_rd_A	0	0	368358938	2307	0	0
tb.dut.flash_ctrl_core_csr_assert.fifo_rst_rd_A	0	0	368358938	2101	0	0
tb.dut.flash_ctrl_core_csr_assert.hw_info_cfg_override_rd_A	0	0	368358938	2287	0	0
tb.dut.flash_ctrl_core_csr_assert.intr_enable_rd_A	0	0	368358938	2811	0	0
tb.dut.flash_ctrl_core_csr_assert.mp_region_0_rd_A	0	0	368358938	2301	0	0
tb.dut.flash_ctrl_core_csr_assert.mp_region_1_rd_A	0	0	368358938	2239	0	0
tb.dut.flash_ctrl_core_csr_assert.mp_region_2_rd_A	0	0	368358938	2394	0	0
tb.dut.flash_ctrl_core_csr_assert.mp_region_3_rd_A	0	0	368358938	2841	0	0
tb.dut.flash_ctrl_core_csr_assert.mp_region_4_rd_A	0	0	368358938	2343	0	0
tb.dut.flash_ctrl_core_csr_assert.mp_region_5_rd_A	0	0	368358938	2304	0	0
tb.dut.flash_ctrl_core_csr_assert.mp_region_6_rd_A	0	0	368358938	2871	0	0
tb.dut.flash_ctrl_core_csr_assert.mp_region_7_rd_A	0	0	368358938	2548	0	0
tb.dut.flash_ctrl_core_csr_assert.mp_region_cfg_0_rd_A	0	0	368358938	3618	0	0
tb.dut.flash_ctrl_core_csr_assert.mp_region_cfg_1_rd_A	0	0	368358938	3623	0	0
tb.dut.flash_ctrl_core_csr_assert.mp_region_cfg_2_rd_A	0	0	368358938	3503	0	0
tb.dut.flash_ctrl_core_csr_assert.mp_region_cfg_3_rd_A	0	0	368358938	3671	0	0
tb.dut.flash_ctrl_core_csr_assert.mp_region_cfg_4_rd_A	0	0	368358938	3207	0	0
tb.dut.flash_ctrl_core_csr_assert.mp_region_cfg_5_rd_A	0	0	368358938	3639	0	0
tb.dut.flash_ctrl_core_csr_assert.mp_region_cfg_6_rd_A	0	0	368358938	2889	0	0
tb.dut.flash_ctrl_core_csr_assert.mp_region_cfg_7_rd_A	0	0	368358938	2949	0	0
tb.dut.flash_ctrl_core_csr_assert.phy_alert_cfg_rd_A	0	0	368358938	1282	0	0
tb.dut.flash_ctrl_core_csr_assert.region_cfg_regwen_0_rd_A	0	0	368358938	2113	0	0
tb.dut.flash_ctrl_core_csr_assert.region_cfg_regwen_1_rd_A	0	0	368358938	1660	0	0
tb.dut.flash_ctrl_core_csr_assert.region_cfg_regwen_2_rd_A	0	0	368358938	1189	0	0
tb.dut.flash_ctrl_core_csr_assert.region_cfg_regwen_3_rd_A	0	0	368358938	2242	0	0
tb.dut.flash_ctrl_core_csr_assert.region_cfg_regwen_4_rd_A	0	0	368358938	2926	0	0
tb.dut.flash_ctrl_core_csr_assert.region_cfg_regwen_5_rd_A	0	0	368358938	2622	0	0
tb.dut.flash_ctrl_core_csr_assert.region_cfg_regwen_6_rd_A	0	0	368358938	2001	0	0
tb.dut.flash_ctrl_core_csr_assert.region_cfg_regwen_7_rd_A	0	0	368358938	2210	0	0
tb.dut.flash_ctrl_core_csr_assert.scratch_rd_A	0	0	368358938	1663	0	0
tb.dut.gen_phy_assertions[0].FpvSecCmPhyFsmCheck_A	0	0	365919510	50	0	0
tb.dut.gen_phy_assertions[0].FpvSecCmPhyProgFsmCheck_A	0	0	365919510	50	0	0
tb.dut.gen_phy_assertions[1].FpvSecCmPhyFsmCheck_A	0	0	365919510	50	0	0
tb.dut.gen_phy_assertions[1].FpvSecCmPhyProgFsmCheck_A	0	0	365919510	50	0	0
tb.dut.gen_phy_cnt_errs[0].FpvSecCmPhyHostCnt_A	0	0	365919510	50	0	0
tb.dut.gen_phy_cnt_errs[0].FpvSecCmPhyRdDataFifoRPtr_A	0	0	365919510	50	0	0
tb.dut.gen_phy_cnt_errs[0].FpvSecCmPhyRdDataFifoWPtr_A	0	0	365919510	50	0	0
tb.dut.gen_phy_cnt_errs[0].FpvSecCmPhyRdRspFifoRPtr_A	0	0	365919510	50	0	0
tb.dut.gen_phy_cnt_errs[0].FpvSecCmPhyRdRspFifoWPtr_A	0	0	365919510	50	0	0
tb.dut.gen_phy_cnt_errs[0].FpvSecCmPhyRspFifoRPtr_A	0	0	365919510	50	0	0
tb.dut.gen_phy_cnt_errs[0].FpvSecCmPhyRspFifoWPtr_A	0	0	365919510	50	0	0
tb.dut.gen_phy_cnt_errs[1].FpvSecCmPhyHostCnt_A	0	0	365919510	50	0	0
tb.dut.gen_phy_cnt_errs[1].FpvSecCmPhyRdDataFifoRPtr_A	0	0	365919510	50	0	0
tb.dut.gen_phy_cnt_errs[1].FpvSecCmPhyRdDataFifoWPtr_A	0	0	365919510	50	0	0
tb.dut.gen_phy_cnt_errs[1].FpvSecCmPhyRdRspFifoRPtr_A	0	0	365919510	50	0	0
tb.dut.gen_phy_cnt_errs[1].FpvSecCmPhyRdRspFifoWPtr_A	0	0	365919510	50	0	0
tb.dut.gen_phy_cnt_errs[1].FpvSecCmPhyRspFifoRPtr_A	0	0	365919510	50	0	0
tb.dut.gen_phy_cnt_errs[1].FpvSecCmPhyRspFifoWPtr_A	0	0	365919510	50	0	0
tb.dut.gen_reg_we_assert_generic.FpvSecCmPrimRegWeOnehotCheck_A	0	0	365919510	25	0	0
tb.dut.tlul_assert_device.aKnown_A	0	0	368358806	36153804	0	0
tb.dut.tlul_assert_device.aKnown_AKnownEnable	0	0	368358806	367528093	0	0
tb.dut.tlul_assert_device.aReadyKnown_A	0	0	368358806	367528093	0	0
tb.dut.tlul_assert_device.dKnown_A	0	0	368358806	39020150	0	0
tb.dut.tlul_assert_device.dKnown_AKnownEnable	0	0	368358806	367528093	0	0
tb.dut.tlul_assert_device.dReadyKnown_A	0	0	368358806	367528093	0	0
tb.dut.tlul_assert_device.gen_assert_final[0].noOutstandingReqsAtEndOfSim_A	0	0	1268	1268	0	0
tb.dut.tlul_assert_device.gen_assert_final[100].noOutstandingReqsAtEndOfSim_A	0	0	1268	1268	0	0
tb.dut.tlul_assert_device.gen_assert_final[101].noOutstandingReqsAtEndOfSim_A	0	0	1268	1268	0	0
tb.dut.tlul_assert_device.gen_assert_final[102].noOutstandingReqsAtEndOfSim_A	0	0	1268	1268	0	0
tb.dut.tlul_assert_device.gen_assert_final[103].noOutstandingReqsAtEndOfSim_A	0	0	1268	1268	0	0
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tb.dut.tlul_assert_device.gen_assert_final[167].noOutstandingReqsAtEndOfSim_A	0	0	1268	1268	0	0
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tb.dut.tlul_assert_device.gen_assert_final[170].noOutstandingReqsAtEndOfSim_A	0	0	1268	1268	0	0
tb.dut.tlul_assert_device.gen_assert_final[171].noOutstandingReqsAtEndOfSim_A	0	0	1268	1268	0	0
tb.dut.tlul_assert_device.gen_assert_final[172].noOutstandingReqsAtEndOfSim_A	0	0	1268	1268	0	0
tb.dut.tlul_assert_device.gen_assert_final[173].noOutstandingReqsAtEndOfSim_A	0	0	1268	1268	0	0
tb.dut.tlul_assert_device.gen_assert_final[174].noOutstandingReqsAtEndOfSim_A	0	0	1268	1268	0	0

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