Tests
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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
96.07 95.23 93.83 98.31 92.52 97.16 97.27 98.18


Total tests in report: 1273
Tests are in graded order

Scores are accumulated (Total) and incremental (Incr) for each test.

SCORE LINE COND TOGGLE FSM BRANCH ASSERT GROUP  
TOTAL INCRTOTALINCRTOTALINCRTOTALINCRTOTALINCRTOTALINCRTOTALINCRTOTALINCRNAME
58.21 58.21 85.25 85.25 65.08 65.08 43.01 43.01 19.73 19.73 82.31 82.31 81.19 81.19 30.89 30.89 /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default/0.flash_ctrl_fetch_code.3271395311
67.38 9.17 87.35 2.09 68.38 3.29 59.43 16.42 53.74 34.01 85.06 2.76 82.60 1.41 35.08 4.19 /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default/0.flash_ctrl_mid_op_rst.3309074478
73.89 6.51 89.38 2.03 72.79 4.41 83.75 24.32 67.35 13.61 85.94 0.88 82.78 0.19 35.23 0.15 /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default/0.flash_ctrl_otp_reset.2291773828
78.91 5.02 92.42 3.05 78.73 5.94 85.99 2.25 67.35 0.00 91.56 5.62 83.63 0.85 52.65 17.42 /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/cover_reg_top/0.flash_ctrl_csr_mem_rw_with_rand_reset.899855900
82.43 3.53 92.92 0.50 85.00 6.27 86.62 0.63 74.15 6.80 93.10 1.54 84.48 0.85 60.76 8.11 /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default/0.flash_ctrl_rw_serr.3693167144
85.33 2.89 93.26 0.34 85.95 0.94 86.85 0.22 74.15 0.00 93.46 0.36 85.04 0.56 78.58 17.82 /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default/0.flash_ctrl_mp_regions.211846843
87.39 2.07 93.27 0.01 86.15 0.20 86.85 0.00 74.15 0.00 93.53 0.06 92.85 7.81 84.96 6.38 /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/cover_reg_top/1.flash_ctrl_csr_aliasing.2624806056
88.91 1.52 93.45 0.18 87.00 0.86 90.88 4.03 75.51 1.36 94.27 0.75 96.05 3.20 85.23 0.28 /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default/2.flash_ctrl_sec_cm.857854815
90.43 1.51 93.96 0.51 87.47 0.47 93.99 3.12 80.95 5.44 94.87 0.60 96.24 0.19 85.51 0.28 /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default/0.flash_ctrl_hw_rma.1468251436
91.04 0.62 94.05 0.09 87.49 0.02 94.03 0.03 85.03 4.08 94.96 0.09 96.24 0.00 85.51 0.00 /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default/2.flash_ctrl_mid_op_rst.2032973229
91.51 0.47 94.30 0.25 88.30 0.81 94.76 0.74 85.03 0.00 95.51 0.56 96.24 0.00 86.44 0.92 /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default/0.flash_ctrl_intr_rd_slow_flash.539359560
91.93 0.42 94.30 0.00 88.46 0.16 94.76 0.00 85.03 0.00 95.51 0.00 96.24 0.00 89.18 2.74 /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/cover_reg_top/1.flash_ctrl_csr_bit_bash.2543278269
92.30 0.38 94.45 0.15 88.94 0.49 95.47 0.71 85.71 0.68 95.94 0.43 96.24 0.00 89.36 0.18 /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default/0.flash_ctrl_wr_intg.3123452590
92.63 0.32 94.58 0.13 89.85 0.90 95.87 0.40 85.71 0.00 95.94 0.00 96.24 0.00 90.20 0.83 /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default/1.flash_ctrl_hw_sec_otp.1526949047
92.93 0.30 94.59 0.01 89.87 0.02 95.87 0.00 87.76 2.04 95.96 0.02 96.24 0.00 90.20 0.00 /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default/19.flash_ctrl_otp_reset.246293378
93.15 0.22 94.71 0.12 89.88 0.01 95.87 0.00 87.76 0.00 95.96 0.00 96.24 0.00 91.65 1.45 /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/cover_reg_top/0.flash_ctrl_intr_test.2052465029
93.35 0.20 94.72 0.01 89.94 0.07 95.90 0.03 87.76 0.00 95.98 0.02 96.24 0.00 92.91 1.26 /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/cover_reg_top/0.flash_ctrl_tl_intg_err.730818602
93.55 0.20 94.72 0.00 89.95 0.01 95.90 0.00 89.12 1.36 96.00 0.02 96.24 0.00 92.91 0.00 /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default/22.flash_ctrl_otp_reset.1672408646
93.72 0.17 94.73 0.02 90.60 0.65 96.02 0.11 89.12 0.00 96.13 0.13 96.33 0.09 93.13 0.22 /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default/0.flash_ctrl_rw_derr.1433692496
93.88 0.15 94.79 0.05 90.72 0.11 96.40 0.39 89.12 0.00 96.26 0.13 96.33 0.00 93.53 0.40 /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default/0.flash_ctrl_sec_info_access.27970573
94.02 0.15 94.80 0.02 91.63 0.91 96.40 0.00 89.12 0.00 96.26 0.00 96.33 0.00 93.62 0.09 /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/cover_reg_top/0.flash_ctrl_tl_errors.1512480181
94.15 0.13 94.80 0.00 91.64 0.01 96.59 0.19 89.80 0.68 96.26 0.00 96.33 0.00 93.62 0.00 /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default/0.flash_ctrl_rma_err.2983213037
94.27 0.12 94.82 0.02 91.82 0.18 96.80 0.21 89.80 0.00 96.37 0.11 96.33 0.00 93.96 0.34 /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default/0.flash_ctrl_invalid_op.4264466975
94.39 0.12 94.92 0.10 91.93 0.10 97.25 0.45 89.80 0.00 96.37 0.00 96.33 0.00 94.14 0.18 /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default/0.flash_ctrl_alert_test.4172461997
94.50 0.11 94.93 0.01 91.93 0.00 97.29 0.03 90.48 0.68 96.39 0.02 96.33 0.00 94.14 0.00 /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default/30.flash_ctrl_otp_reset.3869979625
94.60 0.10 94.93 0.00 91.95 0.03 97.29 0.00 91.16 0.68 96.39 0.00 96.33 0.00 94.14 0.00 /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default/3.flash_ctrl_mid_op_rst.418732840
94.70 0.10 94.93 0.00 91.96 0.01 97.29 0.00 91.84 0.68 96.39 0.00 96.33 0.00 94.14 0.00 /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default/0.flash_ctrl_host_ctrl_arb.1566856621
94.79 0.10 94.93 0.00 91.96 0.00 97.29 0.00 92.52 0.68 96.39 0.00 96.33 0.00 94.14 0.00 /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default/1.flash_ctrl_mid_op_rst.3295579308
94.87 0.08 94.95 0.02 92.09 0.12 97.29 0.00 92.52 0.00 96.52 0.13 96.61 0.28 94.14 0.00 /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/cover_reg_top/0.flash_ctrl_csr_hw_reset.1812661974
94.94 0.07 94.95 0.00 92.09 0.00 97.29 0.00 92.52 0.00 96.52 0.00 97.08 0.47 94.14 0.00 /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/cover_reg_top/4.flash_ctrl_mem_partial_access.2664815344
94.99 0.05 94.95 0.00 92.09 0.00 97.29 0.00 92.52 0.00 96.52 0.00 97.08 0.00 94.51 0.37 /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default/6.flash_ctrl_re_evict.2746212022
95.04 0.05 94.95 0.00 92.11 0.02 97.29 0.00 92.52 0.00 96.52 0.00 97.08 0.00 94.85 0.34 /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default/0.flash_ctrl_integrity.222485653
95.09 0.05 94.96 0.01 92.15 0.05 97.48 0.19 92.52 0.00 96.56 0.04 97.08 0.00 94.88 0.03 /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default/2.flash_ctrl_lcmgr_intg.3096148659
95.14 0.04 94.96 0.01 92.32 0.16 97.53 0.05 92.52 0.00 96.62 0.06 97.08 0.00 94.91 0.03 /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default/0.flash_ctrl_phy_arb_redun.824791906
95.18 0.04 95.00 0.04 92.54 0.23 97.53 0.00 92.52 0.00 96.62 0.00 97.08 0.00 94.94 0.03 /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/cover_reg_top/10.flash_ctrl_tl_errors.3215832573
95.22 0.04 95.00 0.00 92.54 0.00 97.53 0.00 92.52 0.00 96.62 0.00 97.08 0.00 95.22 0.28 /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/cover_reg_top/3.flash_ctrl_intr_test.2271770408
95.26 0.04 95.00 0.00 92.54 0.00 97.53 0.00 92.52 0.00 96.62 0.00 97.08 0.00 95.50 0.28 /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default/13.flash_ctrl_intr_rd.151454981
95.30 0.04 95.04 0.04 92.60 0.06 97.65 0.13 92.52 0.00 96.65 0.02 97.08 0.00 95.53 0.03 /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default/0.flash_ctrl_error_prog_win.2582298280
95.33 0.04 95.05 0.01 92.63 0.03 97.78 0.13 92.52 0.00 96.69 0.04 97.08 0.00 95.59 0.06 /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default/18.flash_ctrl_hw_prog_rma_wipe_err.850961464
95.37 0.04 95.05 0.00 92.65 0.02 97.78 0.00 92.52 0.00 96.69 0.00 97.08 0.00 95.84 0.25 /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default/2.flash_ctrl_mp_regions.114296725
95.41 0.04 95.06 0.02 92.68 0.03 97.82 0.03 92.52 0.00 96.77 0.09 97.08 0.00 95.93 0.09 /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default/4.flash_ctrl_hw_read_seed_err.2822490423
95.44 0.04 95.06 0.00 92.68 0.00 97.82 0.00 92.52 0.00 96.77 0.00 97.08 0.00 96.18 0.25 /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/cover_reg_top/2.flash_ctrl_tl_intg_err.2209494581
95.48 0.03 95.06 0.00 92.69 0.01 97.85 0.03 92.52 0.00 96.77 0.00 97.08 0.00 96.36 0.18 /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default/18.flash_ctrl_intr_rd_slow_flash.2297181189
95.51 0.03 95.06 0.00 92.74 0.06 97.94 0.10 92.52 0.00 96.77 0.00 97.08 0.00 96.42 0.06 /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default/1.flash_ctrl_rw_evict_all_en.3630797958
95.54 0.03 95.08 0.02 92.81 0.07 97.94 0.00 92.52 0.00 96.84 0.06 97.08 0.00 96.49 0.06 /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default/2.flash_ctrl_phy_host_grant_err.1895808236
95.56 0.03 95.13 0.05 92.83 0.02 97.99 0.05 92.52 0.00 96.88 0.04 97.08 0.00 96.52 0.03 /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default/30.flash_ctrl_disable.1878051512
95.59 0.03 95.13 0.00 92.83 0.00 97.99 0.00 92.52 0.00 96.88 0.00 97.27 0.19 96.52 0.00 /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/cover_reg_top/0.flash_ctrl_mem_partial_access.3650965293
95.62 0.02 95.15 0.02 92.93 0.10 97.99 0.00 92.52 0.00 96.92 0.04 97.27 0.00 96.52 0.00 /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default/0.flash_ctrl_access_after_disable.2802181661
95.64 0.02 95.16 0.01 92.99 0.06 97.99 0.00 92.52 0.00 96.97 0.04 97.27 0.00 96.55 0.03 /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default/0.flash_ctrl_phy_ack_consistency.695312467
95.65 0.02 95.17 0.01 93.01 0.02 98.02 0.03 92.52 0.00 97.01 0.04 97.27 0.00 96.58 0.03 /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default/0.flash_ctrl_hw_read_seed_err.1990668777
95.67 0.02 95.17 0.00 93.02 0.01 98.02 0.00 92.52 0.00 97.01 0.00 97.27 0.00 96.70 0.12 /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default/12.flash_ctrl_rw_evict_all_en.2448742554
95.69 0.02 95.17 0.00 93.11 0.09 98.02 0.00 92.52 0.00 97.05 0.04 97.27 0.00 96.70 0.00 /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default/1.flash_ctrl_fetch_code.282977819
95.71 0.02 95.17 0.00 93.11 0.00 98.02 0.00 92.52 0.00 97.05 0.00 97.27 0.00 96.82 0.12 /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default/1.flash_ctrl_sec_info_access.3578542770
95.73 0.02 95.18 0.01 93.14 0.04 98.02 0.00 92.52 0.00 97.09 0.04 97.27 0.00 96.86 0.03 /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default/11.flash_ctrl_hw_prog_rma_wipe_err.3524004431
95.74 0.01 95.18 0.00 93.15 0.01 98.02 0.00 92.52 0.00 97.09 0.00 97.27 0.00 96.95 0.09 /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/cover_reg_top/13.flash_ctrl_tl_intg_err.1744604183
95.75 0.01 95.18 0.00 93.15 0.00 98.12 0.10 92.52 0.00 97.09 0.00 97.27 0.00 96.95 0.00 /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default/15.flash_ctrl_lcmgr_intg.2905396212
95.77 0.01 95.18 0.00 93.15 0.00 98.12 0.00 92.52 0.00 97.09 0.00 97.27 0.00 97.04 0.09 /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/cover_reg_top/9.flash_ctrl_tl_intg_err.323937220
95.78 0.01 95.18 0.00 93.23 0.08 98.14 0.02 92.52 0.00 97.09 0.00 97.27 0.00 97.04 0.00 /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default/0.flash_ctrl_erase_suspend.3797731304
95.79 0.01 95.19 0.01 93.24 0.01 98.14 0.00 92.52 0.00 97.14 0.04 97.27 0.00 97.07 0.03 /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default/1.flash_ctrl_hw_prog_rma_wipe_err.2813496145
95.81 0.01 95.23 0.04 93.24 0.00 98.15 0.02 92.52 0.00 97.14 0.00 97.27 0.00 97.10 0.03 /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default/2.flash_ctrl_connect.595097547
95.82 0.01 95.23 0.00 93.27 0.03 98.15 0.00 92.52 0.00 97.14 0.00 97.27 0.00 97.16 0.06 /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default/4.flash_ctrl_re_evict.4133571024
95.83 0.01 95.23 0.00 93.33 0.06 98.15 0.00 92.52 0.00 97.14 0.00 97.27 0.00 97.19 0.03 /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default/2.flash_ctrl_error_prog_type.3078863227
95.84 0.01 95.23 0.00 93.35 0.03 98.19 0.03 92.52 0.00 97.16 0.02 97.27 0.00 97.19 0.00 /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default/1.flash_ctrl_hw_rma_reset.2638224347
95.86 0.01 95.23 0.00 93.43 0.08 98.19 0.00 92.52 0.00 97.16 0.00 97.27 0.00 97.19 0.00 /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default/0.flash_ctrl_rd_intg.3908942252
95.87 0.01 95.23 0.00 93.44 0.01 98.19 0.00 92.52 0.00 97.16 0.00 97.27 0.00 97.26 0.06 /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/cover_reg_top/17.flash_ctrl_tl_intg_err.3703002999
95.88 0.01 95.23 0.00 93.45 0.01 98.19 0.00 92.52 0.00 97.16 0.00 97.27 0.00 97.32 0.06 /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default/2.flash_ctrl_fs_sup.3219943824
95.89 0.01 95.23 0.00 93.52 0.07 98.19 0.00 92.52 0.00 97.16 0.00 97.27 0.00 97.32 0.00 /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default/5.flash_ctrl_rw.1477801494
95.89 0.01 95.23 0.00 93.52 0.00 98.22 0.03 92.52 0.00 97.16 0.00 97.27 0.00 97.35 0.03 /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default/10.flash_ctrl_hw_rma_reset.2568866877
95.90 0.01 95.23 0.00 93.52 0.00 98.22 0.00 92.52 0.00 97.16 0.00 97.27 0.00 97.41 0.06 /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/cover_reg_top/2.flash_ctrl_csr_bit_bash.2224193782
95.91 0.01 95.23 0.00 93.52 0.00 98.22 0.00 92.52 0.00 97.16 0.00 97.27 0.00 97.47 0.06 /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default/10.flash_ctrl_rw.1061873531
95.92 0.01 95.23 0.00 93.52 0.00 98.22 0.00 92.52 0.00 97.16 0.00 97.27 0.00 97.53 0.06 /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default/10.flash_ctrl_sec_info_access.1370456723
95.93 0.01 95.23 0.00 93.52 0.00 98.22 0.00 92.52 0.00 97.16 0.00 97.27 0.00 97.60 0.06 /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default/11.flash_ctrl_intr_rd.2884263245
95.94 0.01 95.23 0.00 93.53 0.02 98.22 0.00 92.52 0.00 97.16 0.00 97.27 0.00 97.63 0.03 /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/cover_reg_top/2.flash_ctrl_tl_errors.512064308
95.94 0.01 95.23 0.00 93.53 0.00 98.27 0.05 92.52 0.00 97.16 0.00 97.27 0.00 97.63 0.00 /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default/0.flash_ctrl_hw_sec_otp.2969828116
95.95 0.01 95.23 0.00 93.58 0.05 98.27 0.00 92.52 0.00 97.16 0.00 97.27 0.00 97.63 0.00 /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default/1.flash_ctrl_phy_arb_redun.1725083833
95.96 0.01 95.23 0.00 93.58 0.00 98.28 0.02 92.52 0.00 97.16 0.00 97.27 0.00 97.66 0.03 /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default/10.flash_ctrl_disable.2771304498
95.96 0.01 95.23 0.00 93.59 0.01 98.31 0.03 92.52 0.00 97.16 0.00 97.27 0.00 97.66 0.00 /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default/1.flash_ctrl_sec_cm.3103814433
95.97 0.01 95.23 0.00 93.60 0.01 98.31 0.00 92.52 0.00 97.16 0.00 97.27 0.00 97.69 0.03 /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default/0.flash_ctrl_full_mem_access.2199420293
95.97 0.01 95.23 0.00 93.61 0.01 98.31 0.00 92.52 0.00 97.16 0.00 97.27 0.00 97.72 0.03 /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default/1.flash_ctrl_config_regwen.3978076409
95.98 0.01 95.23 0.00 93.62 0.01 98.31 0.00 92.52 0.00 97.16 0.00 97.27 0.00 97.75 0.03 /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default/4.flash_ctrl_error_mp.175891237
95.99 0.01 95.23 0.00 93.63 0.01 98.31 0.00 92.52 0.00 97.16 0.00 97.27 0.00 97.78 0.03 /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default/74.flash_ctrl_otp_reset.977964086
95.99 0.01 95.23 0.00 93.67 0.04 98.31 0.00 92.52 0.00 97.16 0.00 97.27 0.00 97.78 0.00 /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default/4.flash_ctrl_phy_arb_redun.4080256851
96.00 0.01 95.23 0.00 93.67 0.00 98.31 0.00 92.52 0.00 97.16 0.00 97.27 0.00 97.81 0.03 /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default/0.flash_ctrl_disable.4112167017
96.00 0.01 95.23 0.00 93.67 0.00 98.31 0.00 92.52 0.00 97.16 0.00 97.27 0.00 97.84 0.03 /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default/12.flash_ctrl_disable.3625139749
96.00 0.01 95.23 0.00 93.67 0.00 98.31 0.00 92.52 0.00 97.16 0.00 97.27 0.00 97.87 0.03 /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default/13.flash_ctrl_rw_evict.3088292485
96.01 0.01 95.23 0.00 93.67 0.00 98.31 0.00 92.52 0.00 97.16 0.00 97.27 0.00 97.90 0.03 /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default/14.flash_ctrl_sec_info_access.1435780842
96.01 0.01 95.23 0.00 93.67 0.00 98.31 0.00 92.52 0.00 97.16 0.00 97.27 0.00 97.93 0.03 /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default/19.flash_ctrl_disable.3170071005
96.02 0.01 95.23 0.00 93.67 0.00 98.31 0.00 92.52 0.00 97.16 0.00 97.27 0.00 97.97 0.03 /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default/22.flash_ctrl_intr_rd.2885862967
96.02 0.01 95.23 0.00 93.67 0.00 98.31 0.00 92.52 0.00 97.16 0.00 97.27 0.00 98.00 0.03 /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default/26.flash_ctrl_sec_info_access.1485527172
96.03 0.01 95.23 0.00 93.67 0.00 98.31 0.00 92.52 0.00 97.16 0.00 97.27 0.00 98.03 0.03 /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default/3.flash_ctrl_disable.674120837
96.03 0.01 95.23 0.00 93.67 0.00 98.31 0.00 92.52 0.00 97.16 0.00 97.27 0.00 98.06 0.03 /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default/3.flash_ctrl_fs_sup.3366051207
96.04 0.01 95.23 0.00 93.67 0.00 98.31 0.00 92.52 0.00 97.16 0.00 97.27 0.00 98.09 0.03 /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default/30.flash_ctrl_rw_evict_all_en.3282843955
96.04 0.01 95.23 0.00 93.67 0.00 98.31 0.00 92.52 0.00 97.16 0.00 97.27 0.00 98.12 0.03 /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default/30.flash_ctrl_sec_info_access.1545417969
96.04 0.01 95.23 0.00 93.67 0.00 98.31 0.00 92.52 0.00 97.16 0.00 97.27 0.00 98.15 0.03 /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default/33.flash_ctrl_sec_info_access.3378206144
96.05 0.01 95.23 0.00 93.67 0.00 98.31 0.00 92.52 0.00 97.16 0.00 97.27 0.00 98.18 0.03 /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default/43.flash_ctrl_disable.804701948
96.05 0.01 95.23 0.00 93.70 0.03 98.31 0.00 92.52 0.00 97.16 0.00 97.27 0.00 98.18 0.00 /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default/0.flash_ctrl_intr_wr.3340791835
96.06 0.01 95.23 0.00 93.73 0.03 98.31 0.00 92.52 0.00 97.16 0.00 97.27 0.00 98.18 0.00 /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default/4.flash_ctrl_phy_ack_consistency.3088385411
96.06 0.01 95.23 0.00 93.74 0.02 98.31 0.00 92.52 0.00 97.16 0.00 97.27 0.00 98.18 0.00 /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/cover_reg_top/0.flash_ctrl_csr_aliasing.238937663
96.06 0.01 95.23 0.00 93.76 0.02 98.31 0.00 92.52 0.00 97.16 0.00 97.27 0.00 98.18 0.00 /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default/14.flash_ctrl_intr_rd.1202751435
96.07 0.01 95.23 0.00 93.78 0.02 98.31 0.00 92.52 0.00 97.16 0.00 97.27 0.00 98.18 0.00 /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default/2.flash_ctrl_ro_serr.870045294
96.07 0.01 95.23 0.00 93.79 0.01 98.31 0.00 92.52 0.00 97.16 0.00 97.27 0.00 98.18 0.00 /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default/1.flash_ctrl_wr_intg.1144880736
96.07 0.01 95.23 0.00 93.80 0.01 98.31 0.00 92.52 0.00 97.16 0.00 97.27 0.00 98.18 0.00 /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default/11.flash_ctrl_hw_read_seed_err.3079738501
96.07 0.01 95.23 0.00 93.81 0.01 98.31 0.00 92.52 0.00 97.16 0.00 97.27 0.00 98.18 0.00 /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default/2.flash_ctrl_host_ctrl_arb.2966745914
96.07 0.01 95.23 0.00 93.82 0.01 98.31 0.00 92.52 0.00 97.16 0.00 97.27 0.00 98.18 0.00 /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default/3.flash_ctrl_phy_arb_redun.3893975513
96.07 0.01 95.23 0.00 93.83 0.01 98.31 0.00 92.52 0.00 97.16 0.00 97.27 0.00 98.18 0.00 /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default/34.flash_ctrl_otp_reset.3946837004

Tests that do not contribute to grading

Name
/workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/cover_reg_top/0.flash_ctrl_csr_bit_bash.3471938198
/workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/cover_reg_top/0.flash_ctrl_csr_rw.2790801569
/workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/cover_reg_top/0.flash_ctrl_mem_walk.129456065
/workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/cover_reg_top/0.flash_ctrl_same_csr_outstanding.705704815
/workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/cover_reg_top/0.flash_ctrl_shadow_reg_errors.2008148022
/workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/cover_reg_top/0.flash_ctrl_shadow_reg_errors_with_csr_rw.2759118574
/workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/cover_reg_top/1.flash_ctrl_csr_hw_reset.2697596500
/workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/cover_reg_top/1.flash_ctrl_csr_mem_rw_with_rand_reset.2333718495
/workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/cover_reg_top/1.flash_ctrl_csr_rw.1256011416
/workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/cover_reg_top/1.flash_ctrl_intr_test.2262135525
/workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/cover_reg_top/1.flash_ctrl_mem_partial_access.2256600070
/workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/cover_reg_top/1.flash_ctrl_mem_walk.1776693992
/workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/cover_reg_top/1.flash_ctrl_same_csr_outstanding.1270972986
/workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/cover_reg_top/1.flash_ctrl_shadow_reg_errors.3999043237
/workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/cover_reg_top/1.flash_ctrl_shadow_reg_errors_with_csr_rw.2073982273
/workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/cover_reg_top/1.flash_ctrl_tl_errors.1933302241
/workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/cover_reg_top/1.flash_ctrl_tl_intg_err.681164675
/workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/cover_reg_top/10.flash_ctrl_csr_mem_rw_with_rand_reset.1224320092
/workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/cover_reg_top/10.flash_ctrl_csr_rw.3304878682
/workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/cover_reg_top/10.flash_ctrl_intr_test.3426513390
/workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/cover_reg_top/10.flash_ctrl_same_csr_outstanding.1711156427
/workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/cover_reg_top/10.flash_ctrl_shadow_reg_errors.2973077682
/workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/cover_reg_top/10.flash_ctrl_shadow_reg_errors_with_csr_rw.3927234032
/workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/cover_reg_top/10.flash_ctrl_tl_intg_err.1644769515
/workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/cover_reg_top/11.flash_ctrl_csr_mem_rw_with_rand_reset.506229404
/workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/cover_reg_top/11.flash_ctrl_csr_rw.1455779649
/workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/cover_reg_top/11.flash_ctrl_intr_test.3713111317
/workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/cover_reg_top/11.flash_ctrl_same_csr_outstanding.2190873186
/workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/cover_reg_top/11.flash_ctrl_shadow_reg_errors.2446257709
/workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/cover_reg_top/11.flash_ctrl_shadow_reg_errors_with_csr_rw.3763036335
/workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/cover_reg_top/11.flash_ctrl_tl_errors.275219823
/workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/cover_reg_top/11.flash_ctrl_tl_intg_err.994759811
/workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/cover_reg_top/12.flash_ctrl_csr_mem_rw_with_rand_reset.2646743265
/workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/cover_reg_top/12.flash_ctrl_csr_rw.2077910283
/workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/cover_reg_top/12.flash_ctrl_intr_test.1362145319
/workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/cover_reg_top/12.flash_ctrl_same_csr_outstanding.1472613526
/workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/cover_reg_top/12.flash_ctrl_shadow_reg_errors.2942082612
/workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/cover_reg_top/12.flash_ctrl_shadow_reg_errors_with_csr_rw.2457249081
/workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/cover_reg_top/12.flash_ctrl_tl_errors.4025212101
/workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/cover_reg_top/12.flash_ctrl_tl_intg_err.2991581569
/workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/cover_reg_top/13.flash_ctrl_csr_mem_rw_with_rand_reset.4226615415
/workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/cover_reg_top/13.flash_ctrl_csr_rw.3007274801
/workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/cover_reg_top/13.flash_ctrl_intr_test.1049053074
/workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/cover_reg_top/13.flash_ctrl_same_csr_outstanding.4096782280
/workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/cover_reg_top/13.flash_ctrl_shadow_reg_errors.797136953
/workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/cover_reg_top/13.flash_ctrl_shadow_reg_errors_with_csr_rw.3218632157
/workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/cover_reg_top/13.flash_ctrl_tl_errors.519892475
/workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/cover_reg_top/14.flash_ctrl_csr_mem_rw_with_rand_reset.3063852157
/workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/cover_reg_top/14.flash_ctrl_csr_rw.1003107681
/workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/cover_reg_top/14.flash_ctrl_intr_test.161091762
/workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/cover_reg_top/14.flash_ctrl_same_csr_outstanding.234138626
/workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/cover_reg_top/14.flash_ctrl_shadow_reg_errors.2348925060
/workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/cover_reg_top/14.flash_ctrl_shadow_reg_errors_with_csr_rw.168373182
/workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/cover_reg_top/14.flash_ctrl_tl_errors.1481287739
/workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/cover_reg_top/14.flash_ctrl_tl_intg_err.2224669346
/workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/cover_reg_top/15.flash_ctrl_csr_mem_rw_with_rand_reset.3778990787
/workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/cover_reg_top/15.flash_ctrl_csr_rw.964109675
/workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/cover_reg_top/15.flash_ctrl_intr_test.3479437595
/workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/cover_reg_top/15.flash_ctrl_same_csr_outstanding.4282497327
/workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/cover_reg_top/15.flash_ctrl_shadow_reg_errors.2039753927
/workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/cover_reg_top/15.flash_ctrl_shadow_reg_errors_with_csr_rw.3333063085
/workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/cover_reg_top/15.flash_ctrl_tl_errors.2859925417
/workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/cover_reg_top/15.flash_ctrl_tl_intg_err.705571605
/workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/cover_reg_top/16.flash_ctrl_csr_mem_rw_with_rand_reset.468362451
/workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/cover_reg_top/16.flash_ctrl_csr_rw.941776563
/workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/cover_reg_top/16.flash_ctrl_intr_test.3286660148
/workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/cover_reg_top/16.flash_ctrl_same_csr_outstanding.1348740199
/workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/cover_reg_top/16.flash_ctrl_shadow_reg_errors.2761831356
/workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/cover_reg_top/16.flash_ctrl_shadow_reg_errors_with_csr_rw.2880493284
/workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/cover_reg_top/16.flash_ctrl_tl_errors.1490999548
/workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/cover_reg_top/16.flash_ctrl_tl_intg_err.474657974
/workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/cover_reg_top/17.flash_ctrl_csr_mem_rw_with_rand_reset.1573926709
/workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/cover_reg_top/17.flash_ctrl_csr_rw.2870457579
/workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/cover_reg_top/17.flash_ctrl_intr_test.3004062839
/workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/cover_reg_top/17.flash_ctrl_same_csr_outstanding.993983658
/workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/cover_reg_top/17.flash_ctrl_shadow_reg_errors.446977277
/workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/cover_reg_top/17.flash_ctrl_shadow_reg_errors_with_csr_rw.410666125
/workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/cover_reg_top/17.flash_ctrl_tl_errors.3146753768
/workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/cover_reg_top/18.flash_ctrl_csr_mem_rw_with_rand_reset.3427160051
/workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/cover_reg_top/18.flash_ctrl_csr_rw.3080698499
/workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/cover_reg_top/18.flash_ctrl_intr_test.3019318089
/workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/cover_reg_top/18.flash_ctrl_same_csr_outstanding.56824946
/workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/cover_reg_top/18.flash_ctrl_shadow_reg_errors.3331103763
/workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/cover_reg_top/18.flash_ctrl_shadow_reg_errors_with_csr_rw.156862794
/workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/cover_reg_top/18.flash_ctrl_tl_errors.2999394717
/workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/cover_reg_top/18.flash_ctrl_tl_intg_err.1094185655
/workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/cover_reg_top/19.flash_ctrl_csr_mem_rw_with_rand_reset.148085099
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/workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default/9.flash_ctrl_rw_evict.3277551485
/workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default/9.flash_ctrl_rw_evict_all_en.169948172
/workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default/9.flash_ctrl_rw_serr.3125870857
/workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default/9.flash_ctrl_sec_info_access.1285351161
/workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default/9.flash_ctrl_smoke.528535276
/workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default/9.flash_ctrl_wo.2933986256



Total test records in report: 1273
tests.html | tests1.html | tests2.html | tests3.html | tests4.html | tests5.html | tests6.html | tests7.html | tests8.html | tests9.html | tests10.html | tests11.html | tests12.html | tests13.html | tests14.html | tests15.html | tests16.html | tests17.html | tests18.html | tests19.html | tests20.html | tests21.html | tests22.html | tests23.html | tests24.html | tests25.html | tests26.html
TEST NOTEST LOCATIONTEST NAMESTATUSSTARTEDFINISHEDSIMULATION TIME
T1 /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default/0.flash_ctrl_smoke_hw.990372862 Oct 09 07:04:27 PM UTC 24 Oct 09 07:05:11 PM UTC 24 23845800 ps
T2 /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default/0.flash_ctrl_sw_op.1452243940 Oct 09 07:04:35 PM UTC 24 Oct 09 07:05:18 PM UTC 24 34990900 ps
T3 /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default/0.flash_ctrl_host_dir_rd.2606157977 Oct 09 07:04:35 PM UTC 24 Oct 09 07:05:18 PM UTC 24 64731600 ps
T9 /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default/0.flash_ctrl_hw_sec_otp.2969828116 Oct 09 07:04:37 PM UTC 24 Oct 09 07:05:41 PM UTC 24 5000205200 ps
T17 /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default/0.flash_ctrl_smoke.3120199217 Oct 09 07:04:26 PM UTC 24 Oct 09 07:06:30 PM UTC 24 146777200 ps
T12 /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default/0.flash_ctrl_fetch_code.3271395311 Oct 09 07:06:31 PM UTC 24 Oct 09 07:07:04 PM UTC 24 1396902700 ps
T18 /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default/0.flash_ctrl_rd_buff_evict.2697346295 Oct 09 07:04:36 PM UTC 24 Oct 09 07:07:24 PM UTC 24 201804200 ps
T4 /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default/0.flash_ctrl_otp_reset.2291773828 Oct 09 07:05:19 PM UTC 24 Oct 09 07:08:54 PM UTC 24 72422100 ps
T10 /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default/0.flash_ctrl_write_word_sweep.933587196 Oct 09 07:08:57 PM UTC 24 Oct 09 07:09:22 PM UTC 24 50093300 ps
T19 /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default/0.flash_ctrl_read_word_sweep.1656734565 Oct 09 07:09:23 PM UTC 24 Oct 09 07:09:46 PM UTC 24 24776000 ps
T32 /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default/0.flash_ctrl_invalid_op.4264466975 Oct 09 07:08:31 PM UTC 24 Oct 09 07:10:10 PM UTC 24 916197700 ps
T66 /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default/0.flash_ctrl_read_word_sweep_serr.2755691130 Oct 09 07:09:54 PM UTC 24 Oct 09 07:10:30 PM UTC 24 45237300 ps
T11 /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default/0.flash_ctrl_mid_op_rst.3309074478 Oct 09 07:08:38 PM UTC 24 Oct 09 07:10:37 PM UTC 24 8645530900 ps
T71 /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default/0.flash_ctrl_wo.2112383905 Oct 09 07:08:54 PM UTC 24 Oct 09 07:11:30 PM UTC 24 16859246100 ps
T13 /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default/0.flash_ctrl_ro.1432572709 Oct 09 07:09:30 PM UTC 24 Oct 09 07:11:33 PM UTC 24 505207100 ps
T48 /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default/0.flash_ctrl_serr_counter.779773160 Oct 09 07:10:37 PM UTC 24 Oct 09 07:11:38 PM UTC 24 292021900 ps
T53 /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default/0.flash_ctrl_read_word_sweep_derr.2138208255 Oct 09 07:11:32 PM UTC 24 Oct 09 07:12:07 PM UTC 24 17717000 ps
T49 /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default/0.flash_ctrl_ro_serr.2806344911 Oct 09 07:10:11 PM UTC 24 Oct 09 07:12:51 PM UTC 24 2601995200 ps
T70 /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default/0.flash_ctrl_serr_address.3889637086 Oct 09 07:11:25 PM UTC 24 Oct 09 07:13:01 PM UTC 24 2545476400 ps
T28 /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default/0.flash_ctrl_erase_suspend.3797731304 Oct 09 07:04:37 PM UTC 24 Oct 09 07:13:10 PM UTC 24 3674015700 ps
T72 /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default/0.flash_ctrl_prog_reset.1651846176 Oct 09 07:13:34 PM UTC 24 Oct 09 07:13:57 PM UTC 24 42419800 ps
T50 /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default/0.flash_ctrl_rw_serr.3693167144 Oct 09 07:10:31 PM UTC 24 Oct 09 07:14:11 PM UTC 24 2534812200 ps
T54 /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default/0.flash_ctrl_phy_arb.555683805 Oct 09 07:04:37 PM UTC 24 Oct 09 07:14:25 PM UTC 24 315363800 ps
T61 /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default/0.flash_ctrl_ro_derr.767847560 Oct 09 07:11:35 PM UTC 24 Oct 09 07:14:29 PM UTC 24 1426757500 ps
T33 /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default/0.flash_ctrl_intr_wr.3340791835 Oct 09 07:13:01 PM UTC 24 Oct 09 07:14:43 PM UTC 24 11156232200 ps
T29 /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default/0.flash_ctrl_mp_regions.211846843 Oct 09 07:05:41 PM UTC 24 Oct 09 07:14:44 PM UTC 24 15385712500 ps
T34 /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default/0.flash_ctrl_rw_evict.2203153523 Oct 09 07:13:58 PM UTC 24 Oct 09 07:14:45 PM UTC 24 196604900 ps
T35 /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default/0.flash_ctrl_rw_evict_all_en.539557286 Oct 09 07:14:12 PM UTC 24 Oct 09 07:15:01 PM UTC 24 118445100 ps
T5 /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default/0.flash_ctrl_disable.4112167017 Oct 09 07:14:30 PM UTC 24 Oct 09 07:15:05 PM UTC 24 62710000 ps
T62 /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default/0.flash_ctrl_rw_derr.1433692496 Oct 09 07:11:39 PM UTC 24 Oct 09 07:15:09 PM UTC 24 1204431100 ps
T37 /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default/0.flash_ctrl_re_evict.3101898237 Oct 09 07:14:26 PM UTC 24 Oct 09 07:15:19 PM UTC 24 100646300 ps
T25 /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default/0.flash_ctrl_connect.1950955128 Oct 09 07:15:02 PM UTC 24 Oct 09 07:15:28 PM UTC 24 50945300 ps
T6 /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default/0.flash_ctrl_access_after_disable.2802181661 Oct 09 07:15:11 PM UTC 24 Oct 09 07:15:33 PM UTC 24 41637400 ps
T7 /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default/0.flash_ctrl_wr_intg.3123452590 Oct 09 07:15:10 PM UTC 24 Oct 09 07:15:36 PM UTC 24 46648400 ps
T63 /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default/0.flash_ctrl_rd_intg.3908942252 Oct 09 07:15:06 PM UTC 24 Oct 09 07:15:55 PM UTC 24 287805100 ps
T85 /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default/0.flash_ctrl_phy_arb_redun.824791906 Oct 09 07:15:29 PM UTC 24 Oct 09 07:15:56 PM UTC 24 890026800 ps
T23 /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default/0.flash_ctrl_phy_host_grant_err.4179385541 Oct 09 07:15:34 PM UTC 24 Oct 09 07:15:57 PM UTC 24 57838300 ps
T68 /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default/0.flash_ctrl_phy_ack_consistency.695312467 Oct 09 07:15:37 PM UTC 24 Oct 09 07:16:01 PM UTC 24 25374400 ps
T104 /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default/0.flash_ctrl_fs_sup.1750075789 Oct 09 07:15:20 PM UTC 24 Oct 09 07:16:07 PM UTC 24 635475000 ps
T24 /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default/0.flash_ctrl_oversize_error.1709049444 Oct 09 07:12:11 PM UTC 24 Oct 09 07:16:11 PM UTC 24 2127233500 ps
T124 /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default/0.flash_ctrl_config_regwen.2746549888 Oct 09 07:15:55 PM UTC 24 Oct 09 07:16:17 PM UTC 24 27997100 ps
T134 /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default/0.flash_ctrl_lcmgr_intg.692795830 Oct 09 07:15:57 PM UTC 24 Oct 09 07:16:19 PM UTC 24 82244200 ps
T40 /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default/0.flash_ctrl_sec_info_access.27970573 Oct 09 07:14:45 PM UTC 24 Oct 09 07:16:21 PM UTC 24 1625275100 ps
T123 /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default/0.flash_ctrl_hw_read_seed_err.1990668777 Oct 09 07:16:02 PM UTC 24 Oct 09 07:16:24 PM UTC 24 27047300 ps
T57 /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default/0.flash_ctrl_derr_detect.2685540405 Oct 09 07:12:08 PM UTC 24 Oct 09 07:16:25 PM UTC 24 738895800 ps
T110 /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default/0.flash_ctrl_alert_test.4172461997 Oct 09 07:16:20 PM UTC 24 Oct 09 07:16:44 PM UTC 24 34312600 ps
T45 /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default/0.flash_ctrl_intr_rd.169868734 Oct 09 07:12:52 PM UTC 24 Oct 09 07:16:48 PM UTC 24 4301211200 ps
T58 /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default/1.flash_ctrl_smoke_hw.3752543909 Oct 09 07:16:24 PM UTC 24 Oct 09 07:17:04 PM UTC 24 25988700 ps
T379 /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default/0.flash_ctrl_host_addr_infection.357373688 Oct 09 07:16:18 PM UTC 24 Oct 09 07:17:04 PM UTC 24 41001800 ps
T298 /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default/1.flash_ctrl_sw_op.2636221515 Oct 09 07:16:35 PM UTC 24 Oct 09 07:17:16 PM UTC 24 26574700 ps
T377 /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default/0.flash_ctrl_rd_ooo.1791810665 Oct 09 07:16:12 PM UTC 24 Oct 09 07:17:19 PM UTC 24 77567700 ps
T38 /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default/0.flash_ctrl_intr_wr_slow_flash.1636926892 Oct 09 07:13:21 PM UTC 24 Oct 09 07:17:23 PM UTC 24 35230085900 ps
T130 /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default/0.flash_ctrl_hw_prog_rma_wipe_err.2274726405 Oct 09 07:16:08 PM UTC 24 Oct 09 07:17:26 PM UTC 24 10035667700 ps
T212 /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default/1.flash_ctrl_host_dir_rd.2886186595 Oct 09 07:16:44 PM UTC 24 Oct 09 07:17:27 PM UTC 24 74742100 ps
T52 /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default/1.flash_ctrl_fetch_code.282977819 Oct 09 07:17:59 PM UTC 24 Oct 09 07:18:40 PM UTC 24 1317774300 ps
T46 /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default/0.flash_ctrl_intr_rd_slow_flash.539359560 Oct 09 07:13:11 PM UTC 24 Oct 09 07:19:33 PM UTC 24 12507093600 ps
T56 /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default/1.flash_ctrl_smoke.254651067 Oct 09 07:16:22 PM UTC 24 Oct 09 07:19:37 PM UTC 24 103541800 ps
T41 /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default/1.flash_ctrl_mp_regions.3164205905 Oct 09 07:17:28 PM UTC 24 Oct 09 07:19:53 PM UTC 24 6436852500 ps
T114 /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default/1.flash_ctrl_hw_sec_otp.1526949047 Oct 09 07:17:05 PM UTC 24 Oct 09 07:20:24 PM UTC 24 73224578700 ps
T30 /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default/1.flash_ctrl_rd_buff_evict.108280839 Oct 09 07:16:49 PM UTC 24 Oct 09 07:20:25 PM UTC 24 15340339800 ps
T210 /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default/0.flash_ctrl_stress_all.310558950 Oct 09 07:14:46 PM UTC 24 Oct 09 07:20:35 PM UTC 24 53935700 ps
T84 /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default/1.flash_ctrl_otp_reset.1854260877 Oct 09 07:17:24 PM UTC 24 Oct 09 07:21:02 PM UTC 24 40161600 ps
T142 /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default/0.flash_ctrl_rw.2339168009 Oct 09 07:09:47 PM UTC 24 Oct 09 07:21:16 PM UTC 24 18825135200 ps
T89 /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default/1.flash_ctrl_invalid_op.3357516133 Oct 09 07:20:25 PM UTC 24 Oct 09 07:22:00 PM UTC 24 3531198000 ps
T129 /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default/0.flash_ctrl_hw_rma_reset.1474374480 Oct 09 07:05:12 PM UTC 24 Oct 09 07:22:07 PM UTC 24 80147504400 ps
T67 /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default/1.flash_ctrl_mid_op_rst.3295579308 Oct 09 07:20:26 PM UTC 24 Oct 09 07:22:16 PM UTC 24 858247300 ps
T182 /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default/1.flash_ctrl_read_word_sweep_serr.1551436725 Oct 09 07:22:01 PM UTC 24 Oct 09 07:22:37 PM UTC 24 40248600 ps
T183 /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default/0.flash_ctrl_integrity.222485653 Oct 09 07:12:42 PM UTC 24 Oct 09 07:22:42 PM UTC 24 7990950500 ps
T184 /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default/1.flash_ctrl_ro.4274175895 Oct 09 07:21:03 PM UTC 24 Oct 09 07:23:17 PM UTC 24 839594500 ps
T185 /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default/1.flash_ctrl_read_word_sweep_derr.1982553331 Oct 09 07:23:18 PM UTC 24 Oct 09 07:23:54 PM UTC 24 18263800 ps
T186 /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default/1.flash_ctrl_serr_address.2767674936 Oct 09 07:22:42 PM UTC 24 Oct 09 07:24:14 PM UTC 24 2515782700 ps
T187 /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default/1.flash_ctrl_serr_counter.1615090179 Oct 09 07:22:38 PM UTC 24 Oct 09 07:24:15 PM UTC 24 1394159200 ps
T113 /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default/1.flash_ctrl_ro_serr.3157893645 Oct 09 07:22:07 PM UTC 24 Oct 09 07:24:16 PM UTC 24 996917800 ps
T143 /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default/1.flash_ctrl_phy_arb.1281379224 Oct 09 07:16:51 PM UTC 24 Oct 09 07:25:33 PM UTC 24 745685500 ps
T386 /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default/1.flash_ctrl_rw_serr.2519598640 Oct 09 07:22:17 PM UTC 24 Oct 09 07:25:53 PM UTC 24 1391212300 ps
T199 /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default/1.flash_ctrl_ro_derr.230289757 Oct 09 07:23:55 PM UTC 24 Oct 09 07:26:45 PM UTC 24 3117718800 ps
T144 /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default/0.flash_ctrl_rand_ops.2513381743 Oct 09 07:04:32 PM UTC 24 Oct 09 07:27:55 PM UTC 24 588504900 ps
T39 /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default/1.flash_ctrl_intr_wr.2462083317 Oct 09 07:25:53 PM UTC 24 Oct 09 07:27:55 PM UTC 24 48444392300 ps
T156 /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default/1.flash_ctrl_rw_derr.2032301680 Oct 09 07:24:15 PM UTC 24 Oct 09 07:28:10 PM UTC 24 1697606800 ps
T55 /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default/1.flash_ctrl_oversize_error.3440966314 Oct 09 07:24:17 PM UTC 24 Oct 09 07:28:13 PM UTC 24 1409375100 ps
T31 /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default/1.flash_ctrl_erase_suspend.521323846 Oct 09 07:17:06 PM UTC 24 Oct 09 07:28:18 PM UTC 24 7715131200 ps
T261 /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default/1.flash_ctrl_derr_detect.1105777853 Oct 09 07:24:16 PM UTC 24 Oct 09 07:28:51 PM UTC 24 1493960100 ps
T36 /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default/1.flash_ctrl_rw_evict.170697273 Oct 09 07:28:11 PM UTC 24 Oct 09 07:28:58 PM UTC 24 29653500 ps
T51 /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default/1.flash_ctrl_rw_evict_all_en.3630797958 Oct 09 07:28:13 PM UTC 24 Oct 09 07:29:02 PM UTC 24 68012400 ps
T250 /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default/1.flash_ctrl_re_evict.1784988723 Oct 09 07:28:19 PM UTC 24 Oct 09 07:29:10 PM UTC 24 72696700 ps
T424 /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default/1.flash_ctrl_disable.71027558 Oct 09 07:28:52 PM UTC 24 Oct 09 07:29:27 PM UTC 24 11172900 ps
T26 /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default/1.flash_ctrl_connect.3482577027 Oct 09 07:29:28 PM UTC 24 Oct 09 07:29:54 PM UTC 24 27124900 ps
T47 /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default/1.flash_ctrl_intr_rd.831498401 Oct 09 07:25:33 PM UTC 24 Oct 09 07:29:56 PM UTC 24 1593944600 ps
T190 /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default/1.flash_ctrl_sec_info_access.3578542770 Oct 09 07:29:02 PM UTC 24 Oct 09 07:30:18 PM UTC 24 987016100 ps
T8 /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default/1.flash_ctrl_wr_intg.1144880736 Oct 09 07:29:57 PM UTC 24 Oct 09 07:30:22 PM UTC 24 354441700 ps
T425 /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default/1.flash_ctrl_prog_reset.1705049085 Oct 09 07:27:56 PM UTC 24 Oct 09 07:30:36 PM UTC 24 5429301800 ps
T21 /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default/1.flash_ctrl_access_after_disable.2496302609 Oct 09 07:30:19 PM UTC 24 Oct 09 07:30:42 PM UTC 24 14558000 ps
T193 /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default/1.flash_ctrl_rd_intg.3028907907 Oct 09 07:29:55 PM UTC 24 Oct 09 07:30:49 PM UTC 24 86911900 ps
T94 /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default/1.flash_ctrl_phy_arb_redun.1725083833 Oct 09 07:30:37 PM UTC 24 Oct 09 07:31:05 PM UTC 24 665548900 ps
T198 /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default/1.flash_ctrl_rw.3159943924 Oct 09 07:21:18 PM UTC 24 Oct 09 07:31:07 PM UTC 24 50121259900 ps
T215 /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default/1.flash_ctrl_phy_host_grant_err.3329830621 Oct 09 07:30:43 PM UTC 24 Oct 09 07:31:08 PM UTC 24 14462400 ps
T426 /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default/1.flash_ctrl_fs_sup.2101412142 Oct 09 07:30:22 PM UTC 24 Oct 09 07:31:13 PM UTC 24 310330100 ps
T69 /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default/1.flash_ctrl_phy_ack_consistency.1079560870 Oct 09 07:30:49 PM UTC 24 Oct 09 07:31:13 PM UTC 24 25283900 ps
T204 /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default/1.flash_ctrl_config_regwen.3978076409 Oct 09 07:31:05 PM UTC 24 Oct 09 07:31:27 PM UTC 24 40760000 ps
T167 /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default/1.flash_ctrl_lcmgr_intg.2618191379 Oct 09 07:31:09 PM UTC 24 Oct 09 07:31:31 PM UTC 24 25006700 ps
T165 /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default/1.flash_ctrl_hw_read_seed_err.1883227881 Oct 09 07:31:14 PM UTC 24 Oct 09 07:31:36 PM UTC 24 16629500 ps
T111 /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default/1.flash_ctrl_alert_test.1127180063 Oct 09 07:31:32 PM UTC 24 Oct 09 07:31:55 PM UTC 24 68407200 ps
T157 /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default/1.flash_ctrl_hw_prog_rma_wipe_err.2813496145 Oct 09 07:31:15 PM UTC 24 Oct 09 07:32:15 PM UTC 24 10080040100 ps
T288 /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default/1.flash_ctrl_host_addr_infection.2684810304 Oct 09 07:31:28 PM UTC 24 Oct 09 07:32:17 PM UTC 24 65826400 ps
T131 /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default/1.flash_ctrl_hw_rma_reset.2638224347 Oct 09 07:17:20 PM UTC 24 Oct 09 07:32:31 PM UTC 24 40122601200 ps
T209 /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default/2.flash_ctrl_smoke_hw.420354363 Oct 09 07:31:56 PM UTC 24 Oct 09 07:32:39 PM UTC 24 31571300 ps
T80 /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default/1.flash_ctrl_intr_rd_slow_flash.1373626145 Oct 09 07:26:45 PM UTC 24 Oct 09 07:32:49 PM UTC 24 35208940200 ps
T294 /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default/2.flash_ctrl_sw_op.2778711166 Oct 09 07:32:17 PM UTC 24 Oct 09 07:32:59 PM UTC 24 24382500 ps
T427 /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default/1.flash_ctrl_intr_wr_slow_flash.4283169116 Oct 09 07:27:56 PM UTC 24 Oct 09 07:33:14 PM UTC 24 45751571800 ps
T211 /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default/2.flash_ctrl_smoke.1342121863 Oct 09 07:31:37 PM UTC 24 Oct 09 07:33:35 PM UTC 24 55679900 ps
T98 /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default/0.flash_ctrl_rma_err.2983213037 Oct 09 07:15:57 PM UTC 24 Oct 09 07:33:36 PM UTC 24 165690267800 ps
T213 /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default/0.flash_ctrl_error_prog_win.2582298280 Oct 09 07:07:25 PM UTC 24 Oct 09 07:33:44 PM UTC 24 764134700 ps
T122 /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default/2.flash_ctrl_hw_sec_otp.393330862 Oct 09 07:33:00 PM UTC 24 Oct 09 07:34:05 PM UTC 24 1444184300 ps
T214 /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default/2.flash_ctrl_host_dir_rd.1344459719 Oct 09 07:32:31 PM UTC 24 Oct 09 07:34:28 PM UTC 24 145282000 ps
T219 /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default/2.flash_ctrl_rd_buff_evict.1022973617 Oct 09 07:32:40 PM UTC 24 Oct 09 07:36:12 PM UTC 24 1465471300 ps
T378 /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default/1.flash_ctrl_integrity.3008498406 Oct 09 07:24:47 PM UTC 24 Oct 09 07:36:38 PM UTC 24 5125673600 ps
T59 /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default/2.flash_ctrl_fetch_code.3284114503 Oct 09 07:36:14 PM UTC 24 Oct 09 07:36:55 PM UTC 24 403246900 ps
T86 /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default/2.flash_ctrl_otp_reset.2706929247 Oct 09 07:33:44 PM UTC 24 Oct 09 07:37:11 PM UTC 24 36009800 ps
T428 /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default/2.flash_ctrl_read_word_sweep_serr.1305559149 Oct 09 07:36:38 PM UTC 24 Oct 09 07:37:14 PM UTC 24 39172400 ps
T384 /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default/2.flash_ctrl_read_word_sweep_derr.3782272861 Oct 09 07:36:39 PM UTC 24 Oct 09 07:37:17 PM UTC 24 154910400 ps
T385 /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default/2.flash_ctrl_serr_counter.2707893185 Oct 09 07:36:39 PM UTC 24 Oct 09 07:37:52 PM UTC 24 1841183700 ps
T145 /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default/2.flash_ctrl_invalid_op.2076181361 Oct 09 07:36:27 PM UTC 24 Oct 09 07:38:06 PM UTC 24 883911500 ps
T383 /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default/2.flash_ctrl_serr_address.2112957137 Oct 09 07:36:39 PM UTC 24 Oct 09 07:38:11 PM UTC 24 645088800 ps
T81 /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default/2.flash_ctrl_mid_op_rst.2032973229 Oct 09 07:36:27 PM UTC 24 Oct 09 07:38:15 PM UTC 24 1257708500 ps
T99 /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default/0.flash_ctrl_hw_rma.1468251436 Oct 09 07:04:43 PM UTC 24 Oct 09 07:38:19 PM UTC 24 168993621600 ps
T382 /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default/2.flash_ctrl_intr_wr.3178111251 Oct 09 07:37:12 PM UTC 24 Oct 09 07:38:32 PM UTC 24 7751492500 ps
T202 /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default/2.flash_ctrl_ro.2769407408 Oct 09 07:36:28 PM UTC 24 Oct 09 07:38:45 PM UTC 24 523975000 ps
T422 /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default/2.flash_ctrl_rw_evict_all_en.1534611706 Oct 09 07:38:02 PM UTC 24 Oct 09 07:38:48 PM UTC 24 49875300 ps
T429 /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default/2.flash_ctrl_disable.1849258432 Oct 09 07:38:12 PM UTC 24 Oct 09 07:38:49 PM UTC 24 14735700 ps
T289 /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default/2.flash_ctrl_rw_evict.1359019518 Oct 09 07:37:59 PM UTC 24 Oct 09 07:38:53 PM UTC 24 28014500 ps
T146 /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default/2.flash_ctrl_re_evict.2435480620 Oct 09 07:38:07 PM UTC 24 Oct 09 07:39:03 PM UTC 24 236850100 ps
T196 /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default/2.flash_ctrl_ro_serr.870045294 Oct 09 07:36:38 PM UTC 24 Oct 09 07:39:05 PM UTC 24 1172315400 ps
T27 /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default/2.flash_ctrl_connect.595097547 Oct 09 07:38:44 PM UTC 24 Oct 09 07:39:12 PM UTC 24 23900700 ps
T22 /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default/2.flash_ctrl_access_after_disable.2574311227 Oct 09 07:38:50 PM UTC 24 Oct 09 07:39:13 PM UTC 24 13163500 ps
T20 /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default/2.flash_ctrl_wr_intg.1908883095 Oct 09 07:38:49 PM UTC 24 Oct 09 07:39:23 PM UTC 24 77700500 ps
T82 /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default/2.flash_ctrl_mp_regions.114296725 Oct 09 07:34:28 PM UTC 24 Oct 09 07:39:26 PM UTC 24 20083285100 ps
T42 /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default/2.flash_ctrl_intr_rd.3872679415 Oct 09 07:37:02 PM UTC 24 Oct 09 07:39:31 PM UTC 24 553361600 ps
T95 /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default/2.flash_ctrl_phy_arb_redun.66213646 Oct 09 07:38:54 PM UTC 24 Oct 09 07:39:35 PM UTC 24 876793500 ps
T90 /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default/2.flash_ctrl_phy_host_grant_err.1895808236 Oct 09 07:39:04 PM UTC 24 Oct 09 07:39:35 PM UTC 24 28752400 ps
T351 /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default/2.flash_ctrl_config_regwen.3554459003 Oct 09 07:39:12 PM UTC 24 Oct 09 07:39:35 PM UTC 24 37240800 ps
T252 /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default/2.flash_ctrl_rd_intg.2950184655 Oct 09 07:38:46 PM UTC 24 Oct 09 07:39:35 PM UTC 24 115730800 ps
T216 /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default/2.flash_ctrl_phy_ack_consistency.2074032348 Oct 09 07:39:06 PM UTC 24 Oct 09 07:39:37 PM UTC 24 24132000 ps
T430 /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default/2.flash_ctrl_wo.1461505497 Oct 09 07:36:27 PM UTC 24 Oct 09 07:39:39 PM UTC 24 2092498700 ps
T397 /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default/2.flash_ctrl_fs_sup.3219943824 Oct 09 07:38:52 PM UTC 24 Oct 09 07:39:41 PM UTC 24 299277400 ps
T194 /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default/2.flash_ctrl_ro_derr.1964489024 Oct 09 07:36:41 PM UTC 24 Oct 09 07:39:44 PM UTC 24 975345400 ps
T168 /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default/2.flash_ctrl_lcmgr_intg.3096148659 Oct 09 07:39:25 PM UTC 24 Oct 09 07:39:47 PM UTC 24 25952300 ps
T166 /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default/2.flash_ctrl_hw_read_seed_err.315455009 Oct 09 07:39:28 PM UTC 24 Oct 09 07:39:51 PM UTC 24 49050700 ps
T191 /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default/2.flash_ctrl_sec_info_access.2957952588 Oct 09 07:38:20 PM UTC 24 Oct 09 07:39:54 PM UTC 24 1572151000 ps
T112 /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default/2.flash_ctrl_alert_test.2238671608 Oct 09 07:39:36 PM UTC 24 Oct 09 07:39:58 PM UTC 24 160458800 ps
T431 /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default/2.flash_ctrl_host_addr_infection.709207056 Oct 09 07:39:31 PM UTC 24 Oct 09 07:40:20 PM UTC 24 27237100 ps
T432 /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default/3.flash_ctrl_smoke_hw.3941190749 Oct 09 07:39:36 PM UTC 24 Oct 09 07:40:20 PM UTC 24 25144900 ps
T433 /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default/2.flash_ctrl_phy_arb.1645986180 Oct 09 07:32:50 PM UTC 24 Oct 09 07:40:20 PM UTC 24 76059800 ps
T434 /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default/3.flash_ctrl_sw_op.1220352675 Oct 09 07:39:37 PM UTC 24 Oct 09 07:40:26 PM UTC 24 95432100 ps
T60 /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default/3.flash_ctrl_fetch_code.4182255758 Oct 09 07:39:55 PM UTC 24 Oct 09 07:40:29 PM UTC 24 638603900 ps
T435 /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default/3.flash_ctrl_hw_sec_otp.3280570760 Oct 09 07:39:41 PM UTC 24 Oct 09 07:40:43 PM UTC 24 649847900 ps
T436 /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default/2.flash_ctrl_intr_rd_slow_flash.3811466673 Oct 09 07:37:14 PM UTC 24 Oct 09 07:40:49 PM UTC 24 22796093800 ps
T287 /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default/2.flash_ctrl_derr_detect.1883023276 Oct 09 07:36:47 PM UTC 24 Oct 09 07:40:54 PM UTC 24 2114080500 ps
T296 /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default/2.flash_ctrl_rw_serr.384484849 Oct 09 07:36:39 PM UTC 24 Oct 09 07:40:57 PM UTC 24 6525564200 ps
T192 /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default/2.flash_ctrl_hw_prog_rma_wipe_err.3115565256 Oct 09 07:39:28 PM UTC 24 Oct 09 07:41:03 PM UTC 24 10036018200 ps
T437 /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default/2.flash_ctrl_oversize_error.553183534 Oct 09 07:36:48 PM UTC 24 Oct 09 07:41:16 PM UTC 24 7496489500 ps
T438 /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default/2.flash_ctrl_rw_derr.1009495419 Oct 09 07:36:45 PM UTC 24 Oct 09 07:41:17 PM UTC 24 1494218600 ps
T439 /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default/3.flash_ctrl_read_word_sweep_serr.586682072 Oct 09 07:40:50 PM UTC 24 Oct 09 07:41:22 PM UTC 24 168244100 ps
T152 /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default/3.flash_ctrl_invalid_op.1980242534 Oct 09 07:40:27 PM UTC 24 Oct 09 07:41:36 PM UTC 24 4650793300 ps
T153 /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default/1.flash_ctrl_rand_ops.2926321256 Oct 09 07:16:26 PM UTC 24 Oct 09 07:41:37 PM UTC 24 125133400 ps
T440 /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default/3.flash_ctrl_rand_ops.3226056729 Oct 09 07:39:36 PM UTC 24 Oct 09 07:41:40 PM UTC 24 25469100 ps
T441 /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default/3.flash_ctrl_read_word_sweep_derr.3437766940 Oct 09 07:41:18 PM UTC 24 Oct 09 07:41:48 PM UTC 24 58658800 ps
T442 /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default/3.flash_ctrl_host_dir_rd.2128309422 Oct 09 07:39:38 PM UTC 24 Oct 09 07:41:49 PM UTC 24 53377100 ps
T274 /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default/1.flash_ctrl_error_prog_win.2082235987 Oct 09 07:19:38 PM UTC 24 Oct 09 07:41:57 PM UTC 24 2072510900 ps
T443 /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default/3.flash_ctrl_rd_buff_evict.3979374273 Oct 09 07:39:40 PM UTC 24 Oct 09 07:42:10 PM UTC 24 76914100 ps
T444 /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default/2.flash_ctrl_prog_reset.4024691405 Oct 09 07:37:52 PM UTC 24 Oct 09 07:42:15 PM UTC 24 2437133700 ps
T445 /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default/3.flash_ctrl_prog_reset.27775872 Oct 09 07:41:58 PM UTC 24 Oct 09 07:42:17 PM UTC 24 30941600 ps
T446 /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default/3.flash_ctrl_smoke.728499722 Oct 09 07:39:36 PM UTC 24 Oct 09 07:42:29 PM UTC 24 134354300 ps
T248 /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default/3.flash_ctrl_ro.3066972069 Oct 09 07:40:44 PM UTC 24 Oct 09 07:42:35 PM UTC 24 545302600 ps
T447 /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default/3.flash_ctrl_serr_counter.2398069918 Oct 09 07:41:05 PM UTC 24 Oct 09 07:42:41 PM UTC 24 987279300 ps
T400 /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default/3.flash_ctrl_rw_evict.2726655220 Oct 09 07:42:06 PM UTC 24 Oct 09 07:42:46 PM UTC 24 112366200 ps
T407 /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default/3.flash_ctrl_rw_evict_all_en.1892894826 Oct 09 07:42:11 PM UTC 24 Oct 09 07:42:51 PM UTC 24 69318800 ps
T78 /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default/3.flash_ctrl_mid_op_rst.418732840 Oct 09 07:40:29 PM UTC 24 Oct 09 07:42:55 PM UTC 24 671980400 ps
T115 /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default/3.flash_ctrl_disable.674120837 Oct 09 07:42:18 PM UTC 24 Oct 09 07:42:56 PM UTC 24 10181200 ps
T218 /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default/2.flash_ctrl_erase_suspend.1681321365 Oct 09 07:33:15 PM UTC 24 Oct 09 07:42:56 PM UTC 24 2130607100 ps
T173 /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default/3.flash_ctrl_otp_reset.3680017465 Oct 09 07:39:48 PM UTC 24 Oct 09 07:42:59 PM UTC 24 69715400 ps
T403 /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default/3.flash_ctrl_re_evict.1724234918 Oct 09 07:42:16 PM UTC 24 Oct 09 07:43:01 PM UTC 24 78725800 ps
T448 /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default/3.flash_ctrl_serr_address.1979578951 Oct 09 07:41:17 PM UTC 24 Oct 09 07:43:03 PM UTC 24 3704010300 ps
T449 /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default/3.flash_ctrl_connect.886596686 Oct 09 07:42:42 PM UTC 24 Oct 09 07:43:03 PM UTC 24 24319100 ps
T217 /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default/3.flash_ctrl_phy_ack_consistency.1416347121 Oct 09 07:42:57 PM UTC 24 Oct 09 07:43:21 PM UTC 24 99897700 ps
T450 /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default/3.flash_ctrl_phy_host_grant_err.2428150493 Oct 09 07:42:52 PM UTC 24 Oct 09 07:43:22 PM UTC 24 43889900 ps
T451 /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default/3.flash_ctrl_hw_read_seed_err.2498175238 Oct 09 07:43:01 PM UTC 24 Oct 09 07:43:26 PM UTC 24 67951600 ps
T452 /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default/3.flash_ctrl_intr_wr.1931168497 Oct 09 07:41:46 PM UTC 24 Oct 09 07:43:27 PM UTC 24 7515829500 ps
T453 /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default/3.flash_ctrl_ro_serr.529701540 Oct 09 07:40:56 PM UTC 24 Oct 09 07:43:27 PM UTC 24 1602952600 ps
T269 /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default/3.flash_ctrl_lcmgr_intg.2990157635 Oct 09 07:42:58 PM UTC 24 Oct 09 07:43:27 PM UTC 24 25889100 ps
T454 /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default/3.flash_ctrl_config_regwen.1320517552 Oct 09 07:42:58 PM UTC 24 Oct 09 07:43:28 PM UTC 24 74760100 ps
T398 /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default/3.flash_ctrl_fs_sup.3366051207 Oct 09 07:42:46 PM UTC 24 Oct 09 07:43:29 PM UTC 24 336921200 ps
T97 /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default/3.flash_ctrl_phy_arb_redun.3893975513 Oct 09 07:42:47 PM UTC 24 Oct 09 07:43:31 PM UTC 24 876100400 ps
T455 /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default/3.flash_ctrl_wo.3099387521 Oct 09 07:40:30 PM UTC 24 Oct 09 07:43:33 PM UTC 24 4356202000 ps
T295 /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default/3.flash_ctrl_alert_test.1498295491 Oct 09 07:43:03 PM UTC 24 Oct 09 07:43:33 PM UTC 24 52177800 ps
T456 /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default/4.flash_ctrl_smoke_hw.3809442728 Oct 09 07:43:04 PM UTC 24 Oct 09 07:43:45 PM UTC 24 32007900 ps
T203 /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default/3.flash_ctrl_intr_rd.1217349723 Oct 09 07:41:41 PM UTC 24 Oct 09 07:43:49 PM UTC 24 470499200 ps
T457 /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default/4.flash_ctrl_host_dir_rd.4104443153 Oct 09 07:43:26 PM UTC 24 Oct 09 07:44:04 PM UTC 24 40009800 ps
T356 /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default/3.flash_ctrl_sec_info_access.1132285538 Oct 09 07:42:35 PM UTC 24 Oct 09 07:44:07 PM UTC 24 2095407900 ps
T458 /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default/3.flash_ctrl_rw_serr.1550776826 Oct 09 07:40:58 PM UTC 24 Oct 09 07:44:13 PM UTC 24 1613802300 ps
T459 /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default/4.flash_ctrl_sw_op.708430134 Oct 09 07:43:23 PM UTC 24 Oct 09 07:44:16 PM UTC 24 22549300 ps
T267 /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default/3.flash_ctrl_hw_prog_rma_wipe_err.315307710 Oct 09 07:43:02 PM UTC 24 Oct 09 07:44:20 PM UTC 24 10058285600 ps
T460 /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default/3.flash_ctrl_ro_derr.3432407752 Oct 09 07:41:23 PM UTC 24 Oct 09 07:44:36 PM UTC 24 620318200 ps
T74 /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default/4.flash_ctrl_fetch_code.1965970052 Oct 09 07:43:46 PM UTC 24 Oct 09 07:44:38 PM UTC 24 382499500 ps
T154 /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default/2.flash_ctrl_rand_ops.1892707115 Oct 09 07:32:16 PM UTC 24 Oct 09 07:44:41 PM UTC 24 149678600 ps
T461 /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default/3.flash_ctrl_oversize_error.135887788 Oct 09 07:41:37 PM UTC 24 Oct 09 07:45:01 PM UTC 24 3799050600 ps
T249 /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default/3.flash_ctrl_rw_derr.3536448619 Oct 09 07:41:32 PM UTC 24 Oct 09 07:45:11 PM UTC 24 6083460800 ps
T381 /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default/4.flash_ctrl_smoke.2808989378 Oct 09 07:43:04 PM UTC 24 Oct 09 07:45:20 PM UTC 24 29330200 ps
T380 /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default/1.flash_ctrl_stress_all.2240053321 Oct 09 07:29:10 PM UTC 24 Oct 09 07:45:24 PM UTC 24 307898000 ps
T155 /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default/4.flash_ctrl_invalid_op.1698263433 Oct 09 07:44:17 PM UTC 24 Oct 09 07:45:36 PM UTC 24 6213740600 ps
T327 /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default/3.flash_ctrl_intr_rd_slow_flash.4220352719 Oct 09 07:41:49 PM UTC 24 Oct 09 07:45:38 PM UTC 24 44945208600 ps
T462 /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default/2.flash_ctrl_intr_wr_slow_flash.676822517 Oct 09 07:37:18 PM UTC 24 Oct 09 07:45:43 PM UTC 24 263715277800 ps
T463 /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default/4.flash_ctrl_read_word_sweep_serr.1623287992 Oct 09 07:45:02 PM UTC 24 Oct 09 07:45:43 PM UTC 24 85249100 ps
T220 /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default/4.flash_ctrl_rd_buff_evict.3520790849 Oct 09 07:43:27 PM UTC 24 Oct 09 07:45:56 PM UTC 24 1459491600 ps
T253 /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default/3.flash_ctrl_derr_detect.842782899 Oct 09 07:41:34 PM UTC 24 Oct 09 07:46:07 PM UTC 24 1229658500 ps
T464 /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default/4.flash_ctrl_read_word_sweep_derr.1634644600 Oct 09 07:45:37 PM UTC 24 Oct 09 07:46:23 PM UTC 24 18744900 ps
T91 /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default/4.flash_ctrl_otp_reset.1521883169 Oct 09 07:43:32 PM UTC 24 Oct 09 07:46:29 PM UTC 24 68973600 ps
T79 /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default/4.flash_ctrl_mid_op_rst.3191096683 Oct 09 07:44:21 PM UTC 24 Oct 09 07:46:33 PM UTC 24 5039948100 ps
T465 /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default/2.flash_ctrl_rw.4041126322 Oct 09 07:36:35 PM UTC 24 Oct 09 07:46:33 PM UTC 24 20082139800 ps
T83 /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default/3.flash_ctrl_mp_regions.1121033863 Oct 09 07:39:51 PM UTC 24 Oct 09 07:46:54 PM UTC 24 47045194300 ps
T466 /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default/4.flash_ctrl_prog_reset.3987670750 Oct 09 07:46:35 PM UTC 24 Oct 09 07:46:59 PM UTC 24 159414600 ps
T467 /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default/4.flash_ctrl_serr_address.443822101 Oct 09 07:45:24 PM UTC 24 Oct 09 07:47:19 PM UTC 24 1604920800 ps
T468 /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default/4.flash_ctrl_serr_counter.915076920 Oct 09 07:45:21 PM UTC 24 Oct 09 07:47:34 PM UTC 24 1602895100 ps
T221 /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default/3.flash_ctrl_erase_suspend.936997732 Oct 09 07:39:45 PM UTC 24 Oct 09 07:47:35 PM UTC 24 2843869600 ps
T469 /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default/4.flash_ctrl_intr_wr.3497921423 Oct 09 07:46:24 PM UTC 24 Oct 09 07:47:40 PM UTC 24 6824286200 ps
T470 /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default/4.flash_ctrl_hw_sec_otp.1060426866 Oct 09 07:43:28 PM UTC 24 Oct 09 07:47:41 PM UTC 24 25188972700 ps
T471 /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default/4.flash_ctrl_ro_serr.1512321557 Oct 09 07:45:12 PM UTC 24 Oct 09 07:47:41 PM UTC 24 1617722700 ps
T472 /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default/2.flash_ctrl_integrity.1289092651 Oct 09 07:36:56 PM UTC 24 Oct 09 07:47:47 PM UTC 24 7332037700 ps
T473 /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default/3.flash_ctrl_intr_wr_slow_flash.1532802004 Oct 09 07:41:50 PM UTC 24 Oct 09 07:47:48 PM UTC 24 93549796100 ps
T399 /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default/4.flash_ctrl_rw_evict.4046669422 Oct 09 07:46:55 PM UTC 24 Oct 09 07:47:49 PM UTC 24 112127000 ps
T474 /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default/4.flash_ctrl_rw_evict_all_en.797158430 Oct 09 07:47:00 PM UTC 24 Oct 09 07:47:53 PM UTC 24 92524100 ps
T475 /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default/4.flash_ctrl_phy_host_grant_err.481768419 Oct 09 07:47:49 PM UTC 24 Oct 09 07:48:07 PM UTC 24 26213400 ps
T102 /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default/4.flash_ctrl_connect.2609836934 Oct 09 07:47:42 PM UTC 24 Oct 09 07:48:10 PM UTC 24 28342000 ps
T476 /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default/4.flash_ctrl_ro_derr.1444172922 Oct 09 07:45:38 PM UTC 24 Oct 09 07:48:12 PM UTC 24 4841124900 ps
T420 /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default/4.flash_ctrl_re_evict.4133571024 Oct 09 07:47:20 PM UTC 24 Oct 09 07:48:19 PM UTC 24 263934400 ps
T96 /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default/4.flash_ctrl_phy_arb_redun.4080256851 Oct 09 07:47:49 PM UTC 24 Oct 09 07:48:20 PM UTC 24 906937300 ps
T100 /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default/4.flash_ctrl_disable.2490817832 Oct 09 07:47:35 PM UTC 24 Oct 09 07:48:21 PM UTC 24 10707700 ps
T101 /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default/4.flash_ctrl_phy_ack_consistency.3088385411 Oct 09 07:47:54 PM UTC 24 Oct 09 07:48:21 PM UTC 24 32092400 ps
T43 /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default/4.flash_ctrl_intr_rd.258916458 Oct 09 07:46:07 PM UTC 24 Oct 09 07:48:26 PM UTC 24 1551024400 ps
T264 /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default/4.flash_ctrl_hw_read_seed_err.2822490423 Oct 09 07:48:13 PM UTC 24 Oct 09 07:48:29 PM UTC 24 44615700 ps
T477 /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default/4.flash_ctrl_config_regwen.2348950655 Oct 09 07:48:08 PM UTC 24 Oct 09 07:48:33 PM UTC 24 35903900 ps
T270 /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default/4.flash_ctrl_lcmgr_intg.612016155 Oct 09 07:48:11 PM UTC 24 Oct 09 07:48:34 PM UTC 24 29550100 ps
T478 /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default/4.flash_ctrl_oversize_error.2816576369 Oct 09 07:45:53 PM UTC 24 Oct 09 07:48:35 PM UTC 24 15921008300 ps
T479 /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default/4.flash_ctrl_alert_test.2688037956 Oct 09 07:48:21 PM UTC 24 Oct 09 07:48:47 PM UTC 24 51084200 ps
T415 /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default/4.flash_ctrl_fs_sup.197079716 Oct 09 07:47:48 PM UTC 24 Oct 09 07:48:50 PM UTC 24 326332900 ps
T372 /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default/4.flash_ctrl_sec_info_access.452378731 Oct 09 07:47:41 PM UTC 24 Oct 09 07:48:57 PM UTC 24 8213393500 ps
T480 /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default/4.flash_ctrl_wo.1944717645 Oct 09 07:44:37 PM UTC 24 Oct 09 07:49:05 PM UTC 24 11047783800 ps
T481 /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default/4.flash_ctrl_derr_detect.2930166626 Oct 09 07:45:45 PM UTC 24 Oct 09 07:49:24 PM UTC 24 3052283300 ps
T416 /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default/3.flash_ctrl_rw.38478469 Oct 09 07:40:49 PM UTC 24 Oct 09 07:49:33 PM UTC 24 3952252100 ps
T64 /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default/5.flash_ctrl_fetch_code.298645546 Oct 09 07:48:48 PM UTC 24 Oct 09 07:49:34 PM UTC 24 824569600 ps
T197 /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default/4.flash_ctrl_rw_derr.2865216850 Oct 09 07:45:45 PM UTC 24 Oct 09 07:49:37 PM UTC 24 6368559200 ps
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