Unified Coverage Report :: Group :: cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=5}

Group : cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=5}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
88.24	1	100	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

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Summary for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=5}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	10	0	10	100.00
Crosses	24	4	20	83.33

Variables for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=5}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	6	0	6	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=5}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_cg_cc	24	4	20	83.33	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	6	0	6	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	274978	1		T1	1		T2	2		T3	2
all_values[1]	274978	1		T1	1		T2	2		T3	2
all_values[2]	274978	1		T1	1		T2	2		T3	2
all_values[3]	274978	1		T1	1		T2	2		T3	2
all_values[4]	274978	1		T1	1		T2	2		T3	2
all_values[5]	274978	1		T1	1		T2	2		T3	2

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Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	556333	1		T1	6		T2	12		T3	12
auto[1]	1093535	1		T33	6700		T45	12896		T38	5396

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Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	806375	1		T1	4		T2	7		T3	7
auto[1]	843493	1		T1	2		T2	5		T3	5

---

Summary for Cross intr_cg_cc

Samples crossed: cp_intr cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	24	4	20	83.33	4

Automatically Generated Cross Bins for intr_cg_cc

Element holes

cp_intr	cp_intr_en	cp_intr_state	COUNT	AT LEAST	NUMBER
[all_values[0] , all_values[1]]	*	[auto[0]]	--	--	4

Covered bins

cp_intr	cp_intr_en	cp_intr_state	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[1]	274812	1		T1	1		T2	2		T3	2
all_values[0]	auto[1]	auto[1]	166	1		T225	5		T316	4		T317	1
all_values[1]	auto[0]	auto[1]	274848	1		T1	1		T2	2		T3	2
all_values[1]	auto[1]	auto[1]	130	1		T225	3		T235	1		T316	2
all_values[2]	auto[0]	auto[0]	1620	1		T1	1		T2	2		T3	2
all_values[2]	auto[0]	auto[1]	56	1		T225	2		T235	1		T316	2
all_values[2]	auto[1]	auto[0]	273247	1		T33	1675		T45	3224		T38	1349
all_values[2]	auto[1]	auto[1]	55	1		T225	1		T235	1		T316	2
all_values[3]	auto[0]	auto[0]	1631	1		T1	1		T2	2		T3	2
all_values[3]	auto[0]	auto[1]	40	1		T225	1		T318	3		T335	2
all_values[3]	auto[1]	auto[0]	83585	1		T33	1675		T45	1612		T38	1349
all_values[3]	auto[1]	auto[1]	189722	1		T45	1612		T46	5067		T47	6692
all_values[4]	auto[0]	auto[0]	1142	1		T1	1		T2	1		T3	1
all_values[4]	auto[0]	auto[1]	525	1		T2	1		T3	1		T17	1
all_values[4]	auto[1]	auto[0]	170313	1		T33	1		T45	1612		T38	1
all_values[4]	auto[1]	auto[1]	102998	1		T33	1674		T45	1612		T38	1348
all_values[5]	auto[0]	auto[0]	1578	1		T1	1		T2	2		T3	2
all_values[5]	auto[0]	auto[1]	81	1		T48	1		T49	1		T50	1
all_values[5]	auto[1]	auto[0]	273259	1		T33	1675		T45	3224		T38	1349
all_values[5]	auto[1]	auto[1]	60	1		T316	2		T317	2		T319	1