Unified Coverage Report :: Group :: flash_ctrl_env_pkg::flash_ctrl_env_cov::control_cg

Group : flash_ctrl_env_pkg::flash_ctrl_env_cov::control_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/default/sim-vcs/../src/lowrisc_dv_flash_ctrl_env_0.1/flash_ctrl_env_cov.sv

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Summary for Group flash_ctrl_env_pkg::flash_ctrl_env_cov::control_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	15	0	15	100.00
Crosses	16	0	16	100.00

Variables for Group flash_ctrl_env_pkg::flash_ctrl_env_cov::control_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
erase_cp	2	0	2	100.00	100	1	1	0
op_cp	4	0	4	100.00	100	1	1	0
op_evict_cp	5	0	5	100.00	100	1	1	0
part_cp	4	0	4	100.00	100	1	1	0

Crosses for Group flash_ctrl_env_pkg::flash_ctrl_env_cov::control_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
op_part_cross	16	0	16	100.00	100	1	1	0

Summary for Variable erase_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for erase_cp

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[FlashErasePage]	229681	1		T2	4		T3	2		T9	368
auto[FlashEraseBank]	268591	1		T12	7		T18	2		T10	13

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Summary for Variable op_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for op_cp

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[FlashOpRead]	247284	1		T2	2		T3	1		T9	188
auto[FlashOpProgram]	233531	1		T2	1		T3	1		T9	90
auto[FlashOpErase]	13457	1		T2	1		T9	90		T18	4
auto[FlashOpInvalid]	4000	1		T32	200		T89	200		T145	200

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Summary for Variable op_evict_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	5	0	5	100.00

User Defined Bins for op_evict_cp

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
op[FlashOpRead]	247284	1		T2	2		T3	1		T9	188
op[FlashOpProgram]	233531	1		T2	1		T3	1		T9	90
op[FlashOpErase]	13457	1		T2	1		T9	90		T18	4
read_erase_read	552	1		T18	2		T29	6		T37	15
read_prog_read	801	1		T18	1		T48	1		T70	3

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Summary for Variable part_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for part_cp

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[FlashPartData]	361057	1		T2	4		T3	2		T17	2
auto[FlashPartInfo]	129024	1		T9	368		T10	13		T32	138
auto[FlashPartInfo1]	2279	1		T32	56		T48	1		T49	2
auto[FlashPartInfo2]	5912	1		T32	102		T71	4		T13	3

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Summary for Cross op_part_cross

Samples crossed: part_cp op_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for op_part_cross

Bins

part_cp	op_cp	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[FlashPartData]	auto[FlashOpRead]	180478	1		T2	2		T3	1		T17	2
auto[FlashPartData]	auto[FlashOpProgram]	176029	1		T2	1		T3	1		T18	4
auto[FlashPartData]	auto[FlashOpErase]	2622	1		T2	1		T18	4		T32	46
auto[FlashPartData]	auto[FlashOpInvalid]	1928	1		T32	92		T89	104		T145	104
auto[FlashPartInfo]	auto[FlashOpRead]	62415	1		T9	188		T32	46		T13	179
auto[FlashPartInfo]	auto[FlashOpProgram]	55480	1		T9	90		T10	13		T32	23
auto[FlashPartInfo]	auto[FlashOpErase]	10445	1		T9	90		T32	23		T29	18
auto[FlashPartInfo]	auto[FlashOpInvalid]	684	1		T32	46		T89	34		T145	26
auto[FlashPartInfo1]	auto[FlashOpRead]	1414	1		T32	28		T48	1		T49	2
auto[FlashPartInfo1]	auto[FlashOpProgram]	160	1		T149	32		T140	32		T151	32
auto[FlashPartInfo1]	auto[FlashOpErase]	1	1		T396	1		-	-		-	-
auto[FlashPartInfo1]	auto[FlashOpInvalid]	704	1		T32	28		T89	34		T145	32
auto[FlashPartInfo2]	auto[FlashOpRead]	2977	1		T32	34		T13	3		T48	1
auto[FlashPartInfo2]	auto[FlashOpProgram]	1862	1		T32	17		T71	4		T70	2
auto[FlashPartInfo2]	auto[FlashOpErase]	389	1		T32	17		T37	2		T89	14
auto[FlashPartInfo2]	auto[FlashOpInvalid]	684	1		T32	34		T89	28		T145	38