Unified Coverage Report :: Group :: flash_ctrl_env_pkg::flash_ctrl_env_cov::eviction_cg

Group : flash_ctrl_env_pkg::flash_ctrl_env_cov::eviction_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/default/sim-vcs/../src/lowrisc_dv_flash_ctrl_env_0.1/flash_ctrl_env_cov.sv

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Summary for Group flash_ctrl_env_pkg::flash_ctrl_env_cov::eviction_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	10	0	10	100.00
Crosses	32	0	32	100.00

Variables for Group flash_ctrl_env_pkg::flash_ctrl_env_cov::eviction_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
evic_cfg_cp	4	0	4	100.00	100	1	1	4
evic_idx_cp	4	0	4	100.00	100	1	1	0
evic_op_cp	2	0	2	100.00	100	1	1	0

Crosses for Group flash_ctrl_env_pkg::flash_ctrl_env_cov::eviction_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
evic_all_cross	32	0	32	100.00	100	1	1	0

Summary for Variable evic_cfg_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for evic_cfg_cp

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	25579	1		T2	4		T3	4		T9	172
auto[1]	27	1		T397	2		T398	1		T399	1
auto[2]	56	1		T31	8		T400	1		T218	4
auto[3]	277	1		T37	8		T36	1		T51	1

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Summary for Variable evic_idx_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for evic_idx_cp

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
evic_idx[0]	6492	1		T2	1		T3	1		T9	43
evic_idx[1]	6491	1		T2	1		T3	1		T9	43
evic_idx[2]	6479	1		T2	1		T3	1		T9	43
evic_idx[3]	6477	1		T2	1		T3	1		T9	43

---

Summary for Variable evic_op_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for evic_op_cp

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
evic_op[1]	24986	1		T2	4		T9	172		T18	16
evic_op[2]	309	1		T3	4		T18	16		T54	1

---

Summary for Cross evic_all_cross

Samples crossed: evic_idx_cp evic_op_cp evic_cfg_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	32	0	32	100.00

Automatically Generated Cross Bins for evic_all_cross

Bins

evic_idx_cp	evic_op_cp	evic_cfg_cp	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
evic_idx[0]	evic_op[1]	auto[0]	6183	1		T2	1		T9	43		T18	4
evic_idx[0]	evic_op[1]	auto[1]	3	1		T401	3		-	-		-	-
evic_idx[0]	evic_op[1]	auto[2]	5	1		T247	1		T401	1		T402	1
evic_idx[0]	evic_op[1]	auto[3]	64	1		T37	3		T146	8		T403	7
evic_idx[0]	evic_op[2]	auto[0]	56	1		T3	1		T18	4		T40	1
evic_idx[0]	evic_op[2]	auto[1]	4	1		T397	1		T399	1		T404	1
evic_idx[0]	evic_op[2]	auto[2]	3	1		T405	1		T406	2		-	-
evic_idx[0]	evic_op[2]	auto[3]	11	1		T289	1		T407	1		T408	1
evic_idx[1]	evic_op[1]	auto[0]	6184	1		T2	1		T9	43		T18	4
evic_idx[1]	evic_op[1]	auto[1]	2	1		T401	2		-	-		-	-
evic_idx[1]	evic_op[1]	auto[2]	4	1		T247	2		T401	1		T402	1
evic_idx[1]	evic_op[1]	auto[3]	64	1		T37	2		T146	8		T403	4
evic_idx[1]	evic_op[2]	auto[0]	54	1		T3	1		T18	4		T40	1
evic_idx[1]	evic_op[2]	auto[1]	5	1		T398	1		T409	1		T410	1
evic_idx[1]	evic_op[2]	auto[2]	2	1		T411	1		T412	1		-	-
evic_idx[1]	evic_op[2]	auto[3]	15	1		T51	1		T413	1		T414	1
evic_idx[2]	evic_op[1]	auto[0]	6182	1		T2	1		T9	43		T18	4
evic_idx[2]	evic_op[1]	auto[1]	2	1		T401	2		-	-		-	-
evic_idx[2]	evic_op[1]	auto[2]	6	1		T247	3		T401	1		T402	1
evic_idx[2]	evic_op[1]	auto[3]	49	1		T37	2		T250	1		T146	5
evic_idx[2]	evic_op[2]	auto[0]	57	1		T3	1		T18	4		T34	1
evic_idx[2]	evic_op[2]	auto[1]	6	1		T415	1		T416	1		T417	1
evic_idx[2]	evic_op[2]	auto[2]	4	1		T400	1		T405	1		T406	2
evic_idx[2]	evic_op[2]	auto[3]	12	1		T36	1		T418	1		T419	1
evic_idx[3]	evic_op[1]	auto[0]	6185	1		T2	1		T9	43		T18	4
evic_idx[3]	evic_op[1]	auto[1]	1	1		T401	1		-	-		-	-
evic_idx[3]	evic_op[1]	auto[2]	5	1		T420	1		T247	2		T201	2
evic_idx[3]	evic_op[1]	auto[3]	47	1		T37	1		T250	1		T146	6
evic_idx[3]	evic_op[2]	auto[0]	58	1		T3	1		T18	4		T54	1
evic_idx[3]	evic_op[2]	auto[1]	4	1		T397	1		T415	1		T421	1
evic_idx[3]	evic_op[2]	auto[2]	3	1		T406	2		T411	1		-	-
evic_idx[3]	evic_op[2]	auto[3]	15	1		T422	1		T406	1		T423	1