Unified Coverage Report :: Group :: flash_ctrl_env_pkg::flash_ctrl_env_cov::msgfifo_level_cg

Group : flash_ctrl_env_pkg::flash_ctrl_env_cov::msgfifo_level_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
83.33	1	100	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/default/sim-vcs/../src/lowrisc_dv_flash_ctrl_env_0.1/flash_ctrl_env_cov.sv

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Summary for Group flash_ctrl_env_pkg::flash_ctrl_env_cov::msgfifo_level_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	18	3	15	83.33

Variables for Group flash_ctrl_env_pkg::flash_ctrl_env_cov::msgfifo_level_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
prog_lvl_cp	3	3	0	0.00	100	1	1	0
rd_lvl_cp	15	0	15	100.00	100	1	1	0

Summary for Variable prog_lvl_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	3	0	0.00

User Defined Bins for prog_lvl_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER
prog_lvl[1]	0	1	1
prog_lvl[2]	0	1	1
prog_lvl[3]	0	1	1

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Summary for Variable rd_lvl_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	15	0	15	100.00

User Defined Bins for rd_lvl_cp

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
rd_lvl[1]	4744	1		T323	2650		T324	2094		-	-
rd_lvl[2]	33120	1		T307	6900		T325	1227		T323	2330
rd_lvl[3]	17719	1		T203	911		T307	220		T326	4165
rd_lvl[4]	37278	1		T47	5502		T203	503		T307	2
rd_lvl[5]	16240	1		T46	2468		T47	956		T203	47
rd_lvl[6]	13457	1		T46	2599		T47	14		T203	26
rd_lvl[7]	5221	1		T47	78		T203	31		T327	1004
rd_lvl[8]	11995	1		T47	89		T203	9		T327	554
rd_lvl[9]	5921	1		T80	556		T42	197		T328	438
rd_lvl[10]	10137	1		T45	1365		T80	1192		T42	82
rd_lvl[11]	3448	1		T45	247		T329	4		T330	173
rd_lvl[12]	5559	1		T42	64		T307	2		T331	246
rd_lvl[13]	1270	1		T332	15		T331	1		T325	170
rd_lvl[14]	8071	1		T44	1177		T331	55		T333	1439
rd_lvl[15]	4816	1		T43	273		T44	496		T334	235