Unified Coverage Report :: Group :: cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=5}

Group : cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=5}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=5}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	10	0	10	100.00
Crosses	24	0	24	100.00

Variables for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=5}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr_pin	6	0	6	100.00	100	1	1	0
cp_intr_pin_value	4	0	4	100.00	100	1	1	0

Crosses for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=5}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_intr_pins_all_values	24	0	24	100.00	100	1	1	0

Summary for Variable cp_intr_pin

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	6	0	6	100.00

User Defined Bins for cp_intr_pin

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	274978	1		T1	1		T2	2		T3	2
all_pins[1]	274978	1		T1	1		T2	2		T3	2
all_pins[2]	274978	1		T1	1		T2	2		T3	2
all_pins[3]	274978	1		T1	1		T2	2		T3	2
all_pins[4]	274978	1		T1	1		T2	2		T3	2
all_pins[5]	274978	1		T1	1		T2	2		T3	2

---

Summary for Variable cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for cp_intr_pin_value

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x0]	1351542	1		T1	6		T2	12		T3	12
values[0x1]	298326	1		T33	1674		T45	3224		T38	1348
transitions[0x0=>0x1]	266855	1		T33	1674		T45	3224		T38	1348
transitions[0x1=>0x0]	266835	1		T33	1674		T45	3224		T38	1348

---

Summary for Cross cp_intr_pins_all_values

Samples crossed: cp_intr_pin cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	24	0	24	100.00

Automatically Generated Cross Bins for cp_intr_pins_all_values

Bins

cp_intr_pin	cp_intr_pin_value	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	values[0x0]	274812	1		T1	1		T2	2		T3	2
all_pins[0]	values[0x1]	166	1		T225	5		T316	4		T317	1
all_pins[0]	transitions[0x0=>0x1]	94	1		T225	3		T316	2		T317	1
all_pins[0]	transitions[0x1=>0x0]	58	1		T225	1		T235	1		T317	1
all_pins[1]	values[0x0]	274848	1		T1	1		T2	2		T3	2
all_pins[1]	values[0x1]	130	1		T225	3		T235	1		T316	2
all_pins[1]	transitions[0x0=>0x1]	102	1		T225	2		T235	1		T316	1
all_pins[1]	transitions[0x1=>0x0]	3782	1		T43	271		T334	326		T336	251
all_pins[2]	values[0x0]	271168	1		T1	1		T2	2		T3	2
all_pins[2]	values[0x1]	3810	1		T43	271		T334	326		T336	251
all_pins[2]	transitions[0x0=>0x1]	39	1		T235	1		T316	1		T317	1
all_pins[2]	transitions[0x1=>0x0]	179063	1		T45	1612		T46	5067		T47	6639
all_pins[3]	values[0x0]	92144	1		T1	1		T2	2		T3	2
all_pins[3]	values[0x1]	182834	1		T45	1612		T46	5067		T47	6639
all_pins[3]	transitions[0x0=>0x1]	155287	1		T45	1612		T46	3951		T47	4908
all_pins[3]	transitions[0x1=>0x0]	83779	1		T33	1674		T45	1612		T38	1348
all_pins[4]	values[0x0]	163652	1		T1	1		T2	2		T3	2
all_pins[4]	values[0x1]	111326	1		T33	1674		T45	1612		T38	1348
all_pins[4]	transitions[0x0=>0x1]	111308	1		T33	1674		T45	1612		T38	1348
all_pins[4]	transitions[0x1=>0x0]	42	1		T316	1		T317	2		T320	3
all_pins[5]	values[0x0]	274918	1		T1	1		T2	2		T3	2
all_pins[5]	values[0x1]	60	1		T316	2		T317	2		T319	1
all_pins[5]	transitions[0x0=>0x1]	25	1		T317	1		T319	1		T320	3
all_pins[5]	transitions[0x1=>0x0]	111	1		T225	4		T316	2		T318	2