Unified Coverage Report :: Group :: cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=5}

Group : cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=5}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
83.33	1	100	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=5}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	12	0	12	100.00
Crosses	36	8	28	77.78

Variables for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=5}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	6	0	6	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2
cp_intr_test	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=5}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_test_cg_cc	36	8	28	77.78	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	6	0	6	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	269	1		T225	7		T235	4		T316	7
all_values[1]	269	1		T225	7		T235	4		T316	7
all_values[2]	269	1		T225	7		T235	4		T316	7
all_values[3]	269	1		T225	7		T235	4		T316	7
all_values[4]	269	1		T225	7		T235	4		T316	7
all_values[5]	269	1		T225	7		T235	4		T316	7

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	864	1		T225	24		T235	18		T316	18
auto[1]	750	1		T225	18		T235	6		T316	24

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	570	1		T225	14		T235	10		T316	9
auto[1]	1044	1		T225	28		T235	14		T316	33

---

Summary for Variable cp_intr_test

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_test

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	993	1		T225	25		T235	16		T316	22
auto[1]	621	1		T225	17		T235	8		T316	20

---

Summary for Cross intr_test_cg_cc

Samples crossed: cp_intr cp_intr_test cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	36	8	28	77.78	8
Automatically Generated Cross Bins	36	8	28	77.78	8
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for intr_test_cg_cc

Element holes

cp_intr	cp_intr_test	cp_intr_en	cp_intr_state	COUNT	AT LEAST	NUMBER
[all_values[0] , all_values[1]]	[auto[0]]	*	[auto[0]]	--	--	4
[all_values[2] , all_values[3]]	[auto[0]]	*	[auto[1]]	--	--	4

Covered bins

cp_intr	cp_intr_test	cp_intr_en	cp_intr_state	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	auto[1]	81	1		T225	1		T235	3		T316	3
all_values[0]	auto[0]	auto[1]	auto[1]	77	1		T225	2		T316	3		T317	1
all_values[0]	auto[1]	auto[0]	auto[1]	54	1		T225	2		T235	1		T317	2
all_values[0]	auto[1]	auto[1]	auto[1]	57	1		T225	2		T316	1		T318	1
all_values[1]	auto[0]	auto[0]	auto[1]	99	1		T225	3		T235	1		T316	2
all_values[1]	auto[0]	auto[1]	auto[1]	58	1		T225	2		T316	1		T317	1
all_values[1]	auto[1]	auto[0]	auto[1]	71	1		T225	1		T235	2		T316	2
all_values[1]	auto[1]	auto[1]	auto[1]	41	1		T225	1		T235	1		T316	2
all_values[2]	auto[0]	auto[0]	auto[0]	80	1		T225	1		T235	2		T316	1
all_values[2]	auto[0]	auto[1]	auto[0]	78	1		T225	3		T316	2		T319	3
all_values[2]	auto[1]	auto[0]	auto[1]	63	1		T225	3		T235	1		T316	3
all_values[2]	auto[1]	auto[1]	auto[1]	48	1		T235	1		T316	1		T317	1
all_values[3]	auto[0]	auto[0]	auto[0]	90	1		T225	3		T235	4		T316	1
all_values[3]	auto[0]	auto[1]	auto[0]	82	1		T225	1		T316	2		T319	3
all_values[3]	auto[1]	auto[0]	auto[1]	49	1		T225	2		T316	1		T318	3
all_values[3]	auto[1]	auto[1]	auto[1]	48	1		T225	1		T316	3		T320	2
all_values[4]	auto[0]	auto[0]	auto[0]	65	1		T225	1		T317	1		T318	1
all_values[4]	auto[0]	auto[0]	auto[1]	28	1		T235	2		T316	1		T317	2
all_values[4]	auto[0]	auto[1]	auto[0]	49	1		T225	2		T321	1		T322	1
all_values[4]	auto[0]	auto[1]	auto[1]	30	1		T225	1		T316	3		T318	1
all_values[4]	auto[1]	auto[0]	auto[1]	49	1		T225	1		T235	2		T316	3
all_values[4]	auto[1]	auto[1]	auto[1]	48	1		T225	2		T317	1		T319	1
all_values[5]	auto[0]	auto[0]	auto[0]	68	1		T225	2		T316	1		T318	1
all_values[5]	auto[0]	auto[0]	auto[1]	22	1		T225	2		T318	2		T321	1
all_values[5]	auto[0]	auto[1]	auto[0]	58	1		T225	1		T235	4		T316	2
all_values[5]	auto[0]	auto[1]	auto[1]	28	1		T317	1		T319	1		T320	1
all_values[5]	auto[1]	auto[0]	auto[1]	45	1		T225	2		T317	1		T318	1
all_values[5]	auto[1]	auto[1]	auto[1]	48	1		T316	4		T317	1		T319	3

User Defined Cross Bins for intr_test_cg_cc

Excluded/Illegal bins

NAME	COUNT	STATUS
test_1_state_0	0	Illegal