|  |  |  |  |  |  |  |     
    
| gen_flash_cores[0].u_core | 
 97.56 | 
 96.96 | 
 93.32 | 
100.00 | 
100.00 | 
 97.88 | 
 97.17 | 
    
    
| gen_prog_data.u_prog | 
 98.65 | 
100.00 | 
 95.38 | 
100.00 | 
100.00 | 
 96.49 | 
100.00 | 
    
    
| u_data_intg_chk | 
100.00 | 
100.00 | 
 | 
100.00 | 
 | 
 | 
 | 
    
    
| u_data_chk | 
100.00 | 
 | 
 | 
100.00 | 
 | 
 | 
 | 
    
    
| u_enc | 
100.00 | 
100.00 | 
 | 
 | 
 | 
 | 
 | 
    
    
| u_plain_enc | 
100.00 | 
100.00 | 
 | 
 | 
 | 
 | 
 | 
    
    
| u_state_regs | 
100.00 | 
100.00 | 
 | 
 | 
 | 
100.00 | 
100.00 | 
    
    
| u_state_flop | 
100.00 | 
100.00 | 
 | 
 | 
 | 
100.00 | 
 | 
    
    
| gen_generic.u_impl_generic | 
100.00 | 
100.00 | 
 | 
 | 
 | 
100.00 | 
 | 
    
    
| u_disable_buf | 
100.00 | 
100.00 | 
 | 
 | 
 | 
 | 
100.00 | 
    
    
| gen_buffs[0].gen_bits[0].u_prim_buf | 
100.00 | 
100.00 | 
 | 
 | 
 | 
 | 
 | 
    
    
| gen_generic.u_impl_generic | 
100.00 | 
100.00 | 
 | 
 | 
 | 
 | 
 | 
    
    
| gen_buffs[0].gen_bits[1].u_prim_buf | 
100.00 | 
100.00 | 
 | 
 | 
 | 
 | 
 | 
    
    
| gen_generic.u_impl_generic | 
100.00 | 
100.00 | 
 | 
 | 
 | 
 | 
 | 
    
    
| gen_buffs[0].gen_bits[2].u_prim_buf | 
100.00 | 
100.00 | 
 | 
 | 
 | 
 | 
 | 
    
    
| gen_generic.u_impl_generic | 
100.00 | 
100.00 | 
 | 
 | 
 | 
 | 
 | 
    
    
| gen_buffs[0].gen_bits[3].u_prim_buf | 
100.00 | 
100.00 | 
 | 
 | 
 | 
 | 
 | 
    
    
| gen_generic.u_impl_generic | 
100.00 | 
100.00 | 
 | 
 | 
 | 
 | 
 | 
    
    
| gen_buffs[1].gen_bits[0].u_prim_buf | 
100.00 | 
100.00 | 
 | 
 | 
 | 
 | 
 | 
    
    
| gen_generic.u_impl_generic | 
100.00 | 
100.00 | 
 | 
 | 
 | 
 | 
 | 
    
    
| gen_buffs[1].gen_bits[1].u_prim_buf | 
100.00 | 
100.00 | 
 | 
 | 
 | 
 | 
 | 
    
    
| gen_generic.u_impl_generic | 
100.00 | 
100.00 | 
 | 
 | 
 | 
 | 
 | 
    
    
| gen_buffs[1].gen_bits[2].u_prim_buf | 
100.00 | 
100.00 | 
 | 
 | 
 | 
 | 
 | 
    
    
| gen_generic.u_impl_generic | 
100.00 | 
100.00 | 
 | 
 | 
 | 
 | 
 | 
    
    
| gen_buffs[1].gen_bits[3].u_prim_buf | 
100.00 | 
100.00 | 
 | 
 | 
 | 
 | 
 | 
    
    
| gen_generic.u_impl_generic | 
100.00 | 
100.00 | 
 | 
 | 
 | 
 | 
 | 
    
    
| gen_buffs[2].gen_bits[0].u_prim_buf | 
100.00 | 
100.00 | 
 | 
 | 
 | 
 | 
 | 
    
    
| gen_generic.u_impl_generic | 
100.00 | 
100.00 | 
 | 
 | 
 | 
 | 
 | 
    
    
| gen_buffs[2].gen_bits[1].u_prim_buf | 
100.00 | 
100.00 | 
 | 
 | 
 | 
 | 
 | 
    
    
| gen_generic.u_impl_generic | 
100.00 | 
100.00 | 
 | 
 | 
 | 
 | 
 | 
    
    
| gen_buffs[2].gen_bits[2].u_prim_buf | 
100.00 | 
100.00 | 
 | 
 | 
 | 
 | 
 | 
    
    
| gen_generic.u_impl_generic | 
100.00 | 
100.00 | 
 | 
 | 
 | 
 | 
 | 
    
    
| gen_buffs[2].gen_bits[3].u_prim_buf | 
100.00 | 
100.00 | 
 | 
 | 
 | 
 | 
 | 
    
    
| gen_generic.u_impl_generic | 
100.00 | 
100.00 | 
 | 
 | 
 | 
 | 
 | 
    
    
| gen_buffs[3].gen_bits[0].u_prim_buf | 
100.00 | 
100.00 | 
 | 
 | 
 | 
 | 
 | 
    
    
| gen_generic.u_impl_generic | 
100.00 | 
100.00 | 
 | 
 | 
 | 
 | 
 | 
    
    
| gen_buffs[3].gen_bits[1].u_prim_buf | 
100.00 | 
100.00 | 
 | 
 | 
 | 
 | 
 | 
    
    
| gen_generic.u_impl_generic | 
100.00 | 
100.00 | 
 | 
 | 
 | 
 | 
 | 
    
    
| gen_buffs[3].gen_bits[2].u_prim_buf | 
100.00 | 
100.00 | 
 | 
 | 
 | 
 | 
 | 
    
    
| gen_generic.u_impl_generic | 
100.00 | 
100.00 | 
 | 
 | 
 | 
 | 
 | 
    
    
| gen_buffs[3].gen_bits[3].u_prim_buf | 
100.00 | 
100.00 | 
 | 
 | 
 | 
 | 
 | 
    
    
| gen_generic.u_impl_generic | 
100.00 | 
100.00 | 
 | 
 | 
 | 
 | 
 | 
    
    
| u_erase | 
 92.22 | 
100.00 | 
 88.89 | 
 | 
100.00 | 
 80.00 | 
 | 
    
    
| u_host_arb | 
 91.95 | 
 75.93 | 
 91.89 | 
 | 
 | 
100.00 | 
100.00 | 
    
    
| gen_input_bufs[0].gen_data_bufs[0].u_dat_buf | 
  0.00 | 
  0.00 | 
 | 
 | 
 | 
 | 
 | 
    
    
| gen_generic.u_impl_generic | 
  0.00 | 
  0.00 | 
 | 
 | 
 | 
 | 
 | 
    
    
| gen_input_bufs[0].gen_data_bufs[1].u_dat_buf | 
  0.00 | 
  0.00 | 
 | 
 | 
 | 
 | 
 | 
    
    
| gen_generic.u_impl_generic | 
  0.00 | 
  0.00 | 
 | 
 | 
 | 
 | 
 | 
    
    
| gen_input_bufs[0].gen_fixed_arbiter.u_arb | 
 96.88 | 
 87.50 | 
100.00 | 
 | 
 | 
100.00 | 
100.00 | 
    
    
| gen_input_bufs[0].u_req_buf | 
100.00 | 
100.00 | 
 | 
 | 
 | 
 | 
 | 
    
    
| gen_generic.u_impl_generic | 
100.00 | 
100.00 | 
 | 
 | 
 | 
 | 
 | 
    
    
| gen_input_bufs[1].gen_data_bufs[0].u_dat_buf | 
  0.00 | 
  0.00 | 
 | 
 | 
 | 
 | 
 | 
    
    
| gen_generic.u_impl_generic | 
  0.00 | 
  0.00 | 
 | 
 | 
 | 
 | 
 | 
    
    
| gen_input_bufs[1].gen_data_bufs[1].u_dat_buf | 
  0.00 | 
  0.00 | 
 | 
 | 
 | 
 | 
 | 
    
    
| gen_generic.u_impl_generic | 
  0.00 | 
  0.00 | 
 | 
 | 
 | 
 | 
 | 
    
    
| gen_input_bufs[1].gen_fixed_arbiter.u_arb | 
 96.88 | 
 87.50 | 
100.00 | 
 | 
 | 
100.00 | 
100.00 | 
    
    
| gen_input_bufs[1].u_req_buf | 
100.00 | 
100.00 | 
 | 
 | 
 | 
 | 
 | 
    
    
| gen_generic.u_impl_generic | 
100.00 | 
100.00 | 
 | 
 | 
 | 
 | 
 | 
    
    
| u_host_outstanding_cnt | 
100.00 | 
 | 
 | 
100.00 | 
 | 
 | 
 | 
    
    
| u_rd | 
 97.08 | 
 97.64 | 
 93.24 | 
100.00 | 
 | 
 99.37 | 
 95.16 | 
    
    
| gen_bufs[0].u_rd_buf | 
 94.64 | 
100.00 | 
 78.57 | 
 | 
 | 
100.00 | 
100.00 | 
    
    
| gen_bufs[1].u_rd_buf | 
 94.64 | 
100.00 | 
 78.57 | 
 | 
 | 
100.00 | 
100.00 | 
    
    
| gen_bufs[2].u_rd_buf | 
 94.64 | 
100.00 | 
 78.57 | 
 | 
 | 
100.00 | 
100.00 | 
    
    
| gen_bufs[3].u_rd_buf | 
 94.64 | 
100.00 | 
 78.57 | 
 | 
 | 
100.00 | 
100.00 | 
    
    
| gen_rd.gen_bus_words_intg[0].u_bus_intg | 
100.00 | 
100.00 | 
 | 
 | 
 | 
 | 
 | 
    
    
| u_data_gen | 
100.00 | 
100.00 | 
 | 
 | 
 | 
 | 
 | 
    
    
| gen_rd.gen_bus_words_intg[0].u_prim_buf_intg | 
100.00 | 
100.00 | 
 | 
 | 
 | 
 | 
 | 
    
    
| gen_generic.u_impl_generic | 
100.00 | 
100.00 | 
 | 
 | 
 | 
 | 
 | 
    
    
| gen_rd.gen_bus_words_intg[1].u_bus_intg | 
100.00 | 
100.00 | 
 | 
 | 
 | 
 | 
 | 
    
    
| u_data_gen | 
100.00 | 
100.00 | 
 | 
 | 
 | 
 | 
 | 
    
    
| gen_rd.gen_bus_words_intg[1].u_prim_buf_intg | 
100.00 | 
100.00 | 
 | 
 | 
 | 
 | 
 | 
    
    
| gen_generic.u_impl_generic | 
100.00 | 
100.00 | 
 | 
 | 
 | 
 | 
 | 
    
    
| u_addr_xor_storage | 
 96.53 | 
100.00 | 
 86.11 | 
 | 
 | 
100.00 | 
100.00 | 
    
    
| gen_normal_fifo.u_fifo_cnt | 
100.00 | 
100.00 | 
100.00 | 
 | 
 | 
100.00 | 
 | 
    
    
| u_bus_inv_data_intg | 
  0.00 | 
  0.00 | 
 | 
 | 
 | 
 | 
 | 
    
    
| u_data_gen | 
  0.00 | 
  0.00 | 
 | 
 | 
 | 
 | 
 | 
    
    
| u_dec | 
100.00 | 
100.00 | 
100.00 | 
 | 
 | 
 | 
 | 
    
    
| u_intg_buf | 
100.00 | 
100.00 | 
 | 
 | 
 | 
 | 
 | 
    
    
| u_secure_anchor_buf | 
100.00 | 
100.00 | 
 | 
 | 
 | 
 | 
 | 
    
    
| gen_generic.u_impl_generic | 
100.00 | 
100.00 | 
 | 
 | 
 | 
 | 
 | 
    
    
| u_mask_storage | 
 93.75 | 
100.00 | 
 80.56 | 
 | 
 | 
 94.44 | 
100.00 | 
    
    
| gen_normal_fifo.u_fifo_cnt | 
 93.64 | 
100.00 | 
 90.00 | 
 | 
 | 
 90.91 | 
 | 
    
    
| u_plain_enc | 
100.00 | 
100.00 | 
 | 
 | 
 | 
 | 
 | 
    
    
| u_prim_buf_data_xor_out | 
100.00 | 
100.00 | 
 | 
 | 
 | 
 | 
 | 
    
    
| gen_generic.u_impl_generic | 
100.00 | 
100.00 | 
 | 
 | 
 | 
 | 
 | 
    
    
| u_rd_buf_dep | 
 96.59 | 
100.00 | 
 86.36 | 
 | 
 | 
100.00 | 
100.00 | 
    
    
| u_rd_storage | 
 97.44 | 
100.00 | 
 87.18 | 
100.00 | 
 | 
100.00 | 
100.00 | 
    
    
| gen_normal_fifo.u_fifo_cnt | 
100.00 | 
100.00 | 
100.00 | 
100.00 | 
 | 
100.00 | 
 | 
    
    
| gen_secure_ptrs.u_rptr | 
100.00 | 
 | 
 | 
100.00 | 
 | 
 | 
 | 
    
    
| gen_secure_ptrs.u_wptr | 
100.00 | 
 | 
 | 
100.00 | 
 | 
 | 
 | 
    
    
| u_rsp_order_fifo | 
 97.44 | 
100.00 | 
 87.18 | 
100.00 | 
 | 
100.00 | 
100.00 | 
    
    
| gen_normal_fifo.u_fifo_cnt | 
100.00 | 
100.00 | 
100.00 | 
100.00 | 
 | 
100.00 | 
 | 
    
    
| gen_secure_ptrs.u_rptr | 
100.00 | 
 | 
 | 
100.00 | 
 | 
 | 
 | 
    
    
| gen_secure_ptrs.u_wptr | 
100.00 | 
 | 
 | 
100.00 | 
 | 
 | 
 | 
    
    
| u_valid_random | 
 92.50 | 
 92.31 | 
 97.69 | 
 | 
 | 
100.00 | 
 80.00 | 
    
    
| u_state_regs | 
100.00 | 
100.00 | 
 | 
 | 
 | 
100.00 | 
100.00 | 
    
    
| u_state_flop | 
100.00 | 
100.00 | 
 | 
 | 
 | 
100.00 | 
 | 
    
    
| gen_generic.u_impl_generic | 
100.00 | 
100.00 | 
 | 
 | 
 | 
100.00 | 
 | 
    
    
| gen_flash_cores[0].u_host_rsp_fifo | 
 97.45 | 
100.00 | 
 87.23 | 
100.00 | 
 | 
100.00 | 
100.00 | 
    
    
| gen_normal_fifo.u_fifo_cnt | 
 97.83 | 
100.00 | 
 91.30 | 
100.00 | 
 | 
100.00 | 
 | 
    
    
| gen_secure_ptrs.u_rptr | 
100.00 | 
 | 
 | 
100.00 | 
 | 
 | 
 | 
    
    
| gen_secure_ptrs.u_wptr | 
100.00 | 
 | 
 | 
100.00 | 
 | 
 | 
 | 
    
    
| gen_flash_cores[1].u_core | 
 96.72 | 
 96.73 | 
 92.70 | 
 96.90 | 
100.00 | 
 96.82 | 
 97.17 | 
    
    
| gen_prog_data.u_prog | 
 97.56 | 
100.00 | 
 93.85 | 
 95.00 | 
100.00 | 
 96.49 | 
100.00 | 
    
    
| u_data_intg_chk | 
 97.50 | 
100.00 | 
 | 
 95.00 | 
 | 
 | 
 | 
    
    
| u_data_chk | 
 95.00 | 
 | 
 | 
 95.00 | 
 | 
 | 
 | 
    
    
| u_enc | 
100.00 | 
100.00 | 
 | 
 | 
 | 
 | 
 | 
    
    
| u_plain_enc | 
100.00 | 
100.00 | 
 | 
 | 
 | 
 | 
 | 
    
    
| u_state_regs | 
100.00 | 
100.00 | 
 | 
 | 
 | 
100.00 | 
100.00 | 
    
    
| u_state_flop | 
100.00 | 
100.00 | 
 | 
 | 
 | 
100.00 | 
 | 
    
    
| gen_generic.u_impl_generic | 
100.00 | 
100.00 | 
 | 
 | 
 | 
100.00 | 
 | 
    
    
| u_disable_buf | 
100.00 | 
100.00 | 
 | 
 | 
 | 
 | 
100.00 | 
    
    
| gen_buffs[0].gen_bits[0].u_prim_buf | 
100.00 | 
100.00 | 
 | 
 | 
 | 
 | 
 | 
    
    
| gen_generic.u_impl_generic | 
100.00 | 
100.00 | 
 | 
 | 
 | 
 | 
 | 
    
    
| gen_buffs[0].gen_bits[1].u_prim_buf | 
100.00 | 
100.00 | 
 | 
 | 
 | 
 | 
 | 
    
    
| gen_generic.u_impl_generic | 
100.00 | 
100.00 | 
 | 
 | 
 | 
 | 
 | 
    
    
| gen_buffs[0].gen_bits[2].u_prim_buf | 
100.00 | 
100.00 | 
 | 
 | 
 | 
 | 
 | 
    
    
| gen_generic.u_impl_generic | 
100.00 | 
100.00 | 
 | 
 | 
 | 
 | 
 | 
    
    
| gen_buffs[0].gen_bits[3].u_prim_buf | 
100.00 | 
100.00 | 
 | 
 | 
 | 
 | 
 | 
    
    
| gen_generic.u_impl_generic | 
100.00 | 
100.00 | 
 | 
 | 
 | 
 | 
 | 
    
    
| gen_buffs[1].gen_bits[0].u_prim_buf | 
100.00 | 
100.00 | 
 | 
 | 
 | 
 | 
 | 
    
    
| gen_generic.u_impl_generic | 
100.00 | 
100.00 | 
 | 
 | 
 | 
 | 
 | 
    
    
| gen_buffs[1].gen_bits[1].u_prim_buf | 
100.00 | 
100.00 | 
 | 
 | 
 | 
 | 
 | 
    
    
| gen_generic.u_impl_generic | 
100.00 | 
100.00 | 
 | 
 | 
 | 
 | 
 | 
    
    
| gen_buffs[1].gen_bits[2].u_prim_buf | 
100.00 | 
100.00 | 
 | 
 | 
 | 
 | 
 | 
    
    
| gen_generic.u_impl_generic | 
100.00 | 
100.00 | 
 | 
 | 
 | 
 | 
 | 
    
    
| gen_buffs[1].gen_bits[3].u_prim_buf | 
100.00 | 
100.00 | 
 | 
 | 
 | 
 | 
 | 
    
    
| gen_generic.u_impl_generic | 
100.00 | 
100.00 | 
 | 
 | 
 | 
 | 
 | 
    
    
| gen_buffs[2].gen_bits[0].u_prim_buf | 
100.00 | 
100.00 | 
 | 
 | 
 | 
 | 
 | 
    
    
| gen_generic.u_impl_generic | 
100.00 | 
100.00 | 
 | 
 | 
 | 
 | 
 | 
    
    
| gen_buffs[2].gen_bits[1].u_prim_buf | 
100.00 | 
100.00 | 
 | 
 | 
 | 
 | 
 | 
    
    
| gen_generic.u_impl_generic | 
100.00 | 
100.00 | 
 | 
 | 
 | 
 | 
 | 
    
    
| gen_buffs[2].gen_bits[2].u_prim_buf | 
100.00 | 
100.00 | 
 | 
 | 
 | 
 | 
 | 
    
    
| gen_generic.u_impl_generic | 
100.00 | 
100.00 | 
 | 
 | 
 | 
 | 
 | 
    
    
| gen_buffs[2].gen_bits[3].u_prim_buf | 
100.00 | 
100.00 | 
 | 
 | 
 | 
 | 
 | 
    
    
| gen_generic.u_impl_generic | 
100.00 | 
100.00 | 
 | 
 | 
 | 
 | 
 | 
    
    
| gen_buffs[3].gen_bits[0].u_prim_buf | 
100.00 | 
100.00 | 
 | 
 | 
 | 
 | 
 | 
    
    
| gen_generic.u_impl_generic | 
100.00 | 
100.00 | 
 | 
 | 
 | 
 | 
 | 
    
    
| gen_buffs[3].gen_bits[1].u_prim_buf | 
100.00 | 
100.00 | 
 | 
 | 
 | 
 | 
 | 
    
    
| gen_generic.u_impl_generic | 
100.00 | 
100.00 | 
 | 
 | 
 | 
 | 
 | 
    
    
| gen_buffs[3].gen_bits[2].u_prim_buf | 
100.00 | 
100.00 | 
 | 
 | 
 | 
 | 
 | 
    
    
| gen_generic.u_impl_generic | 
100.00 | 
100.00 | 
 | 
 | 
 | 
 | 
 | 
    
    
| gen_buffs[3].gen_bits[3].u_prim_buf | 
100.00 | 
100.00 | 
 | 
 | 
 | 
 | 
 | 
    
    
| gen_generic.u_impl_generic | 
100.00 | 
100.00 | 
 | 
 | 
 | 
 | 
 | 
    
    
| u_erase | 
 92.22 | 
100.00 | 
 88.89 | 
 | 
100.00 | 
 80.00 | 
 | 
    
    
| u_host_arb | 
 93.98 | 
 75.93 | 
100.00 | 
 | 
 | 
100.00 | 
100.00 | 
    
    
| gen_input_bufs[0].gen_data_bufs[0].u_dat_buf | 
  0.00 | 
  0.00 | 
 | 
 | 
 | 
 | 
 | 
    
    
| gen_generic.u_impl_generic | 
  0.00 | 
  0.00 | 
 | 
 | 
 | 
 | 
 | 
    
    
| gen_input_bufs[0].gen_data_bufs[1].u_dat_buf | 
  0.00 | 
  0.00 | 
 | 
 | 
 | 
 | 
 | 
    
    
| gen_generic.u_impl_generic | 
  0.00 | 
  0.00 | 
 | 
 | 
 | 
 | 
 | 
    
    
| gen_input_bufs[0].gen_fixed_arbiter.u_arb | 
 96.88 | 
 87.50 | 
100.00 | 
 | 
 | 
100.00 | 
100.00 | 
    
    
| gen_input_bufs[0].u_req_buf | 
100.00 | 
100.00 | 
 | 
 | 
 | 
 | 
 | 
    
    
| gen_generic.u_impl_generic | 
100.00 | 
100.00 | 
 | 
 | 
 | 
 | 
 | 
    
    
| gen_input_bufs[1].gen_data_bufs[0].u_dat_buf | 
  0.00 | 
  0.00 | 
 | 
 | 
 | 
 | 
 | 
    
    
| gen_generic.u_impl_generic | 
  0.00 | 
  0.00 | 
 | 
 | 
 | 
 | 
 | 
    
    
| gen_input_bufs[1].gen_data_bufs[1].u_dat_buf | 
  0.00 | 
  0.00 | 
 | 
 | 
 | 
 | 
 | 
    
    
| gen_generic.u_impl_generic | 
  0.00 | 
  0.00 | 
 | 
 | 
 | 
 | 
 | 
    
    
| gen_input_bufs[1].gen_fixed_arbiter.u_arb | 
 96.88 | 
 87.50 | 
100.00 | 
 | 
 | 
100.00 | 
100.00 | 
    
    
| gen_input_bufs[1].u_req_buf | 
100.00 | 
100.00 | 
 | 
 | 
 | 
 | 
 | 
    
    
| gen_generic.u_impl_generic | 
100.00 | 
100.00 | 
 | 
 | 
 | 
 | 
 | 
    
    
| u_host_outstanding_cnt | 
100.00 | 
 | 
 | 
100.00 | 
 | 
 | 
 | 
    
    
| u_rd | 
 97.05 | 
 97.64 | 
 93.07 | 
100.00 | 
 | 
 99.37 | 
 95.16 | 
    
    
| gen_bufs[0].u_rd_buf | 
 94.64 | 
100.00 | 
 78.57 | 
 | 
 | 
100.00 | 
100.00 | 
    
    
| gen_bufs[1].u_rd_buf | 
 94.64 | 
100.00 | 
 78.57 | 
 | 
 | 
100.00 | 
100.00 | 
    
    
| gen_bufs[2].u_rd_buf | 
 94.64 | 
100.00 | 
 78.57 | 
 | 
 | 
100.00 | 
100.00 | 
    
    
| gen_bufs[3].u_rd_buf | 
 94.64 | 
100.00 | 
 78.57 | 
 | 
 | 
100.00 | 
100.00 | 
    
    
| gen_rd.gen_bus_words_intg[0].u_bus_intg | 
100.00 | 
100.00 | 
 | 
 | 
 | 
 | 
 | 
    
    
| u_data_gen | 
100.00 | 
100.00 | 
 | 
 | 
 | 
 | 
 | 
    
    
| gen_rd.gen_bus_words_intg[0].u_prim_buf_intg | 
100.00 | 
100.00 | 
 | 
 | 
 | 
 | 
 | 
    
    
| gen_generic.u_impl_generic | 
100.00 | 
100.00 | 
 | 
 | 
 | 
 | 
 | 
    
    
| gen_rd.gen_bus_words_intg[1].u_bus_intg | 
100.00 | 
100.00 | 
 | 
 | 
 | 
 | 
 | 
    
    
| u_data_gen | 
100.00 | 
100.00 | 
 | 
 | 
 | 
 | 
 | 
    
    
| gen_rd.gen_bus_words_intg[1].u_prim_buf_intg | 
100.00 | 
100.00 | 
 | 
 | 
 | 
 | 
 | 
    
    
| gen_generic.u_impl_generic | 
100.00 | 
100.00 | 
 | 
 | 
 | 
 | 
 | 
    
    
| u_addr_xor_storage | 
 96.53 | 
100.00 | 
 86.11 | 
 | 
 | 
100.00 | 
100.00 | 
    
    
| gen_normal_fifo.u_fifo_cnt | 
100.00 | 
100.00 | 
100.00 | 
 | 
 | 
100.00 | 
 | 
    
    
| u_bus_inv_data_intg | 
  0.00 | 
  0.00 | 
 | 
 | 
 | 
 | 
 | 
    
    
| u_data_gen | 
  0.00 | 
  0.00 | 
 | 
 | 
 | 
 | 
 | 
    
    
| u_dec | 
100.00 | 
100.00 | 
100.00 | 
 | 
 | 
 | 
 | 
    
    
| u_intg_buf | 
100.00 | 
100.00 | 
 | 
 | 
 | 
 | 
 | 
    
    
| u_secure_anchor_buf | 
100.00 | 
100.00 | 
 | 
 | 
 | 
 | 
 | 
    
    
| gen_generic.u_impl_generic | 
100.00 | 
100.00 | 
 | 
 | 
 | 
 | 
 | 
    
    
| u_mask_storage | 
 93.75 | 
100.00 | 
 80.56 | 
 | 
 | 
 94.44 | 
100.00 | 
    
    
| gen_normal_fifo.u_fifo_cnt | 
 93.64 | 
100.00 | 
 90.00 | 
 | 
 | 
 90.91 | 
 | 
    
    
| u_plain_enc | 
100.00 | 
100.00 | 
 | 
 | 
 | 
 | 
 | 
    
    
| u_prim_buf_data_xor_out | 
100.00 | 
100.00 | 
 | 
 | 
 | 
 | 
 | 
    
    
| gen_generic.u_impl_generic | 
100.00 | 
100.00 | 
 | 
 | 
 | 
 | 
 | 
    
    
| u_rd_buf_dep | 
 96.59 | 
100.00 | 
 86.36 | 
 | 
 | 
100.00 | 
100.00 | 
    
    
| u_rd_storage | 
 97.44 | 
100.00 | 
 87.18 | 
100.00 | 
 | 
100.00 | 
100.00 | 
    
    
| gen_normal_fifo.u_fifo_cnt | 
100.00 | 
100.00 | 
100.00 | 
100.00 | 
 | 
100.00 | 
 | 
    
    
| gen_secure_ptrs.u_rptr | 
100.00 | 
 | 
 | 
100.00 | 
 | 
 | 
 | 
    
    
| gen_secure_ptrs.u_wptr | 
100.00 | 
 | 
 | 
100.00 | 
 | 
 | 
 | 
    
    
| u_rsp_order_fifo | 
 97.44 | 
100.00 | 
 87.18 | 
100.00 | 
 | 
100.00 | 
100.00 | 
    
    
| gen_normal_fifo.u_fifo_cnt | 
100.00 | 
100.00 | 
100.00 | 
100.00 | 
 | 
100.00 | 
 | 
    
    
| gen_secure_ptrs.u_rptr | 
100.00 | 
 | 
 | 
100.00 | 
 | 
 | 
 | 
    
    
| gen_secure_ptrs.u_wptr | 
100.00 | 
 | 
 | 
100.00 | 
 | 
 | 
 | 
    
    
| u_valid_random | 
 92.50 | 
 92.31 | 
 97.69 | 
 | 
 | 
100.00 | 
 80.00 | 
    
    
| u_state_regs | 
100.00 | 
100.00 | 
 | 
 | 
 | 
100.00 | 
100.00 | 
    
    
| u_state_flop | 
100.00 | 
100.00 | 
 | 
 | 
 | 
100.00 | 
 | 
    
    
| gen_generic.u_impl_generic | 
100.00 | 
100.00 | 
 | 
 | 
 | 
100.00 | 
 | 
    
    
| gen_flash_cores[1].u_host_rsp_fifo | 
 96.60 | 
100.00 | 
 82.98 | 
100.00 | 
 | 
100.00 | 
100.00 | 
    
    
| gen_normal_fifo.u_fifo_cnt | 
 97.83 | 
100.00 | 
 91.30 | 
100.00 | 
 | 
100.00 | 
 | 
    
    
| gen_secure_ptrs.u_rptr | 
100.00 | 
 | 
 | 
100.00 | 
 | 
 | 
 | 
    
    
| gen_secure_ptrs.u_wptr | 
100.00 | 
 | 
 | 
100.00 | 
 | 
 | 
 | 
    
    
| u_bank_sequence_fifo | 
 96.53 | 
100.00 | 
 86.11 | 
 | 
 | 
100.00 | 
100.00 | 
    
    
| gen_normal_fifo.u_fifo_cnt | 
100.00 | 
100.00 | 
100.00 | 
 | 
 | 
100.00 | 
 | 
    
    
| u_disable_buf | 
100.00 | 
100.00 | 
 | 
 | 
 | 
 | 
100.00 | 
    
    
| gen_buffs[0].gen_bits[0].u_prim_buf | 
100.00 | 
100.00 | 
 | 
 | 
 | 
 | 
 | 
    
    
| gen_generic.u_impl_generic | 
100.00 | 
100.00 | 
 | 
 | 
 | 
 | 
 | 
    
    
| gen_buffs[0].gen_bits[1].u_prim_buf | 
100.00 | 
100.00 | 
 | 
 | 
 | 
 | 
 | 
    
    
| gen_generic.u_impl_generic | 
100.00 | 
100.00 | 
 | 
 | 
 | 
 | 
 | 
    
    
| gen_buffs[0].gen_bits[2].u_prim_buf | 
100.00 | 
100.00 | 
 | 
 | 
 | 
 | 
 | 
    
    
| gen_generic.u_impl_generic | 
100.00 | 
100.00 | 
 | 
 | 
 | 
 | 
 | 
    
    
| gen_buffs[0].gen_bits[3].u_prim_buf | 
100.00 | 
100.00 | 
 | 
 | 
 | 
 | 
 | 
    
    
| gen_generic.u_impl_generic | 
100.00 | 
100.00 | 
 | 
 | 
 | 
 | 
 | 
    
    
| gen_buffs[1].gen_bits[0].u_prim_buf | 
100.00 | 
100.00 | 
 | 
 | 
 | 
 | 
 | 
    
    
| gen_generic.u_impl_generic | 
100.00 | 
100.00 | 
 | 
 | 
 | 
 | 
 | 
    
    
| gen_buffs[1].gen_bits[1].u_prim_buf | 
100.00 | 
100.00 | 
 | 
 | 
 | 
 | 
 | 
    
    
| gen_generic.u_impl_generic | 
100.00 | 
100.00 | 
 | 
 | 
 | 
 | 
 | 
    
    
| gen_buffs[1].gen_bits[2].u_prim_buf | 
100.00 | 
100.00 | 
 | 
 | 
 | 
 | 
 | 
    
    
| gen_generic.u_impl_generic | 
100.00 | 
100.00 | 
 | 
 | 
 | 
 | 
 | 
    
    
| gen_buffs[1].gen_bits[3].u_prim_buf | 
100.00 | 
100.00 | 
 | 
 | 
 | 
 | 
 | 
    
    
| gen_generic.u_impl_generic | 
100.00 | 
100.00 | 
 | 
 | 
 | 
 | 
 | 
    
    
| gen_buffs[2].gen_bits[0].u_prim_buf | 
100.00 | 
100.00 | 
 | 
 | 
 | 
 | 
 | 
    
    
| gen_generic.u_impl_generic | 
100.00 | 
100.00 | 
 | 
 | 
 | 
 | 
 | 
    
    
| gen_buffs[2].gen_bits[1].u_prim_buf | 
100.00 | 
100.00 | 
 | 
 | 
 | 
 | 
 | 
    
    
| gen_generic.u_impl_generic | 
100.00 | 
100.00 | 
 | 
 | 
 | 
 | 
 | 
    
    
| gen_buffs[2].gen_bits[2].u_prim_buf | 
100.00 | 
100.00 | 
 | 
 | 
 | 
 | 
 | 
    
    
| gen_generic.u_impl_generic | 
100.00 | 
100.00 | 
 | 
 | 
 | 
 | 
 | 
    
    
| gen_buffs[2].gen_bits[3].u_prim_buf | 
100.00 | 
100.00 | 
 | 
 | 
 | 
 | 
 | 
    
    
| gen_generic.u_impl_generic | 
100.00 | 
100.00 | 
 | 
 | 
 | 
 | 
 | 
    
    
| u_flash | 
 97.34 | 
 98.05 | 
 94.49 | 
100.00 | 
 93.75 | 
 97.78 | 
100.00 | 
    
    
| gen_generic.u_impl_generic | 
 97.34 | 
 98.05 | 
 94.49 | 
100.00 | 
 93.75 | 
 97.78 | 
100.00 | 
    
    
| subtree... | 
 | 
 | 
 | 
 | 
 | 
 | 
 | 
    
    
| u_lc_nvm_debug_en_sync | 
100.00 | 
100.00 | 
 | 
 | 
 | 
100.00 | 
100.00 | 
    
    
| gen_buffs[0].gen_bits[0].u_prim_buf | 
100.00 | 
100.00 | 
 | 
 | 
 | 
 | 
 | 
    
    
| u_secure_anchor_buf | 
100.00 | 
100.00 | 
 | 
 | 
 | 
 | 
 | 
    
    
| gen_generic.u_impl_generic | 
100.00 | 
100.00 | 
 | 
 | 
 | 
 | 
 | 
    
    
| gen_buffs[0].gen_bits[1].u_prim_buf | 
100.00 | 
100.00 | 
 | 
 | 
 | 
 | 
 | 
    
    
| u_secure_anchor_buf | 
100.00 | 
100.00 | 
 | 
 | 
 | 
 | 
 | 
    
    
| gen_generic.u_impl_generic | 
100.00 | 
100.00 | 
 | 
 | 
 | 
 | 
 | 
    
    
| gen_buffs[0].gen_bits[2].u_prim_buf | 
100.00 | 
100.00 | 
 | 
 | 
 | 
 | 
 | 
    
    
| u_secure_anchor_buf | 
100.00 | 
100.00 | 
 | 
 | 
 | 
 | 
 | 
    
    
| gen_generic.u_impl_generic | 
100.00 | 
100.00 | 
 | 
 | 
 | 
 | 
 | 
    
    
| gen_buffs[0].gen_bits[3].u_prim_buf | 
100.00 | 
100.00 | 
 | 
 | 
 | 
 | 
 | 
    
    
| u_secure_anchor_buf | 
100.00 | 
100.00 | 
 | 
 | 
 | 
 | 
 | 
    
    
| gen_generic.u_impl_generic | 
100.00 | 
100.00 | 
 | 
 | 
 | 
 | 
 | 
    
    
| gen_buffs[1].gen_bits[0].u_prim_buf | 
100.00 | 
100.00 | 
 | 
 | 
 | 
 | 
 | 
    
    
| u_secure_anchor_buf | 
100.00 | 
100.00 | 
 | 
 | 
 | 
 | 
 | 
    
    
| gen_generic.u_impl_generic | 
100.00 | 
100.00 | 
 | 
 | 
 | 
 | 
 | 
    
    
| gen_buffs[1].gen_bits[1].u_prim_buf | 
100.00 | 
100.00 | 
 | 
 | 
 | 
 | 
 | 
    
    
| u_secure_anchor_buf | 
100.00 | 
100.00 | 
 | 
 | 
 | 
 | 
 | 
    
    
| gen_generic.u_impl_generic | 
100.00 | 
100.00 | 
 | 
 | 
 | 
 | 
 | 
    
    
| gen_buffs[1].gen_bits[2].u_prim_buf | 
100.00 | 
100.00 | 
 | 
 | 
 | 
 | 
 | 
    
    
| u_secure_anchor_buf | 
100.00 | 
100.00 | 
 | 
 | 
 | 
 | 
 | 
    
    
| gen_generic.u_impl_generic | 
100.00 | 
100.00 | 
 | 
 | 
 | 
 | 
 | 
    
    
| gen_buffs[1].gen_bits[3].u_prim_buf | 
100.00 | 
100.00 | 
 | 
 | 
 | 
 | 
 | 
    
    
| u_secure_anchor_buf | 
100.00 | 
100.00 | 
 | 
 | 
 | 
 | 
 | 
    
    
| gen_generic.u_impl_generic | 
100.00 | 
100.00 | 
 | 
 | 
 | 
 | 
 | 
    
    
| gen_buffs[2].gen_bits[0].u_prim_buf | 
100.00 | 
100.00 | 
 | 
 | 
 | 
 | 
 | 
    
    
| u_secure_anchor_buf | 
100.00 | 
100.00 | 
 | 
 | 
 | 
 | 
 | 
    
    
| gen_generic.u_impl_generic | 
100.00 | 
100.00 | 
 | 
 | 
 | 
 | 
 | 
    
    
| gen_buffs[2].gen_bits[1].u_prim_buf | 
100.00 | 
100.00 | 
 | 
 | 
 | 
 | 
 | 
    
    
| u_secure_anchor_buf | 
100.00 | 
100.00 | 
 | 
 | 
 | 
 | 
 | 
    
    
| gen_generic.u_impl_generic | 
100.00 | 
100.00 | 
 | 
 | 
 | 
 | 
 | 
    
    
| gen_buffs[2].gen_bits[2].u_prim_buf | 
100.00 | 
100.00 | 
 | 
 | 
 | 
 | 
 | 
    
    
| u_secure_anchor_buf | 
100.00 | 
100.00 | 
 | 
 | 
 | 
 | 
 | 
    
    
| gen_generic.u_impl_generic | 
100.00 | 
100.00 | 
 | 
 | 
 | 
 | 
 | 
    
    
| gen_buffs[2].gen_bits[3].u_prim_buf | 
100.00 | 
100.00 | 
 | 
 | 
 | 
 | 
 | 
    
    
| u_secure_anchor_buf | 
100.00 | 
100.00 | 
 | 
 | 
 | 
 | 
 | 
    
    
| gen_generic.u_impl_generic | 
100.00 | 
100.00 | 
 | 
 | 
 | 
 | 
 | 
    
    
| gen_buffs[3].gen_bits[0].u_prim_buf | 
100.00 | 
100.00 | 
 | 
 | 
 | 
 | 
 | 
    
    
| u_secure_anchor_buf | 
100.00 | 
100.00 | 
 | 
 | 
 | 
 | 
 | 
    
    
| gen_generic.u_impl_generic | 
100.00 | 
100.00 | 
 | 
 | 
 | 
 | 
 | 
    
    
| gen_buffs[3].gen_bits[1].u_prim_buf | 
100.00 | 
100.00 | 
 | 
 | 
 | 
 | 
 | 
    
    
| u_secure_anchor_buf | 
100.00 | 
100.00 | 
 | 
 | 
 | 
 | 
 | 
    
    
| gen_generic.u_impl_generic | 
100.00 | 
100.00 | 
 | 
 | 
 | 
 | 
 | 
    
    
| gen_buffs[3].gen_bits[2].u_prim_buf | 
100.00 | 
100.00 | 
 | 
 | 
 | 
 | 
 | 
    
    
| u_secure_anchor_buf | 
100.00 | 
100.00 | 
 | 
 | 
 | 
 | 
 | 
    
    
| gen_generic.u_impl_generic | 
100.00 | 
100.00 | 
 | 
 | 
 | 
 | 
 | 
    
    
| gen_buffs[3].gen_bits[3].u_prim_buf | 
100.00 | 
100.00 | 
 | 
 | 
 | 
 | 
 | 
    
    
| u_secure_anchor_buf | 
100.00 | 
100.00 | 
 | 
 | 
 | 
 | 
 | 
    
    
| gen_generic.u_impl_generic | 
100.00 | 
100.00 | 
 | 
 | 
 | 
 | 
 | 
    
    
| gen_buffs[4].gen_bits[0].u_prim_buf | 
100.00 | 
100.00 | 
 | 
 | 
 | 
 | 
 | 
    
    
| u_secure_anchor_buf | 
100.00 | 
100.00 | 
 | 
 | 
 | 
 | 
 | 
    
    
| gen_generic.u_impl_generic | 
100.00 | 
100.00 | 
 | 
 | 
 | 
 | 
 | 
    
    
| gen_buffs[4].gen_bits[1].u_prim_buf | 
100.00 | 
100.00 | 
 | 
 | 
 | 
 | 
 | 
    
    
| u_secure_anchor_buf | 
100.00 | 
100.00 | 
 | 
 | 
 | 
 | 
 | 
    
    
| gen_generic.u_impl_generic | 
100.00 | 
100.00 | 
 | 
 | 
 | 
 | 
 | 
    
    
| gen_buffs[4].gen_bits[2].u_prim_buf | 
100.00 | 
100.00 | 
 | 
 | 
 | 
 | 
 | 
    
    
| u_secure_anchor_buf | 
100.00 | 
100.00 | 
 | 
 | 
 | 
 | 
 | 
    
    
| gen_generic.u_impl_generic | 
100.00 | 
100.00 | 
 | 
 | 
 | 
 | 
 | 
    
    
| gen_buffs[4].gen_bits[3].u_prim_buf | 
100.00 | 
100.00 | 
 | 
 | 
 | 
 | 
 | 
    
    
| u_secure_anchor_buf | 
100.00 | 
100.00 | 
 | 
 | 
 | 
 | 
 | 
    
    
| gen_generic.u_impl_generic | 
100.00 | 
100.00 | 
 | 
 | 
 | 
 | 
 | 
    
    
| gen_flops.u_prim_flop_2sync | 
100.00 | 
100.00 | 
 | 
 | 
 | 
100.00 | 
 | 
    
    
| gen_generic.u_impl_generic | 
100.00 | 
100.00 | 
 | 
 | 
 | 
100.00 | 
 | 
    
    
| u_sync_1 | 
100.00 | 
100.00 | 
 | 
 | 
 | 
100.00 | 
 | 
    
    
| gen_generic.u_impl_generic | 
100.00 | 
100.00 | 
 | 
 | 
 | 
100.00 | 
 | 
    
    
| u_sync_2 | 
100.00 | 
100.00 | 
 | 
 | 
 | 
100.00 | 
 | 
    
    
| gen_generic.u_impl_generic | 
100.00 | 
100.00 | 
 | 
 | 
 | 
100.00 | 
 | 
    
    
| u_region_sel | 
100.00 | 
100.00 | 
100.00 | 
 | 
 | 
100.00 | 
 | 
    
    
| u_scramble | 
 97.30 | 
100.00 | 
 92.56 | 
100.00 | 
 | 
100.00 | 
 93.94 | 
    
    
| gen_gf_mult.u_mult | 
100.00 | 
100.00 | 
100.00 | 
 | 
 | 
100.00 | 
100.00 | 
    
    
| gen_prince.u_cipher | 
100.00 | 
 | 
 | 
100.00 | 
 | 
 | 
 | 
    
    
| u_prim_arbiter_tree_calc | 
 98.16 | 
100.00 | 
 98.90 | 
 | 
 | 
100.00 | 
 93.75 | 
    
    
| gen_input_bufs[0].gen_data_bufs[0].u_dat_buf | 
100.00 | 
100.00 | 
 | 
 | 
 | 
 | 
 | 
    
    
| gen_generic.u_impl_generic | 
100.00 | 
100.00 | 
 | 
 | 
 | 
 | 
 | 
    
    
| gen_input_bufs[0].gen_data_bufs[1].u_dat_buf | 
100.00 | 
100.00 | 
 | 
 | 
 | 
 | 
 | 
    
    
| gen_generic.u_impl_generic | 
100.00 | 
100.00 | 
 | 
 | 
 | 
 | 
 | 
    
    
| gen_input_bufs[0].gen_rr_arbiter.u_arb | 
 98.44 | 
100.00 | 
100.00 | 
 | 
 | 
100.00 | 
 93.75 | 
    
    
| gen_input_bufs[0].u_req_buf | 
100.00 | 
100.00 | 
 | 
 | 
 | 
 | 
 | 
    
    
| gen_generic.u_impl_generic | 
100.00 | 
100.00 | 
 | 
 | 
 | 
 | 
 | 
    
    
| gen_input_bufs[1].gen_data_bufs[0].u_dat_buf | 
100.00 | 
100.00 | 
 | 
 | 
 | 
 | 
 | 
    
    
| gen_generic.u_impl_generic | 
100.00 | 
100.00 | 
 | 
 | 
 | 
 | 
 | 
    
    
| gen_input_bufs[1].gen_data_bufs[1].u_dat_buf | 
100.00 | 
100.00 | 
 | 
 | 
 | 
 | 
 | 
    
    
| gen_generic.u_impl_generic | 
100.00 | 
100.00 | 
 | 
 | 
 | 
 | 
 | 
    
    
| gen_input_bufs[1].gen_rr_arbiter.u_arb | 
 97.86 | 
100.00 | 
 97.67 | 
 | 
 | 
100.00 | 
 93.75 | 
    
    
| gen_input_bufs[1].u_req_buf | 
100.00 | 
100.00 | 
 | 
 | 
 | 
 | 
 | 
    
    
| gen_generic.u_impl_generic | 
100.00 | 
100.00 | 
 | 
 | 
 | 
 | 
 | 
    
    
| u_prim_arbiter_tree_op | 
 95.40 | 
100.00 | 
 87.85 | 
 | 
 | 
100.00 | 
 93.75 | 
    
    
| gen_input_bufs[0].gen_data_bufs[0].u_dat_buf | 
100.00 | 
100.00 | 
 | 
 | 
 | 
 | 
 | 
    
    
| gen_generic.u_impl_generic | 
100.00 | 
100.00 | 
 | 
 | 
 | 
 | 
 | 
    
    
| gen_input_bufs[0].gen_data_bufs[1].u_dat_buf | 
100.00 | 
100.00 | 
 | 
 | 
 | 
 | 
 | 
    
    
| gen_generic.u_impl_generic | 
100.00 | 
100.00 | 
 | 
 | 
 | 
 | 
 | 
    
    
| gen_input_bufs[0].gen_rr_arbiter.u_arb | 
 95.50 | 
100.00 | 
 88.24 | 
 | 
 | 
100.00 | 
 93.75 | 
    
    
| gen_input_bufs[0].u_req_buf | 
100.00 | 
100.00 | 
 | 
 | 
 | 
 | 
 | 
    
    
| gen_generic.u_impl_generic | 
100.00 | 
100.00 | 
 | 
 | 
 | 
 | 
 | 
    
    
| gen_input_bufs[1].gen_data_bufs[0].u_dat_buf | 
100.00 | 
100.00 | 
 | 
 | 
 | 
 | 
 | 
    
    
| gen_generic.u_impl_generic | 
100.00 | 
100.00 | 
 | 
 | 
 | 
 | 
 | 
    
    
| gen_input_bufs[1].gen_data_bufs[1].u_dat_buf | 
100.00 | 
100.00 | 
 | 
 | 
 | 
 | 
 | 
    
    
| gen_generic.u_impl_generic | 
100.00 | 
100.00 | 
 | 
 | 
 | 
 | 
 | 
    
    
| gen_input_bufs[1].gen_rr_arbiter.u_arb | 
 95.01 | 
100.00 | 
 86.27 | 
 | 
 | 
100.00 | 
 93.75 | 
    
    
| gen_input_bufs[1].u_req_buf | 
100.00 | 
100.00 | 
 | 
 | 
 | 
 | 
 | 
    
    
| gen_generic.u_impl_generic | 
100.00 | 
100.00 | 
 | 
 | 
 | 
 | 
 |