Group : cip_base_pkg::tl_errors_cg_wrap::tl_errors_cg
dashboard | hierarchy | modlist | groups | tests | asserts

Group : cip_base_pkg::tl_errors_cg_wrap::tl_errors_cg
SCOREINSTANCESWEIGHTGOALAT LEASTPER INSTANCEAUTO BIN MAXPRINT MISSING
100.00 92.59 1 100 1 1 64 64


Source File(s) :
/workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

3 Instances:
NAMESCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
tl_errors_cgs_wrap[flash_ctrl_eflash_reg_block] 77.78 1 100 1 64 64
tl_errors_cgs_wrap[flash_ctrl_core_reg_block] 100.00 1 100 1 64 64
tl_errors_cgs_wrap[flash_ctrl_prim_reg_block] 100.00 1 100 1 64 64



Group Instance : tl_errors_cgs_wrap[flash_ctrl_eflash_reg_block]
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
77.78 1 100 1 64 64



Summary for Group Instance tl_errors_cgs_wrap[flash_ctrl_eflash_reg_block]

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 15 5 10 77.78


Variables for Group Instance tl_errors_cgs_wrap[flash_ctrl_eflash_reg_block]
VARIABLE   EXPECTED   UNCOVERED   COVERED   PERCENT   GOAL   WEIGHT   AT LEAST   AUTO BIN MAX   COMMENT   
cp_csr_size_err 2 1 1 50.00 100 0 0 2
cp_instr_type_err 2 0 2 100.00 100 1 1 2
cp_mem_byte_access_err 2 1 1 50.00 100 1 1 2
cp_mem_ro_err 2 0 2 100.00 100 1 1 2
cp_mem_wo_err 2 1 1 50.00 100 0 0 2
cp_tl_protocol_err 1 0 1 100.00 100 1 1 0
cp_unmapped_err 2 1 1 50.00 100 0 0 2
cp_write_w_instr_type_err 2 1 1 50.00 100 1 1 2


Group Instance : tl_errors_cgs_wrap[flash_ctrl_core_reg_block]
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64



Summary for Group Instance tl_errors_cgs_wrap[flash_ctrl_core_reg_block]

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 15 0 15 100.00


Variables for Group Instance tl_errors_cgs_wrap[flash_ctrl_core_reg_block]
VARIABLE   EXPECTED   UNCOVERED   COVERED   PERCENT   GOAL   WEIGHT   AT LEAST   AUTO BIN MAX   COMMENT   
cp_csr_size_err 2 0 2 100.00 100 1 1 2
cp_instr_type_err 2 0 2 100.00 100 1 1 2
cp_mem_byte_access_err 2 0 2 100.00 100 1 1 2
cp_mem_ro_err 2 0 2 100.00 100 1 1 2
cp_mem_wo_err 2 0 2 100.00 100 1 1 2
cp_tl_protocol_err 1 0 1 100.00 100 1 1 0
cp_unmapped_err 2 0 2 100.00 100 1 1 2
cp_write_w_instr_type_err 2 0 2 100.00 100 1 1 2


Group Instance : tl_errors_cgs_wrap[flash_ctrl_prim_reg_block]
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64



Summary for Group Instance tl_errors_cgs_wrap[flash_ctrl_prim_reg_block]

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 15 3 12 100.00


Variables for Group Instance tl_errors_cgs_wrap[flash_ctrl_prim_reg_block]
VARIABLE   EXPECTED   UNCOVERED   COVERED   PERCENT   GOAL   WEIGHT   AT LEAST   AUTO BIN MAX   COMMENT   
cp_csr_size_err 2 0 2 100.00 100 1 1 2
cp_instr_type_err 2 0 2 100.00 100 1 1 2
cp_mem_byte_access_err 2 1 1 50.00 100 0 0 2
cp_mem_ro_err 2 1 1 50.00 100 0 0 2
cp_mem_wo_err 2 1 1 50.00 100 0 0 2
cp_tl_protocol_err 1 0 1 100.00 100 1 1 0
cp_unmapped_err 2 0 2 100.00 100 1 1 2
cp_write_w_instr_type_err 2 0 2 100.00 100 1 1 2


Summary for Variable cp_csr_size_err

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 1 1 50.00


Automatically Generated Bins for cp_csr_size_err

Bins
NAME   COUNT   AT LEAST   TEST   COUNT   TEST   COUNT   TEST   COUNT   
[auto[1]] 0 0 - - - - - -
auto[0] 2069 0 T3 97 T55 33 T57 69


Summary for Variable cp_instr_type_err

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_instr_type_err

Bins
NAME   COUNT   AT LEAST   TEST   COUNT   TEST   COUNT   TEST   COUNT   
auto[0] 1633 1 T127 95 T77 7 T130 115
auto[1] 436 1 T3 97 T55 33 T57 69


Summary for Variable cp_mem_byte_access_err

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 1 1 50.00


Automatically Generated Bins for cp_mem_byte_access_err

Uncovered bins
NAMECOUNTAT LEASTNUMBER
[auto[1]] 0 1 1


Covered bins
NAMECOUNTAT LEASTTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 2069 1 T3 97 T55 33 T57 69


Summary for Variable cp_mem_ro_err

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_mem_ro_err

Bins
NAME   COUNT   AT LEAST   TEST   COUNT   TEST   COUNT   TEST   COUNT   
auto[0] 2056 1 T3 97 T55 33 T57 69
auto[1] 13 1 T127 1 T77 1 T130 1


Summary for Variable cp_mem_wo_err

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 1 1 50.00


Automatically Generated Bins for cp_mem_wo_err

Bins
NAME   COUNT   AT LEAST   TEST   COUNT   TEST   COUNT   TEST   COUNT   
[auto[1]] 0 0 - - - - - -
auto[0] 2069 0 T3 97 T55 33 T57 69


Summary for Variable cp_tl_protocol_err

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 1 0 1 100.00


User Defined Bins for cp_tl_protocol_err

Bins
NAMECOUNTAT LEASTTESTCOUNTTESTCOUNTTESTCOUNT
covered 1537 1 T127 94 T77 6 T130 114


Summary for Variable cp_unmapped_err

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 1 1 50.00


Automatically Generated Bins for cp_unmapped_err

Bins
NAME   COUNT   AT LEAST   TEST   COUNT   TEST   COUNT   TEST   COUNT   
[auto[1]] 0 0 - - - - - -
auto[0] 2069 0 T3 97 T55 33 T57 69


Summary for Variable cp_write_w_instr_type_err

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 1 1 50.00


Automatically Generated Bins for cp_write_w_instr_type_err

Uncovered bins
NAMECOUNTAT LEASTNUMBER
[auto[1]] 0 1 1


Covered bins
NAMECOUNTAT LEASTTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 2069 1 T3 97 T55 33 T57 69


Summary for Variable cp_csr_size_err

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_csr_size_err

Bins
NAME   COUNT   AT LEAST   TEST   COUNT   TEST   COUNT   TEST   COUNT   
auto[0] 6995 1 T127 504 T77 5 T130 122
auto[1] 1276 1 T127 74 T130 57 T224 60


Summary for Variable cp_instr_type_err

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_instr_type_err

Bins
NAME   COUNT   AT LEAST   TEST   COUNT   TEST   COUNT   TEST   COUNT   
auto[0] 6257 1 T127 447 T77 2 T130 140
auto[1] 2014 1 T127 131 T77 3 T130 39


Summary for Variable cp_mem_byte_access_err

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_mem_byte_access_err

Bins
NAME   COUNT   AT LEAST   TEST   COUNT   TEST   COUNT   TEST   COUNT   
auto[0] 7945 1 T127 548 T77 5 T130 159
auto[1] 326 1 T127 30 T130 20 T224 35


Summary for Variable cp_mem_ro_err

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_mem_ro_err

Bins
NAME   COUNT   AT LEAST   TEST   COUNT   TEST   COUNT   TEST   COUNT   
auto[0] 8264 1 T127 578 T77 5 T130 179
auto[1] 7 1 T226 1 T258 1 T256 1


Summary for Variable cp_mem_wo_err

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_mem_wo_err

Bins
NAME   COUNT   AT LEAST   TEST   COUNT   TEST   COUNT   TEST   COUNT   
auto[0] 7789 1 T127 562 T77 4 T130 157
auto[1] 482 1 T127 16 T77 1 T130 22


Summary for Variable cp_tl_protocol_err

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 1 0 1 100.00


User Defined Bins for cp_tl_protocol_err

Bins
NAMECOUNTAT LEASTTESTCOUNTTESTCOUNTTESTCOUNT
covered 1872 1 T127 176 T224 121 T128 28


Summary for Variable cp_unmapped_err

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_unmapped_err

Bins
NAME   COUNT   AT LEAST   TEST   COUNT   TEST   COUNT   TEST   COUNT   
auto[0] 8141 1 T127 577 T77 5 T130 179
auto[1] 130 1 T127 1 T224 8 T225 18


Summary for Variable cp_write_w_instr_type_err

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_write_w_instr_type_err

Bins
NAME   COUNT   AT LEAST   TEST   COUNT   TEST   COUNT   TEST   COUNT   
auto[0] 6191 1 T127 428 T77 4 T130 138
auto[1] 2080 1 T127 150 T77 1 T130 41


Summary for Variable cp_csr_size_err

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_csr_size_err

Bins
NAME   COUNT   AT LEAST   TEST   COUNT   TEST   COUNT   TEST   COUNT   
auto[0] 8016 1 T127 381 T77 29 T130 111
auto[1] 733 1 T127 28 T77 8 T130 17


Summary for Variable cp_instr_type_err

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_instr_type_err

Bins
NAME   COUNT   AT LEAST   TEST   COUNT   TEST   COUNT   TEST   COUNT   
auto[0] 6301 1 T127 339 T77 32 T130 109
auto[1] 2448 1 T127 70 T77 5 T130 19


Summary for Variable cp_mem_byte_access_err

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 1 1 50.00


Automatically Generated Bins for cp_mem_byte_access_err

Bins
NAME   COUNT   AT LEAST   TEST   COUNT   TEST   COUNT   TEST   COUNT   
[auto[1]] 0 0 - - - - - -
auto[0] 8749 0 T127 409 T77 37 T130 128


Summary for Variable cp_mem_ro_err

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 1 1 50.00


Automatically Generated Bins for cp_mem_ro_err

Bins
NAME   COUNT   AT LEAST   TEST   COUNT   TEST   COUNT   TEST   COUNT   
[auto[1]] 0 0 - - - - - -
auto[0] 8749 0 T127 409 T77 37 T130 128


Summary for Variable cp_mem_wo_err

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 1 1 50.00


Automatically Generated Bins for cp_mem_wo_err

Bins
NAME   COUNT   AT LEAST   TEST   COUNT   TEST   COUNT   TEST   COUNT   
[auto[1]] 0 0 - - - - - -
auto[0] 8749 0 T127 409 T77 37 T130 128


Summary for Variable cp_tl_protocol_err

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 1 0 1 100.00


User Defined Bins for cp_tl_protocol_err

Bins
NAMECOUNTAT LEASTTESTCOUNTTESTCOUNTTESTCOUNT
covered 2938 1 T127 247 T77 19 T130 72


Summary for Variable cp_unmapped_err

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_unmapped_err

Bins
NAME   COUNT   AT LEAST   TEST   COUNT   TEST   COUNT   TEST   COUNT   
auto[0] 8555 1 T127 404 T77 37 T130 126
auto[1] 194 1 T127 5 T130 2 T224 9


Summary for Variable cp_write_w_instr_type_err

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_write_w_instr_type_err

Bins
NAME   COUNT   AT LEAST   TEST   COUNT   TEST   COUNT   TEST   COUNT   
auto[0] 6391 1 T127 350 T77 32 T130 110
auto[1] 2358 1 T127 59 T77 5 T130 18