Group : cip_base_pkg::tl_intg_err_cg_wrap::tl_intg_err_cg
dashboard | hierarchy | modlist | groups | tests | asserts

Group : cip_base_pkg::tl_intg_err_cg_wrap::tl_intg_err_cg
SCOREINSTANCESWEIGHTGOALAT LEASTPER INSTANCEAUTO BIN MAXPRINT MISSING
100.00 100.00 1 100 1 1 64 64


Source File(s) :
/workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

3 Instances:
NAMESCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
tl_intg_err_cgs_wrap[flash_ctrl_core_reg_block] 100.00 1 100 1 64 64
tl_intg_err_cgs_wrap[flash_ctrl_eflash_reg_block] 100.00 1 100 1 64 64
tl_intg_err_cgs_wrap[flash_ctrl_prim_reg_block] 100.00 1 100 1 64 64



Group Instance : tl_intg_err_cgs_wrap[flash_ctrl_core_reg_block]
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64



Summary for Group Instance tl_intg_err_cgs_wrap[flash_ctrl_core_reg_block]

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 14 0 14 100.00


Variables for Group Instance tl_intg_err_cgs_wrap[flash_ctrl_core_reg_block]
VARIABLE   EXPECTED   UNCOVERED   COVERED   PERCENT   GOAL   WEIGHT   AT LEAST   AUTO BIN MAX   COMMENT   
cp_is_mem 2 0 2 100.00 100 1 1 2
cp_num_cmd_err_bits 4 0 4 100.00 100 1 1 0
cp_num_data_err_bits 4 0 4 100.00 100 1 1 0
cp_tl_intg_err_type 4 0 4 100.00 100 1 1 0


Group Instance : tl_intg_err_cgs_wrap[flash_ctrl_eflash_reg_block]
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64



Summary for Group Instance tl_intg_err_cgs_wrap[flash_ctrl_eflash_reg_block]

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 14 1 13 100.00


Variables for Group Instance tl_intg_err_cgs_wrap[flash_ctrl_eflash_reg_block]
VARIABLE   EXPECTED   UNCOVERED   COVERED   PERCENT   GOAL   WEIGHT   AT LEAST   AUTO BIN MAX   COMMENT   
cp_is_mem 2 1 1 50.00 100 0 0 2
cp_num_cmd_err_bits 4 0 4 100.00 100 1 1 0
cp_num_data_err_bits 4 0 4 100.00 100 1 1 0
cp_tl_intg_err_type 4 0 4 100.00 100 1 1 0


Group Instance : tl_intg_err_cgs_wrap[flash_ctrl_prim_reg_block]
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64



Summary for Group Instance tl_intg_err_cgs_wrap[flash_ctrl_prim_reg_block]

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 14 1 13 100.00


Variables for Group Instance tl_intg_err_cgs_wrap[flash_ctrl_prim_reg_block]
VARIABLE   EXPECTED   UNCOVERED   COVERED   PERCENT   GOAL   WEIGHT   AT LEAST   AUTO BIN MAX   COMMENT   
cp_is_mem 2 1 1 50.00 100 0 0 2
cp_num_cmd_err_bits 4 0 4 100.00 100 1 1 0
cp_num_data_err_bits 4 0 4 100.00 100 1 1 0
cp_tl_intg_err_type 4 0 4 100.00 100 1 1 0


Summary for Variable cp_is_mem

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_is_mem

Bins
NAME   COUNT   AT LEAST   TEST   COUNT   TEST   COUNT   TEST   COUNT   
auto[0] 27729844 1 T1 20 T2 334 T3 3401
auto[1] 5018826 1 T2 30 T3 638 T8 22


Summary for Variable cp_num_cmd_err_bits

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 4 0 4 100.00


User Defined Bins for cp_num_cmd_err_bits

Bins
NAME   COUNT   AT LEAST   TEST   COUNT   TEST   COUNT   TEST   COUNT   
values[0] 32748494 1 T1 20 T2 364 T3 4039
values[1] 17 1 T247 1 T248 2 T249 4
values[2] 2 1 T363 1 T364 1 - -
values[3] 87 1 T247 3 T248 6 T249 3


Summary for Variable cp_num_data_err_bits

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 4 0 4 100.00


User Defined Bins for cp_num_data_err_bits

Bins
NAME   COUNT   AT LEAST   TEST   COUNT   TEST   COUNT   TEST   COUNT   
values[0] 32748497 1 T1 20 T2 364 T3 4039
values[1] 20 1 T249 4 T365 1 T366 2
values[2] 8 1 T365 1 T367 1 T368 1
values[3] 76 1 T247 2 T248 1 T249 1


Summary for Variable cp_tl_intg_err_type

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 4 0 4 100.00


Automatically Generated Bins for cp_tl_intg_err_type

Bins
NAME   COUNT   AT LEAST   TEST   COUNT   TEST   COUNT   TEST   COUNT   
auto[TlIntgErrNone] 32748410 1 T1 20 T2 364 T3 4039
auto[TlIntgErrCmd] 87 1 T247 3 T248 7 T249 2
auto[TlIntgErrData] 84 1 T247 3 T248 1 T249 2
auto[TlIntgErrBoth] 89 1 T247 4 T248 2 T249 6


Summary for Variable cp_is_mem

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 1 1 50.00


Automatically Generated Bins for cp_is_mem

Bins
NAME   COUNT   AT LEAST   TEST   COUNT   TEST   COUNT   TEST   COUNT   
[auto[0]] 0 0 - - - - - -
auto[1] 3791584 0 T1 10 T3 426 T8 22


Summary for Variable cp_num_cmd_err_bits

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 4 0 4 100.00


User Defined Bins for cp_num_cmd_err_bits

Bins
NAME   COUNT   AT LEAST   TEST   COUNT   TEST   COUNT   TEST   COUNT   
values[0] 3791410 1 T1 10 T3 426 T8 22
values[1] 16 1 T365 1 T369 1 T370 1
values[2] 9 1 T365 1 T371 1 T372 1
values[3] 80 1 T247 2 T248 3 T249 4


Summary for Variable cp_num_data_err_bits

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 4 0 4 100.00


User Defined Bins for cp_num_data_err_bits

Bins
NAME   COUNT   AT LEAST   TEST   COUNT   TEST   COUNT   TEST   COUNT   
values[0] 3791432 1 T1 10 T3 426 T8 22
values[1] 20 1 T249 1 T365 1 T367 2
values[2] 5 1 T247 1 T373 1 T374 1
values[3] 65 1 T247 3 T248 2 T249 2


Summary for Variable cp_tl_intg_err_type

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 4 0 4 100.00


Automatically Generated Bins for cp_tl_intg_err_type

Bins
NAME   COUNT   AT LEAST   TEST   COUNT   TEST   COUNT   TEST   COUNT   
auto[TlIntgErrNone] 3791339 1 T1 10 T3 426 T8 22
auto[TlIntgErrCmd] 93 1 T247 4 T248 4 T249 3
auto[TlIntgErrData] 71 1 T247 5 T248 3 T249 3
auto[TlIntgErrBoth] 81 1 T247 1 T248 1 T249 4


Summary for Variable cp_is_mem

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 1 1 50.00


Automatically Generated Bins for cp_is_mem

Bins
NAME   COUNT   AT LEAST   TEST   COUNT   TEST   COUNT   TEST   COUNT   
[auto[1]] 0 0 - - - - - -
auto[0] 83102 0 T127 1125 T75 65 T77 343


Summary for Variable cp_num_cmd_err_bits

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 4 0 4 100.00


User Defined Bins for cp_num_cmd_err_bits

Bins
NAME   COUNT   AT LEAST   TEST   COUNT   TEST   COUNT   TEST   COUNT   
values[0] 82931 1 T127 1125 T75 65 T77 343
values[1] 12 1 T247 3 T368 2 T370 1
values[2] 3 1 T365 1 T366 1 T363 1
values[3] 92 1 T247 5 T248 7 T249 5


Summary for Variable cp_num_data_err_bits

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 4 0 4 100.00


User Defined Bins for cp_num_data_err_bits

Bins
NAME   COUNT   AT LEAST   TEST   COUNT   TEST   COUNT   TEST   COUNT   
values[0] 82926 1 T127 1125 T75 65 T77 343
values[1] 14 1 T248 1 T249 1 T368 1
values[2] 8 1 T375 2 T373 2 T376 3
values[3] 94 1 T247 1 T248 1 T249 4


Summary for Variable cp_tl_intg_err_type

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 4 0 4 100.00


Automatically Generated Bins for cp_tl_intg_err_type

Bins
NAME   COUNT   AT LEAST   TEST   COUNT   TEST   COUNT   TEST   COUNT   
auto[TlIntgErrNone] 82842 1 T127 1125 T75 65 T77 343
auto[TlIntgErrCmd] 84 1 T247 6 T248 2 T249 2
auto[TlIntgErrData] 89 1 T248 3 T249 5 T365 5
auto[TlIntgErrBoth] 87 1 T247 4 T248 5 T249 3