Group : cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg
dashboard | hierarchy | modlist | groups | tests | asserts

Group : cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg
SCOREINSTANCESWEIGHTGOALAT LEASTPER INSTANCEAUTO BIN MAXPRINT MISSING
100.00 97.92 1 100 1 1 64 64


Source File(s) :
/workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

2 Instances:
NAMESCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
tl_intg_err_mem_subword_cgs_wrap[flash_ctrl_eflash_reg_block] 95.83 1 100 1 64 64
tl_intg_err_mem_subword_cgs_wrap[flash_ctrl_core_reg_block] 100.00 1 100 1 64 64



Group Instance : tl_intg_err_mem_subword_cgs_wrap[flash_ctrl_eflash_reg_block]
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
95.83 1 100 1 64 64



Summary for Group Instance tl_intg_err_mem_subword_cgs_wrap[flash_ctrl_eflash_reg_block]

CATEGORY   EXPECTED   UNCOVERED   COVERED   PERCENT   
Variables 8 0 8 100.00
Crosses 16 1 15 93.75


Variables for Group Instance tl_intg_err_mem_subword_cgs_wrap[flash_ctrl_eflash_reg_block]
VARIABLE   EXPECTED   UNCOVERED   COVERED   PERCENT   GOAL   WEIGHT   AT LEAST   AUTO BIN MAX   COMMENT   
cp_num_num_enable_bytes 2 0 2 100.00 100 1 1 0
cp_tl_intg_err_type 4 0 4 100.00 100 1 1 0
cp_write 2 0 2 100.00 100 1 1 2


Crosses for Group Instance tl_intg_err_mem_subword_cgs_wrap[flash_ctrl_eflash_reg_block]
CROSSEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTPRINT MISSINGCOMMENT
cr_all 16 1 15 93.75 100 1 1 0


Group Instance : tl_intg_err_mem_subword_cgs_wrap[flash_ctrl_core_reg_block]
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64



Summary for Group Instance tl_intg_err_mem_subword_cgs_wrap[flash_ctrl_core_reg_block]

CATEGORY   EXPECTED   UNCOVERED   COVERED   PERCENT   
Variables 8 0 8 100.00
Crosses 16 0 16 100.00


Variables for Group Instance tl_intg_err_mem_subword_cgs_wrap[flash_ctrl_core_reg_block]
VARIABLE   EXPECTED   UNCOVERED   COVERED   PERCENT   GOAL   WEIGHT   AT LEAST   AUTO BIN MAX   COMMENT   
cp_num_num_enable_bytes 2 0 2 100.00 100 1 1 0
cp_tl_intg_err_type 4 0 4 100.00 100 1 1 0
cp_write 2 0 2 100.00 100 1 1 2


Crosses for Group Instance tl_intg_err_mem_subword_cgs_wrap[flash_ctrl_core_reg_block]
CROSSEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTPRINT MISSINGCOMMENT
cr_all 16 0 16 100.00 100 1 1 0


Summary for Variable cp_num_num_enable_bytes

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 2 0 2 100.00


User Defined Bins for cp_num_num_enable_bytes

Bins
NAME   COUNT   AT LEAST   TEST   COUNT   TEST   COUNT   TEST   COUNT   
partial 23578 1 T127 1242 T77 148 T130 907
full_word 3768006 1 T1 10 T3 426 T8 22


Summary for Variable cp_tl_intg_err_type

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 4 0 4 100.00


Automatically Generated Bins for cp_tl_intg_err_type

Bins
NAME   COUNT   AT LEAST   TEST   COUNT   TEST   COUNT   TEST   COUNT   
auto[TlIntgErrNone] 3791339 1 T1 10 T3 426 T8 22
auto[TlIntgErrCmd] 93 1 T247 4 T248 4 T249 3
auto[TlIntgErrData] 71 1 T247 5 T248 3 T249 3
auto[TlIntgErrBoth] 81 1 T247 1 T248 1 T249 4


Summary for Variable cp_write

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_write

Bins
NAME   COUNT   AT LEAST   TEST   COUNT   TEST   COUNT   TEST   COUNT   
auto[0] 3762732 1 T1 10 T3 426 T8 22
auto[1] 28852 1 T127 1375 T77 190 T130 973


Summary for Cross cr_all

Samples crossed: cp_tl_intg_err_type cp_num_num_enable_bytes cp_write
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
Automatically Generated Cross Bins 16 1 15 93.75 1


Automatically Generated Cross Bins for cr_all

Uncovered bins
cp_tl_intg_err_typecp_num_num_enable_bytescp_writeCOUNTAT LEASTNUMBER
[auto[TlIntgErrBoth]] [full_word] [auto[0]] 0 1 1


Covered bins
cp_tl_intg_err_type   cp_num_num_enable_bytes   cp_write   COUNT   AT LEAST   TEST   COUNT   TEST   COUNT   TEST   COUNT   
auto[TlIntgErrNone] partial auto[0] 1332 1 T127 85 T77 6 T130 101
auto[TlIntgErrNone] partial auto[1] 22031 1 T127 1157 T77 142 T130 806
auto[TlIntgErrNone] full_word auto[0] 3761302 1 T1 10 T3 426 T8 22
auto[TlIntgErrNone] full_word auto[1] 6674 1 T127 218 T77 48 T130 167
auto[TlIntgErrCmd] partial auto[0] 30 1 T248 2 T249 1 T365 3
auto[TlIntgErrCmd] partial auto[1] 48 1 T247 2 T248 2 T249 2
auto[TlIntgErrCmd] full_word auto[0] 5 1 T247 2 T371 1 T372 1
auto[TlIntgErrCmd] full_word auto[1] 10 1 T369 2 T371 1 T370 1
auto[TlIntgErrData] partial auto[0] 32 1 T247 1 T248 2 T249 2
auto[TlIntgErrData] partial auto[1] 30 1 T247 2 T248 1 T249 1
auto[TlIntgErrData] full_word auto[0] 5 1 T247 1 T369 1 T375 1
auto[TlIntgErrData] full_word auto[1] 4 1 T247 1 T369 1 T374 1
auto[TlIntgErrBoth] partial auto[0] 26 1 T249 1 T365 2 T367 2
auto[TlIntgErrBoth] partial auto[1] 49 1 T247 1 T248 1 T249 3
auto[TlIntgErrBoth] full_word auto[1] 6 1 T372 1 T376 1 T363 3


Summary for Variable cp_num_num_enable_bytes

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 2 0 2 100.00


User Defined Bins for cp_num_num_enable_bytes

Bins
NAME   COUNT   AT LEAST   TEST   COUNT   TEST   COUNT   TEST   COUNT   
partial 25239317 1 T1 15 T2 310 T3 1086
full_word 7509353 1 T1 5 T2 54 T3 2953


Summary for Variable cp_tl_intg_err_type

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 4 0 4 100.00


Automatically Generated Bins for cp_tl_intg_err_type

Bins
NAME   COUNT   AT LEAST   TEST   COUNT   TEST   COUNT   TEST   COUNT   
auto[TlIntgErrNone] 32748410 1 T1 20 T2 364 T3 4039
auto[TlIntgErrCmd] 87 1 T247 3 T248 7 T249 2
auto[TlIntgErrData] 84 1 T247 3 T248 1 T249 2
auto[TlIntgErrBoth] 89 1 T247 4 T248 2 T249 6


Summary for Variable cp_write

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_write

Bins
NAME   COUNT   AT LEAST   TEST   COUNT   TEST   COUNT   TEST   COUNT   
auto[0] 28415168 1 T1 16 T2 323 T3 1538
auto[1] 4333502 1 T1 4 T2 41 T3 2501


Summary for Cross cr_all

Samples crossed: cp_tl_intg_err_type cp_num_num_enable_bytes cp_write
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
Automatically Generated Cross Bins 16 0 16 100.00


Automatically Generated Cross Bins for cr_all

Bins
cp_tl_intg_err_type   cp_num_num_enable_bytes   cp_write   COUNT   AT LEAST   TEST   COUNT   TEST   COUNT   TEST   COUNT   
auto[TlIntgErrNone] partial auto[0] 24558616 1 T1 15 T2 300 T3 876
auto[TlIntgErrNone] partial auto[1] 680468 1 T2 10 T3 210 T8 3
auto[TlIntgErrNone] full_word auto[0] 3856443 1 T1 1 T2 23 T3 662
auto[TlIntgErrNone] full_word auto[1] 3652883 1 T1 4 T2 31 T3 2291
auto[TlIntgErrCmd] partial auto[0] 32 1 T248 1 T367 1 T366 3
auto[TlIntgErrCmd] partial auto[1] 47 1 T247 2 T248 5 T249 2
auto[TlIntgErrCmd] full_word auto[0] 3 1 T247 1 T377 1 T378 1
auto[TlIntgErrCmd] full_word auto[1] 5 1 T248 1 T369 1 T376 1
auto[TlIntgErrData] partial auto[0] 36 1 T247 2 T249 1 T365 1
auto[TlIntgErrData] partial auto[1] 38 1 T247 1 T248 1 T249 1
auto[TlIntgErrData] full_word auto[0] 6 1 T368 1 T375 1 T373 1
auto[TlIntgErrData] full_word auto[1] 4 1 T375 1 T377 1 T363 1
auto[TlIntgErrBoth] partial auto[0] 29 1 T247 2 T248 1 T249 2
auto[TlIntgErrBoth] partial auto[1] 51 1 T248 1 T249 4 T365 3
auto[TlIntgErrBoth] full_word auto[0] 3 1 T247 1 T379 1 T377 1
auto[TlIntgErrBoth] full_word auto[1] 6 1 T247 1 T365 1 T373 1