Group : cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg
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Group : cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg
SCOREINSTANCESWEIGHTGOALAT LEASTPER INSTANCEAUTO BIN MAXPRINT MISSING
100.00 97.92 1 100 1 1 64 64


Source File(s) :
/workspaces/repo/scratch/os_regression_2024_09_10/flash_ctrl-sim-vcs/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

2 Instances:
NAMESCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
tl_intg_err_mem_subword_cgs_wrap[flash_ctrl_core_reg_block] 95.83 1 100 1 64 64
tl_intg_err_mem_subword_cgs_wrap[flash_ctrl_eflash_reg_block] 100.00 1 100 1 64 64



Group Instance : tl_intg_err_mem_subword_cgs_wrap[flash_ctrl_core_reg_block]
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
95.83 1 100 1 64 64



Summary for Group Instance tl_intg_err_mem_subword_cgs_wrap[flash_ctrl_core_reg_block]

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 8 0 8 100.00
Crosses 16 1 15 93.75


Variables for Group Instance tl_intg_err_mem_subword_cgs_wrap[flash_ctrl_core_reg_block]
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
cp_num_num_enable_bytes 2 0 2 100.00 100 1 1 0
cp_tl_intg_err_type 4 0 4 100.00 100 1 1 0
cp_write 2 0 2 100.00 100 1 1 2


Crosses for Group Instance tl_intg_err_mem_subword_cgs_wrap[flash_ctrl_core_reg_block]
CROSSEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTPRINT MISSINGCOMMENT
cr_all 16 1 15 93.75 100 1 1 0


Group Instance : tl_intg_err_mem_subword_cgs_wrap[flash_ctrl_eflash_reg_block]
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64



Summary for Group Instance tl_intg_err_mem_subword_cgs_wrap[flash_ctrl_eflash_reg_block]

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 8 0 8 100.00
Crosses 16 0 16 100.00


Variables for Group Instance tl_intg_err_mem_subword_cgs_wrap[flash_ctrl_eflash_reg_block]
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
cp_num_num_enable_bytes 2 0 2 100.00 100 1 1 0
cp_tl_intg_err_type 4 0 4 100.00 100 1 1 0
cp_write 2 0 2 100.00 100 1 1 2


Crosses for Group Instance tl_intg_err_mem_subword_cgs_wrap[flash_ctrl_eflash_reg_block]
CROSSEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTPRINT MISSINGCOMMENT
cr_all 16 0 16 100.00 100 1 1 0


Summary for Variable cp_num_num_enable_bytes

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 2 0 2 100.00


User Defined Bins for cp_num_num_enable_bytes

Bins
NAMECOUNTAT LEASTTESTCOUNTTESTCOUNTTESTCOUNT
partial 23467040 1 T1 15 T2 74 T3 770
full_word 7742268 1 T1 4 T2 57 T3 2082


Summary for Variable cp_tl_intg_err_type

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 4 0 4 100.00


Automatically Generated Bins for cp_tl_intg_err_type

Bins
NAMECOUNTAT LEASTTESTCOUNTTESTCOUNTTESTCOUNT
auto[TlIntgErrNone] 31208998 1 T1 19 T2 131 T3 2852
auto[TlIntgErrCmd] 101 1 T266 5 T267 1 T268 4
auto[TlIntgErrData] 99 1 T266 1 T267 3 T268 3
auto[TlIntgErrBoth] 110 1 T266 4 T267 6 T268 3


Summary for Variable cp_write

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_write

Bins
NAMECOUNTAT LEASTTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 26763936 1 T1 15 T2 90 T3 1086
auto[1] 4445372 1 T1 4 T2 41 T3 1766


Summary for Cross cr_all

Samples crossed: cp_tl_intg_err_type cp_num_num_enable_bytes cp_write
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
Automatically Generated Cross Bins 16 1 15 93.75 1


Automatically Generated Cross Bins for cr_all

Uncovered bins
cp_tl_intg_err_typecp_num_num_enable_bytescp_writeCOUNTAT LEASTNUMBER
[auto[TlIntgErrCmd]] [full_word] [auto[0]] 0 1 1


Covered bins
cp_tl_intg_err_typecp_num_num_enable_bytescp_writeCOUNTAT LEASTTESTCOUNTTESTCOUNTTESTCOUNT
auto[TlIntgErrNone] partial auto[0] 22717525 1 T1 14 T2 68 T3 625
auto[TlIntgErrNone] partial auto[1] 749220 1 T1 1 T2 6 T3 145
auto[TlIntgErrNone] full_word auto[0] 4046275 1 T1 1 T2 22 T3 461
auto[TlIntgErrNone] full_word auto[1] 3695978 1 T1 3 T2 35 T3 1621
auto[TlIntgErrCmd] partial auto[0] 38 1 T266 4 T268 2 T355 3
auto[TlIntgErrCmd] partial auto[1] 59 1 T266 1 T267 1 T268 2
auto[TlIntgErrCmd] full_word auto[1] 4 1 T285 1 T283 1 T360 1
auto[TlIntgErrData] partial auto[0] 48 1 T267 1 T268 2 T355 1
auto[TlIntgErrData] partial auto[1] 46 1 T266 1 T267 2 T268 1
auto[TlIntgErrData] full_word auto[0] 2 1 T285 1 T362 1 - -
auto[TlIntgErrData] full_word auto[1] 3 1 T358 1 T285 1 T362 1
auto[TlIntgErrBoth] partial auto[0] 46 1 T266 2 T267 2 T268 2
auto[TlIntgErrBoth] partial auto[1] 58 1 T266 2 T267 4 T268 1
auto[TlIntgErrBoth] full_word auto[0] 2 1 T354 1 T361 1 - -
auto[TlIntgErrBoth] full_word auto[1] 4 1 T353 1 T279 1 T283 1


Summary for Variable cp_num_num_enable_bytes

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 2 0 2 100.00


User Defined Bins for cp_num_num_enable_bytes

Bins
NAMECOUNTAT LEASTTESTCOUNTTESTCOUNTTESTCOUNT
partial 19617 1 T74 975 T121 645 T76 254
full_word 3801111 1 T1 10 T3 245 T11 148


Summary for Variable cp_tl_intg_err_type

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 4 0 4 100.00


Automatically Generated Bins for cp_tl_intg_err_type

Bins
NAMECOUNTAT LEASTTESTCOUNTTESTCOUNTTESTCOUNT
auto[TlIntgErrNone] 3820438 1 T1 10 T3 245 T11 148
auto[TlIntgErrCmd] 80 1 T266 4 T267 1 T268 2
auto[TlIntgErrData] 110 1 T266 2 T267 6 T268 2
auto[TlIntgErrBoth] 100 1 T266 4 T267 3 T268 2


Summary for Variable cp_write

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_write

Bins
NAMECOUNTAT LEASTTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 3795887 1 T1 10 T3 245 T11 148
auto[1] 24841 1 T74 1435 T121 1016 T76 312


Summary for Cross cr_all

Samples crossed: cp_tl_intg_err_type cp_num_num_enable_bytes cp_write
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
Automatically Generated Cross Bins 16 0 16 100.00


Automatically Generated Cross Bins for cr_all

Bins
cp_tl_intg_err_typecp_num_num_enable_bytescp_writeCOUNTAT LEASTTESTCOUNTTESTCOUNTTESTCOUNT
auto[TlIntgErrNone] partial auto[0] 1433 1 T74 83 T121 29 T76 12
auto[TlIntgErrNone] partial auto[1] 17914 1 T74 892 T121 616 T76 242
auto[TlIntgErrNone] full_word auto[0] 3794339 1 T1 10 T3 245 T11 148
auto[TlIntgErrNone] full_word auto[1] 6752 1 T74 543 T121 400 T76 70
auto[TlIntgErrCmd] partial auto[0] 23 1 T266 2 T355 1 T353 1
auto[TlIntgErrCmd] partial auto[1] 54 1 T266 1 T267 1 T268 2
auto[TlIntgErrCmd] full_word auto[0] 1 1 T362 1 - - - -
auto[TlIntgErrCmd] full_word auto[1] 2 1 T266 1 T355 1 - -
auto[TlIntgErrData] partial auto[0] 54 1 T267 1 T268 2 T355 3
auto[TlIntgErrData] partial auto[1] 49 1 T266 2 T267 4 T353 4
auto[TlIntgErrData] full_word auto[0] 4 1 T354 1 T280 1 T363 1
auto[TlIntgErrData] full_word auto[1] 3 1 T267 1 T353 1 T362 1
auto[TlIntgErrBoth] partial auto[0] 30 1 T266 1 T268 1 T355 2
auto[TlIntgErrBoth] partial auto[1] 60 1 T266 2 T267 3 T268 1
auto[TlIntgErrBoth] full_word auto[0] 3 1 T363 1 T362 2 - -
auto[TlIntgErrBoth] full_word auto[1] 7 1 T266 1 T358 2 T280 1

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