Unified Coverage Report :: Module :: prim_arbiter_fixed

Module : prim_arbiter_fixed

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.88	87.50	100.00			100.00	100.00

Source File(s) :
/workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_eflash.gen_flash_cores[0].u_core.u_host_arb.gen_input_bufs[0].gen_fixed_arbiter.u_arb	96.88	87.50	100.00			100.00	100.00
tb.dut.u_eflash.gen_flash_cores[0].u_core.u_host_arb.gen_input_bufs[1].gen_fixed_arbiter.u_arb	96.88	87.50	100.00			100.00	100.00
tb.dut.u_eflash.gen_flash_cores[1].u_core.u_host_arb.gen_input_bufs[0].gen_fixed_arbiter.u_arb	96.88	87.50	100.00			100.00	100.00
tb.dut.u_eflash.gen_flash_cores[1].u_core.u_host_arb.gen_input_bufs[1].gen_fixed_arbiter.u_arb	96.88	87.50	100.00			100.00	100.00

---

Module Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_host_arb.gen_input_bufs[0].gen_fixed_arbiter.u_arb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.88	87.50	100.00			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.88	87.50	100.00			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.67	90.00	100.00			100.00		u_host_arb

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_host_arb.gen_input_bufs[1].gen_fixed_arbiter.u_arb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.88	87.50	100.00			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.88	87.50	100.00			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.67	90.00	100.00			100.00		u_host_arb

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_host_arb.gen_input_bufs[0].gen_fixed_arbiter.u_arb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.88	87.50	100.00			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.88	87.50	100.00			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.67	90.00	100.00			100.00		u_host_arb

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_host_arb.gen_input_bufs[1].gen_fixed_arbiter.u_arb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.88	87.50	100.00			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.88	87.50	100.00			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.67	90.00	100.00			100.00		u_host_arb

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Module : prim_arbiter_fixed

	Line No.	Total	Covered	Percent
TOTAL		16	14	87.50
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	87	1	0	0.00
CONT_ASSIGN	87	1	0	0.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	89	1	1	100.00
ALWAYS	105	6	6	100.00
CONT_ASSIGN	124	1	1	100.00
CONT_ASSIGN	128	1	1	100.00
CONT_ASSIGN	129	1	1	100.00
CONT_ASSIGN	132	1	1	100.00

84                                  // forward path
85         2/2                      assign req_tree[Pa]      = req_i[offset];
           Tests:       T1 T2 T3  | T1 T2 T3 
86                                  assign idx_tree[Pa]      = offset;
87         0/2     ==>              assign data_tree[Pa]     = data_i[offset];
88                                  // backward (grant) path
89         2/2                      assign gnt_o[offset]     = gnt_tree[Pa];
           Tests:       T1 T2 T3  | T1 T2 T3 
90                      
91                                end else begin : gen_tie_off
92                                  // forward path
93                                  assign req_tree[Pa]  = '0;
94                                  assign idx_tree[Pa]  = '0;
95                                  assign data_tree[Pa] = '0;
96                                  logic unused_sigs;
97                                  assign unused_sigs = gnt_tree[Pa];
98                                end
99                              // this creates the node assignments
100                             end else begin : gen_nodes
101                               // forward path
102                               logic sel; // local helper variable
103                               always_comb begin : p_node
104                                 // this always gives priority to the left child
105        1/1                      sel = ~req_tree[C0];
           Tests:       T1 T2 T3 
106                                 // propagate requests
107        1/1                      req_tree[Pa]  = req_tree[C0] | req_tree[C1];
           Tests:       T1 T2 T3 
108                                 // data and index muxes
109        1/1                      idx_tree[Pa]  = (sel) ? idx_tree[C1]  : idx_tree[C0];
           Tests:       T1 T2 T3 
110        1/1                      data_tree[Pa] = (sel) ? data_tree[C1] : data_tree[C0];
           Tests:       T1 T2 T3 
111                                 // propagate the grants back to the input
112        1/1                      gnt_tree[C0] = gnt_tree[Pa] & ~sel;
           Tests:       T1 T2 T3 
113        1/1                      gnt_tree[C1] = gnt_tree[Pa] &  sel;
           Tests:       T1 T2 T3 
114                               end
115                             end
116                           end : gen_level
117                         end : gen_tree
118                     
119                         // the results can be found at the tree root
120                         if (EnDataPort) begin : gen_data_port
121                           assign data_o      = data_tree[0];
122                         end else begin : gen_no_dataport
123                           logic [DW-1:0] unused_data;
124        1/1                assign unused_data = data_tree[0];
           Tests:       T1 T2 T8 
125                           assign data_o = '1;
126                         end
127                     
128        1/1              assign idx_o       = idx_tree[0];
           Tests:       T1 T2 T3 
129        1/1              assign valid_o     = req_tree[0];
           Tests:       T1 T2 T3 
130                     
131                         // this propagates a grant back to the input
132        1/1              assign gnt_tree[0] = valid_o & ready_i;
           Tests:       T1 T2 T3 

---

Cond Coverage for Module : prim_arbiter_fixed

	Total	Covered	Percent
Conditions	16	16	100.00
Logical	16	16	100.00
Non-Logical	0	0
Event	0	0

 LINE       107
 EXPRESSION (gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C0] | gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C1])
             ----------------------------------1----------------------------------   ----------------------------------2----------------------------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T3,T8

 LINE       109
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])

-1-	Status	Tests
0	Covered	T1,T3,T8
1	Covered	T1,T2,T3

 LINE       110
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])

-1-	Status	Tests
0	Covered	T1,T3,T8
1	Covered	T1,T2,T3

 LINE       112
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & ((~gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)))
             ----------------------------------1----------------------------------   -----------------------------2-----------------------------

-1-	-2-	Status	Tests
0	1	Covered	T3,T9,T22
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T3,T8

 LINE       113
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)
             ----------------------------------1----------------------------------   ---------------------------2--------------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T3,T8
1	1	Covered	T1,T2,T3

 LINE       132
 EXPRESSION (valid_o & ready_i)
             ---1---   ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T3,T9,T22
1	1	Covered	T1,T2,T3

---

Branch Coverage for Module : prim_arbiter_fixed

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
TERNARY	109	2	2	100.00
TERNARY	110	2	2	100.00

109                    idx_tree[Pa]  = (sel) ? idx_tree[C1]  : idx_tree[C0];
                                             -1-  
                                             ==>  
                                             ==>  

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T3,T8

110                    data_tree[Pa] = (sel) ? data_tree[C1] : data_tree[C0];
                                             -1-  
                                             ==>  
                                             ==>  

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T3,T8

---

Assert Coverage for Module : prim_arbiter_fixed

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	13	13	100.00	13	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	13	13	100.00	13	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	1533680772	1530316736	0	0
CheckNGreaterZero_A	4232	4232	0	0
GntImpliesReady_A	1533680772	399442084	0	0
GntImpliesValid_A	1533680772	399442084	0	0
GrantKnown_A	1533680772	1530316736	0	0
IdxKnown_A	1533680772	1530316736	0	0
IndexIsCorrect_A	1533680772	399442084	0	0
NoReadyValidNoGrant_A	1533680772	171479178	0	0
Priority_A	1533680772	423460234	0	0
ReadyAndValidImplyGrant_A	1533680772	399442084	0	0
ReqAndReadyImplyGrant_A	1533680772	399442084	0	0
ReqImpliesValid_A	1533680772	423460234	0	0
ValidKnown_A	1533680772	1530316736	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1533680772	1530316736	0	0
T1	4716	4328	0	0
T2	7452	7068	0	0
T3	49692	49340	0	0
T8	7744	7436	0	0
T13	14588	14208	0	0
T14	8836	8528	0	0
T15	6040	5820	0	0
T16	9484	9192	0	0
T17	788116	787756	0	0
T18	5876	5536	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	4232	4232	0	0
T1	4	4	0	0
T2	4	4	0	0
T3	4	4	0	0
T8	4	4	0	0
T13	4	4	0	0
T14	4	4	0	0
T15	4	4	0	0
T16	4	4	0	0
T17	4	4	0	0
T18	4	4	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1533680772	399442084	0	0
T1	2358	84	0	0
T2	3726	1178	0	0
T3	49692	1998	0	0
T8	7744	788	0	0
T9	0	47160	0	0
T13	14588	4444	0	0
T14	8836	356	0	0
T15	6040	584	0	0
T16	9484	356	0	0
T17	788116	76128	0	0
T18	5876	356	0	0
T22	0	19280	0	0
T29	181148	20520	0	0
T32	0	11150	0	0
T58	520898	0	0	0
T71	0	12	0	0
T72	0	85716	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1533680772	399442084	0	0
T1	2358	84	0	0
T2	3726	1178	0	0
T3	49692	1998	0	0
T8	7744	788	0	0
T9	0	47160	0	0
T13	14588	4444	0	0
T14	8836	356	0	0
T15	6040	584	0	0
T16	9484	356	0	0
T17	788116	76128	0	0
T18	5876	356	0	0
T22	0	19280	0	0
T29	181148	20520	0	0
T32	0	11150	0	0
T58	520898	0	0	0
T71	0	12	0	0
T72	0	85716	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1533680772	1530316736	0	0
T1	4716	4328	0	0
T2	7452	7068	0	0
T3	49692	49340	0	0
T8	7744	7436	0	0
T13	14588	14208	0	0
T14	8836	8528	0	0
T15	6040	5820	0	0
T16	9484	9192	0	0
T17	788116	787756	0	0
T18	5876	5536	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1533680772	1530316736	0	0
T1	4716	4328	0	0
T2	7452	7068	0	0
T3	49692	49340	0	0
T8	7744	7436	0	0
T13	14588	14208	0	0
T14	8836	8528	0	0
T15	6040	5820	0	0
T16	9484	9192	0	0
T17	788116	787756	0	0
T18	5876	5536	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1533680772	399442084	0	0
T1	2358	84	0	0
T2	3726	1178	0	0
T3	49692	1998	0	0
T8	7744	788	0	0
T9	0	47160	0	0
T13	14588	4444	0	0
T14	8836	356	0	0
T15	6040	584	0	0
T16	9484	356	0	0
T17	788116	76128	0	0
T18	5876	356	0	0
T22	0	19280	0	0
T29	181148	20520	0	0
T32	0	11150	0	0
T58	520898	0	0	0
T71	0	12	0	0
T72	0	85716	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1533680772	171479178	0	0
T1	2358	286	0	0
T2	3726	316	0	0
T3	49692	3110	0	0
T8	7744	314	0	0
T9	0	1442	0	0
T13	14588	256	0	0
T14	8836	694	0	0
T15	6040	256	0	0
T16	9484	986	0	0
T17	788116	7576	0	0
T18	5876	992	0	0
T22	0	23894	0	0
T29	181148	80	0	0
T32	0	3368	0	0
T34	0	66	0	0
T35	0	56	0	0
T50	0	54770	0	0
T58	520898	0	0	0

Priority_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1533680772	423460234	0	0
T1	2358	84	0	0
T2	3726	1178	0	0
T3	49692	2004	0	0
T8	7744	788	0	0
T9	0	47160	0	0
T13	14588	4444	0	0
T14	8836	356	0	0
T15	6040	584	0	0
T16	9484	356	0	0
T17	788116	76128	0	0
T18	5876	356	0	0
T22	0	34054	0	0
T29	181148	20520	0	0
T32	0	11150	0	0
T58	520898	0	0	0
T71	0	12	0	0
T72	0	85716	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1533680772	399442084	0	0
T1	2358	84	0	0
T2	3726	1178	0	0
T3	49692	1998	0	0
T8	7744	788	0	0
T9	0	47160	0	0
T13	14588	4444	0	0
T14	8836	356	0	0
T15	6040	584	0	0
T16	9484	356	0	0
T17	788116	76128	0	0
T18	5876	356	0	0
T22	0	19280	0	0
T29	181148	20520	0	0
T32	0	11150	0	0
T58	520898	0	0	0
T71	0	12	0	0
T72	0	85716	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1533680772	399442084	0	0
T1	2358	84	0	0
T2	3726	1178	0	0
T3	49692	1998	0	0
T8	7744	788	0	0
T9	0	47160	0	0
T13	14588	4444	0	0
T14	8836	356	0	0
T15	6040	584	0	0
T16	9484	356	0	0
T17	788116	76128	0	0
T18	5876	356	0	0
T22	0	19280	0	0
T29	181148	20520	0	0
T32	0	11150	0	0
T58	520898	0	0	0
T71	0	12	0	0
T72	0	85716	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1533680772	423460234	0	0
T1	2358	84	0	0
T2	3726	1178	0	0
T3	49692	2004	0	0
T8	7744	788	0	0
T9	0	47160	0	0
T13	14588	4444	0	0
T14	8836	356	0	0
T15	6040	584	0	0
T16	9484	356	0	0
T17	788116	76128	0	0
T18	5876	356	0	0
T22	0	34054	0	0
T29	181148	20520	0	0
T32	0	11150	0	0
T58	520898	0	0	0
T71	0	12	0	0
T72	0	85716	0	0

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1533680772	1530316736	0	0
T1	4716	4328	0	0
T2	7452	7068	0	0
T3	49692	49340	0	0
T8	7744	7436	0	0
T13	14588	14208	0	0
T14	8836	8528	0	0
T15	6040	5820	0	0
T16	9484	9192	0	0
T17	788116	787756	0	0
T18	5876	5536	0	0

Line Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_host_arb.gen_input_bufs[0].gen_fixed_arbiter.u_arb

	Line No.	Total	Covered	Percent
TOTAL		16	14	87.50
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	87	1	0	0.00
CONT_ASSIGN	87	1	0	0.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	89	1	1	100.00
ALWAYS	105	6	6	100.00
CONT_ASSIGN	124	1	1	100.00
CONT_ASSIGN	128	1	1	100.00
CONT_ASSIGN	129	1	1	100.00
CONT_ASSIGN	132	1	1	100.00

84                                  // forward path
85         2/2                      assign req_tree[Pa]      = req_i[offset];
           Tests:       T1 T2 T3  | T1 T2 T3 
86                                  assign idx_tree[Pa]      = offset;
87         0/2     ==>              assign data_tree[Pa]     = data_i[offset];
88                                  // backward (grant) path
89         2/2                      assign gnt_o[offset]     = gnt_tree[Pa];
           Tests:       T1 T2 T3  | T1 T2 T3 
90                      
91                                end else begin : gen_tie_off
92                                  // forward path
93                                  assign req_tree[Pa]  = '0;
94                                  assign idx_tree[Pa]  = '0;
95                                  assign data_tree[Pa] = '0;
96                                  logic unused_sigs;
97                                  assign unused_sigs = gnt_tree[Pa];
98                                end
99                              // this creates the node assignments
100                             end else begin : gen_nodes
101                               // forward path
102                               logic sel; // local helper variable
103                               always_comb begin : p_node
104                                 // this always gives priority to the left child
105        1/1                      sel = ~req_tree[C0];
           Tests:       T1 T2 T3 
106                                 // propagate requests
107        1/1                      req_tree[Pa]  = req_tree[C0] | req_tree[C1];
           Tests:       T1 T2 T3 
108                                 // data and index muxes
109        1/1                      idx_tree[Pa]  = (sel) ? idx_tree[C1]  : idx_tree[C0];
           Tests:       T1 T2 T3 
110        1/1                      data_tree[Pa] = (sel) ? data_tree[C1] : data_tree[C0];
           Tests:       T1 T2 T3 
111                                 // propagate the grants back to the input
112        1/1                      gnt_tree[C0] = gnt_tree[Pa] & ~sel;
           Tests:       T1 T2 T3 
113        1/1                      gnt_tree[C1] = gnt_tree[Pa] &  sel;
           Tests:       T1 T2 T3 
114                               end
115                             end
116                           end : gen_level
117                         end : gen_tree
118                     
119                         // the results can be found at the tree root
120                         if (EnDataPort) begin : gen_data_port
121                           assign data_o      = data_tree[0];
122                         end else begin : gen_no_dataport
123                           logic [DW-1:0] unused_data;
124        1/1                assign unused_data = data_tree[0];
           Tests:       T1 T2 T8 
125                           assign data_o = '1;
126                         end
127                     
128        1/1              assign idx_o       = idx_tree[0];
           Tests:       T1 T2 T3 
129        1/1              assign valid_o     = req_tree[0];
           Tests:       T1 T2 T3 
130                     
131                         // this propagates a grant back to the input
132        1/1              assign gnt_tree[0] = valid_o & ready_i;
           Tests:       T1 T2 T3 

---

Cond Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_host_arb.gen_input_bufs[0].gen_fixed_arbiter.u_arb

	Total	Covered	Percent
Conditions	16	16	100.00
Logical	16	16	100.00
Non-Logical	0	0
Event	0	0

 LINE       107
 EXPRESSION (gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C0] | gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C1])
             ----------------------------------1----------------------------------   ----------------------------------2----------------------------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T3,T8

 LINE       109
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])

-1-	Status	Tests
0	Covered	T1,T3,T8
1	Covered	T1,T2,T3

 LINE       110
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])

-1-	Status	Tests
0	Covered	T1,T3,T8
1	Covered	T1,T2,T3

 LINE       112
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & ((~gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)))
             ----------------------------------1----------------------------------   -----------------------------2-----------------------------

-1-	-2-	Status	Tests
0	1	Covered	T3,T9,T22
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T3,T8

 LINE       113
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)
             ----------------------------------1----------------------------------   ---------------------------2--------------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T3,T8
1	1	Covered	T1,T2,T3

 LINE       132
 EXPRESSION (valid_o & ready_i)
             ---1---   ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T3,T9,T22
1	1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_host_arb.gen_input_bufs[0].gen_fixed_arbiter.u_arb

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
TERNARY	109	2	2	100.00
TERNARY	110	2	2	100.00

109                    idx_tree[Pa]  = (sel) ? idx_tree[C1]  : idx_tree[C0];
                                             -1-  
                                             ==>  
                                             ==>  

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T3,T8

110                    data_tree[Pa] = (sel) ? data_tree[C1] : data_tree[C0];
                                             -1-  
                                             ==>  
                                             ==>  

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T3,T8

---

Assert Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_host_arb.gen_input_bufs[0].gen_fixed_arbiter.u_arb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	13	13	100.00	13	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	13	13	100.00	13	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	383420193	382579184	0	0
CheckNGreaterZero_A	1058	1058	0	0
GntImpliesReady_A	383420193	103058591	0	0
GntImpliesValid_A	383420193	103058591	0	0
GrantKnown_A	383420193	382579184	0	0
IdxKnown_A	383420193	382579184	0	0
IndexIsCorrect_A	383420193	103058591	0	0
NoReadyValidNoGrant_A	383420193	44111326	0	0
Priority_A	383420193	109177982	0	0
ReadyAndValidImplyGrant_A	383420193	103058591	0	0
ReqAndReadyImplyGrant_A	383420193	103058591	0	0
ReqImpliesValid_A	383420193	109177982	0	0
ValidKnown_A	383420193	382579184	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	383420193	382579184	0	0
T1	1179	1082	0	0
T2	1863	1767	0	0
T3	12423	12335	0	0
T8	1936	1859	0	0
T13	3647	3552	0	0
T14	2209	2132	0	0
T15	1510	1455	0	0
T16	2371	2298	0	0
T17	197029	196939	0	0
T18	1469	1384	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1058	1058	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T8	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	383420193	103058591	0	0
T1	1179	42	0	0
T2	1863	589	0	0
T3	12423	485	0	0
T8	1936	394	0	0
T13	3647	2222	0	0
T14	2209	178	0	0
T15	1510	32	0	0
T16	2371	178	0	0
T17	197029	17929	0	0
T18	1469	32	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	383420193	103058591	0	0
T1	1179	42	0	0
T2	1863	589	0	0
T3	12423	485	0	0
T8	1936	394	0	0
T13	3647	2222	0	0
T14	2209	178	0	0
T15	1510	32	0	0
T16	2371	178	0	0
T17	197029	17929	0	0
T18	1469	32	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	383420193	382579184	0	0
T1	1179	1082	0	0
T2	1863	1767	0	0
T3	12423	12335	0	0
T8	1936	1859	0	0
T13	3647	3552	0	0
T14	2209	2132	0	0
T15	1510	1455	0	0
T16	2371	2298	0	0
T17	197029	196939	0	0
T18	1469	1384	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	383420193	382579184	0	0
T1	1179	1082	0	0
T2	1863	1767	0	0
T3	12423	12335	0	0
T8	1936	1859	0	0
T13	3647	3552	0	0
T14	2209	2132	0	0
T15	1510	1455	0	0
T16	2371	2298	0	0
T17	197029	196939	0	0
T18	1469	1384	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	383420193	103058591	0	0
T1	1179	42	0	0
T2	1863	589	0	0
T3	12423	485	0	0
T8	1936	394	0	0
T13	3647	2222	0	0
T14	2209	178	0	0
T15	1510	32	0	0
T16	2371	178	0	0
T17	197029	17929	0	0
T18	1469	32	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	383420193	44111326	0	0
T1	1179	143	0	0
T2	1863	158	0	0
T3	12423	794	0	0
T8	1936	157	0	0
T13	3647	128	0	0
T14	2209	347	0	0
T15	1510	128	0	0
T16	2371	493	0	0
T17	197029	1856	0	0
T18	1469	128	0	0

Priority_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	383420193	109177982	0	0
T1	1179	42	0	0
T2	1863	589	0	0
T3	12423	487	0	0
T8	1936	394	0	0
T13	3647	2222	0	0
T14	2209	178	0	0
T15	1510	32	0	0
T16	2371	178	0	0
T17	197029	17929	0	0
T18	1469	32	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	383420193	103058591	0	0
T1	1179	42	0	0
T2	1863	589	0	0
T3	12423	485	0	0
T8	1936	394	0	0
T13	3647	2222	0	0
T14	2209	178	0	0
T15	1510	32	0	0
T16	2371	178	0	0
T17	197029	17929	0	0
T18	1469	32	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	383420193	103058591	0	0
T1	1179	42	0	0
T2	1863	589	0	0
T3	12423	485	0	0
T8	1936	394	0	0
T13	3647	2222	0	0
T14	2209	178	0	0
T15	1510	32	0	0
T16	2371	178	0	0
T17	197029	17929	0	0
T18	1469	32	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	383420193	109177982	0	0
T1	1179	42	0	0
T2	1863	589	0	0
T3	12423	487	0	0
T8	1936	394	0	0
T13	3647	2222	0	0
T14	2209	178	0	0
T15	1510	32	0	0
T16	2371	178	0	0
T17	197029	17929	0	0
T18	1469	32	0	0

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	383420193	382579184	0	0
T1	1179	1082	0	0
T2	1863	1767	0	0
T3	12423	12335	0	0
T8	1936	1859	0	0
T13	3647	3552	0	0
T14	2209	2132	0	0
T15	1510	1455	0	0
T16	2371	2298	0	0
T17	197029	196939	0	0
T18	1469	1384	0	0

Line Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_host_arb.gen_input_bufs[1].gen_fixed_arbiter.u_arb

	Line No.	Total	Covered	Percent
TOTAL		16	14	87.50
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	87	1	0	0.00
CONT_ASSIGN	87	1	0	0.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	89	1	1	100.00
ALWAYS	105	6	6	100.00
CONT_ASSIGN	124	1	1	100.00
CONT_ASSIGN	128	1	1	100.00
CONT_ASSIGN	129	1	1	100.00
CONT_ASSIGN	132	1	1	100.00

84                                  // forward path
85         2/2                      assign req_tree[Pa]      = req_i[offset];
           Tests:       T1 T2 T3  | T1 T2 T3 
86                                  assign idx_tree[Pa]      = offset;
87         0/2     ==>              assign data_tree[Pa]     = data_i[offset];
88                                  // backward (grant) path
89         2/2                      assign gnt_o[offset]     = gnt_tree[Pa];
           Tests:       T1 T2 T3  | T1 T2 T3 
90                      
91                                end else begin : gen_tie_off
92                                  // forward path
93                                  assign req_tree[Pa]  = '0;
94                                  assign idx_tree[Pa]  = '0;
95                                  assign data_tree[Pa] = '0;
96                                  logic unused_sigs;
97                                  assign unused_sigs = gnt_tree[Pa];
98                                end
99                              // this creates the node assignments
100                             end else begin : gen_nodes
101                               // forward path
102                               logic sel; // local helper variable
103                               always_comb begin : p_node
104                                 // this always gives priority to the left child
105        1/1                      sel = ~req_tree[C0];
           Tests:       T1 T2 T3 
106                                 // propagate requests
107        1/1                      req_tree[Pa]  = req_tree[C0] | req_tree[C1];
           Tests:       T1 T2 T3 
108                                 // data and index muxes
109        1/1                      idx_tree[Pa]  = (sel) ? idx_tree[C1]  : idx_tree[C0];
           Tests:       T1 T2 T3 
110        1/1                      data_tree[Pa] = (sel) ? data_tree[C1] : data_tree[C0];
           Tests:       T1 T2 T3 
111                                 // propagate the grants back to the input
112        1/1                      gnt_tree[C0] = gnt_tree[Pa] & ~sel;
           Tests:       T1 T2 T3 
113        1/1                      gnt_tree[C1] = gnt_tree[Pa] &  sel;
           Tests:       T1 T2 T3 
114                               end
115                             end
116                           end : gen_level
117                         end : gen_tree
118                     
119                         // the results can be found at the tree root
120                         if (EnDataPort) begin : gen_data_port
121                           assign data_o      = data_tree[0];
122                         end else begin : gen_no_dataport
123                           logic [DW-1:0] unused_data;
124        1/1                assign unused_data = data_tree[0];
           Tests:       T1 T2 T8 
125                           assign data_o = '1;
126                         end
127                     
128        1/1              assign idx_o       = idx_tree[0];
           Tests:       T1 T2 T3 
129        1/1              assign valid_o     = req_tree[0];
           Tests:       T1 T2 T3 
130                     
131                         // this propagates a grant back to the input
132        1/1              assign gnt_tree[0] = valid_o & ready_i;
           Tests:       T1 T2 T3 

---

Cond Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_host_arb.gen_input_bufs[1].gen_fixed_arbiter.u_arb

	Total	Covered	Percent
Conditions	16	16	100.00
Logical	16	16	100.00
Non-Logical	0	0
Event	0	0

 LINE       107
 EXPRESSION (gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C0] | gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C1])
             ----------------------------------1----------------------------------   ----------------------------------2----------------------------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T3,T8

 LINE       109
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])

-1-	Status	Tests
0	Covered	T1,T3,T8
1	Covered	T1,T2,T3

 LINE       110
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])

-1-	Status	Tests
0	Covered	T1,T3,T8
1	Covered	T1,T2,T3

 LINE       112
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & ((~gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)))
             ----------------------------------1----------------------------------   -----------------------------2-----------------------------

-1-	-2-	Status	Tests
0	1	Covered	T3,T9,T22
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T3,T8

 LINE       113
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)
             ----------------------------------1----------------------------------   ---------------------------2--------------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T3,T8
1	1	Covered	T1,T2,T3

 LINE       132
 EXPRESSION (valid_o & ready_i)
             ---1---   ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T3,T9,T22
1	1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_host_arb.gen_input_bufs[1].gen_fixed_arbiter.u_arb

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
TERNARY	109	2	2	100.00
TERNARY	110	2	2	100.00

109                    idx_tree[Pa]  = (sel) ? idx_tree[C1]  : idx_tree[C0];
                                             -1-  
                                             ==>  
                                             ==>  

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T3,T8

110                    data_tree[Pa] = (sel) ? data_tree[C1] : data_tree[C0];
                                             -1-  
                                             ==>  
                                             ==>  

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T3,T8

---

Assert Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_host_arb.gen_input_bufs[1].gen_fixed_arbiter.u_arb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	13	13	100.00	13	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	13	13	100.00	13	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	383420193	382579184	0	0
CheckNGreaterZero_A	1058	1058	0	0
GntImpliesReady_A	383420193	103058528	0	0
GntImpliesValid_A	383420193	103058528	0	0
GrantKnown_A	383420193	382579184	0	0
IdxKnown_A	383420193	382579184	0	0
IndexIsCorrect_A	383420193	103058528	0	0
NoReadyValidNoGrant_A	383420193	44111326	0	0
Priority_A	383420193	109177919	0	0
ReadyAndValidImplyGrant_A	383420193	103058528	0	0
ReqAndReadyImplyGrant_A	383420193	103058528	0	0
ReqImpliesValid_A	383420193	109177919	0	0
ValidKnown_A	383420193	382579184	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	383420193	382579184	0	0
T1	1179	1082	0	0
T2	1863	1767	0	0
T3	12423	12335	0	0
T8	1936	1859	0	0
T13	3647	3552	0	0
T14	2209	2132	0	0
T15	1510	1455	0	0
T16	2371	2298	0	0
T17	197029	196939	0	0
T18	1469	1384	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1058	1058	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T8	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	383420193	103058528	0	0
T1	1179	42	0	0
T2	1863	589	0	0
T3	12423	485	0	0
T8	1936	394	0	0
T13	3647	2222	0	0
T14	2209	178	0	0
T15	1510	32	0	0
T16	2371	178	0	0
T17	197029	17929	0	0
T18	1469	32	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	383420193	103058528	0	0
T1	1179	42	0	0
T2	1863	589	0	0
T3	12423	485	0	0
T8	1936	394	0	0
T13	3647	2222	0	0
T14	2209	178	0	0
T15	1510	32	0	0
T16	2371	178	0	0
T17	197029	17929	0	0
T18	1469	32	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	383420193	382579184	0	0
T1	1179	1082	0	0
T2	1863	1767	0	0
T3	12423	12335	0	0
T8	1936	1859	0	0
T13	3647	3552	0	0
T14	2209	2132	0	0
T15	1510	1455	0	0
T16	2371	2298	0	0
T17	197029	196939	0	0
T18	1469	1384	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	383420193	382579184	0	0
T1	1179	1082	0	0
T2	1863	1767	0	0
T3	12423	12335	0	0
T8	1936	1859	0	0
T13	3647	3552	0	0
T14	2209	2132	0	0
T15	1510	1455	0	0
T16	2371	2298	0	0
T17	197029	196939	0	0
T18	1469	1384	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	383420193	103058528	0	0
T1	1179	42	0	0
T2	1863	589	0	0
T3	12423	485	0	0
T8	1936	394	0	0
T13	3647	2222	0	0
T14	2209	178	0	0
T15	1510	32	0	0
T16	2371	178	0	0
T17	197029	17929	0	0
T18	1469	32	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	383420193	44111326	0	0
T1	1179	143	0	0
T2	1863	158	0	0
T3	12423	794	0	0
T8	1936	157	0	0
T13	3647	128	0	0
T14	2209	347	0	0
T15	1510	128	0	0
T16	2371	493	0	0
T17	197029	1856	0	0
T18	1469	128	0	0

Priority_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	383420193	109177919	0	0
T1	1179	42	0	0
T2	1863	589	0	0
T3	12423	487	0	0
T8	1936	394	0	0
T13	3647	2222	0	0
T14	2209	178	0	0
T15	1510	32	0	0
T16	2371	178	0	0
T17	197029	17929	0	0
T18	1469	32	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	383420193	103058528	0	0
T1	1179	42	0	0
T2	1863	589	0	0
T3	12423	485	0	0
T8	1936	394	0	0
T13	3647	2222	0	0
T14	2209	178	0	0
T15	1510	32	0	0
T16	2371	178	0	0
T17	197029	17929	0	0
T18	1469	32	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	383420193	103058528	0	0
T1	1179	42	0	0
T2	1863	589	0	0
T3	12423	485	0	0
T8	1936	394	0	0
T13	3647	2222	0	0
T14	2209	178	0	0
T15	1510	32	0	0
T16	2371	178	0	0
T17	197029	17929	0	0
T18	1469	32	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	383420193	109177919	0	0
T1	1179	42	0	0
T2	1863	589	0	0
T3	12423	487	0	0
T8	1936	394	0	0
T13	3647	2222	0	0
T14	2209	178	0	0
T15	1510	32	0	0
T16	2371	178	0	0
T17	197029	17929	0	0
T18	1469	32	0	0

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	383420193	382579184	0	0
T1	1179	1082	0	0
T2	1863	1767	0	0
T3	12423	12335	0	0
T8	1936	1859	0	0
T13	3647	3552	0	0
T14	2209	2132	0	0
T15	1510	1455	0	0
T16	2371	2298	0	0
T17	197029	196939	0	0
T18	1469	1384	0	0

Line Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_host_arb.gen_input_bufs[0].gen_fixed_arbiter.u_arb

	Line No.	Total	Covered	Percent
TOTAL		16	14	87.50
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	87	1	0	0.00
CONT_ASSIGN	87	1	0	0.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	89	1	1	100.00
ALWAYS	105	6	6	100.00
CONT_ASSIGN	124	1	1	100.00
CONT_ASSIGN	128	1	1	100.00
CONT_ASSIGN	129	1	1	100.00
CONT_ASSIGN	132	1	1	100.00

84                                  // forward path
85         2/2                      assign req_tree[Pa]      = req_i[offset];
           Tests:       T1 T2 T3  | T1 T2 T3 
86                                  assign idx_tree[Pa]      = offset;
87         0/2     ==>              assign data_tree[Pa]     = data_i[offset];
88                                  // backward (grant) path
89         2/2                      assign gnt_o[offset]     = gnt_tree[Pa];
           Tests:       T1 T2 T3  | T1 T2 T3 
90                      
91                                end else begin : gen_tie_off
92                                  // forward path
93                                  assign req_tree[Pa]  = '0;
94                                  assign idx_tree[Pa]  = '0;
95                                  assign data_tree[Pa] = '0;
96                                  logic unused_sigs;
97                                  assign unused_sigs = gnt_tree[Pa];
98                                end
99                              // this creates the node assignments
100                             end else begin : gen_nodes
101                               // forward path
102                               logic sel; // local helper variable
103                               always_comb begin : p_node
104                                 // this always gives priority to the left child
105        1/1                      sel = ~req_tree[C0];
           Tests:       T1 T2 T3 
106                                 // propagate requests
107        1/1                      req_tree[Pa]  = req_tree[C0] | req_tree[C1];
           Tests:       T1 T2 T3 
108                                 // data and index muxes
109        1/1                      idx_tree[Pa]  = (sel) ? idx_tree[C1]  : idx_tree[C0];
           Tests:       T1 T2 T3 
110        1/1                      data_tree[Pa] = (sel) ? data_tree[C1] : data_tree[C0];
           Tests:       T1 T2 T3 
111                                 // propagate the grants back to the input
112        1/1                      gnt_tree[C0] = gnt_tree[Pa] & ~sel;
           Tests:       T1 T2 T3 
113        1/1                      gnt_tree[C1] = gnt_tree[Pa] &  sel;
           Tests:       T1 T2 T3 
114                               end
115                             end
116                           end : gen_level
117                         end : gen_tree
118                     
119                         // the results can be found at the tree root
120                         if (EnDataPort) begin : gen_data_port
121                           assign data_o      = data_tree[0];
122                         end else begin : gen_no_dataport
123                           logic [DW-1:0] unused_data;
124        1/1                assign unused_data = data_tree[0];
           Tests:       T1 T2 T8 
125                           assign data_o = '1;
126                         end
127                     
128        1/1              assign idx_o       = idx_tree[0];
           Tests:       T1 T2 T3 
129        1/1              assign valid_o     = req_tree[0];
           Tests:       T1 T2 T3 
130                     
131                         // this propagates a grant back to the input
132        1/1              assign gnt_tree[0] = valid_o & ready_i;
           Tests:       T1 T2 T3 

---

Cond Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_host_arb.gen_input_bufs[0].gen_fixed_arbiter.u_arb

	Total	Covered	Percent
Conditions	16	16	100.00
Logical	16	16	100.00
Non-Logical	0	0
Event	0	0

 LINE       107
 EXPRESSION (gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C0] | gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C1])
             ----------------------------------1----------------------------------   ----------------------------------2----------------------------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T3,T15,T17
1	0	Covered	T3,T9,T22

 LINE       109
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])

-1-	Status	Tests
0	Covered	T3,T9,T22
1	Covered	T1,T2,T3

 LINE       110
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])

-1-	Status	Tests
0	Covered	T3,T9,T22
1	Covered	T1,T2,T3

 LINE       112
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & ((~gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)))
             ----------------------------------1----------------------------------   -----------------------------2-----------------------------

-1-	-2-	Status	Tests
0	1	Covered	T3,T9,T22
1	0	Covered	T3,T15,T17
1	1	Covered	T3,T9,T22

 LINE       113
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)
             ----------------------------------1----------------------------------   ---------------------------2--------------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T3,T9,T22
1	1	Covered	T3,T15,T17

 LINE       132
 EXPRESSION (valid_o & ready_i)
             ---1---   ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T3,T9,T22
1	1	Covered	T3,T15,T17

---

Branch Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_host_arb.gen_input_bufs[0].gen_fixed_arbiter.u_arb

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
TERNARY	109	2	2	100.00
TERNARY	110	2	2	100.00

109                    idx_tree[Pa]  = (sel) ? idx_tree[C1]  : idx_tree[C0];
                                             -1-  
                                             ==>  
                                             ==>  

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T3,T9,T22

110                    data_tree[Pa] = (sel) ? data_tree[C1] : data_tree[C0];
                                             -1-  
                                             ==>  
                                             ==>  

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T3,T9,T22

---

Assert Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_host_arb.gen_input_bufs[0].gen_fixed_arbiter.u_arb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	13	13	100.00	13	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	13	13	100.00	13	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	383420193	382579184	0	0
CheckNGreaterZero_A	1058	1058	0	0
GntImpliesReady_A	383420193	96662454	0	0
GntImpliesValid_A	383420193	96662454	0	0
GrantKnown_A	383420193	382579184	0	0
IdxKnown_A	383420193	382579184	0	0
IndexIsCorrect_A	383420193	96662454	0	0
NoReadyValidNoGrant_A	383420193	41628267	0	0
Priority_A	383420193	102552134	0	0
ReadyAndValidImplyGrant_A	383420193	96662454	0	0
ReqAndReadyImplyGrant_A	383420193	96662454	0	0
ReqImpliesValid_A	383420193	102552134	0	0
ValidKnown_A	383420193	382579184	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	383420193	382579184	0	0
T1	1179	1082	0	0
T2	1863	1767	0	0
T3	12423	12335	0	0
T8	1936	1859	0	0
T13	3647	3552	0	0
T14	2209	2132	0	0
T15	1510	1455	0	0
T16	2371	2298	0	0
T17	197029	196939	0	0
T18	1469	1384	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1058	1058	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T8	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	383420193	96662454	0	0
T3	12423	514	0	0
T8	1936	0	0	0
T9	0	23580	0	0
T13	3647	0	0	0
T14	2209	0	0	0
T15	1510	260	0	0
T16	2371	0	0	0
T17	197029	20135	0	0
T18	1469	146	0	0
T22	0	9640	0	0
T29	90574	10260	0	0
T32	0	5575	0	0
T58	260449	0	0	0
T71	0	6	0	0
T72	0	42858	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	383420193	96662454	0	0
T3	12423	514	0	0
T8	1936	0	0	0
T9	0	23580	0	0
T13	3647	0	0	0
T14	2209	0	0	0
T15	1510	260	0	0
T16	2371	0	0	0
T17	197029	20135	0	0
T18	1469	146	0	0
T22	0	9640	0	0
T29	90574	10260	0	0
T32	0	5575	0	0
T58	260449	0	0	0
T71	0	6	0	0
T72	0	42858	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	383420193	382579184	0	0
T1	1179	1082	0	0
T2	1863	1767	0	0
T3	12423	12335	0	0
T8	1936	1859	0	0
T13	3647	3552	0	0
T14	2209	2132	0	0
T15	1510	1455	0	0
T16	2371	2298	0	0
T17	197029	196939	0	0
T18	1469	1384	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	383420193	382579184	0	0
T1	1179	1082	0	0
T2	1863	1767	0	0
T3	12423	12335	0	0
T8	1936	1859	0	0
T13	3647	3552	0	0
T14	2209	2132	0	0
T15	1510	1455	0	0
T16	2371	2298	0	0
T17	197029	196939	0	0
T18	1469	1384	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	383420193	96662454	0	0
T3	12423	514	0	0
T8	1936	0	0	0
T9	0	23580	0	0
T13	3647	0	0	0
T14	2209	0	0	0
T15	1510	260	0	0
T16	2371	0	0	0
T17	197029	20135	0	0
T18	1469	146	0	0
T22	0	9640	0	0
T29	90574	10260	0	0
T32	0	5575	0	0
T58	260449	0	0	0
T71	0	6	0	0
T72	0	42858	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	383420193	41628267	0	0
T3	12423	761	0	0
T8	1936	0	0	0
T9	0	721	0	0
T13	3647	0	0	0
T14	2209	0	0	0
T15	1510	0	0	0
T16	2371	0	0	0
T17	197029	1932	0	0
T18	1469	368	0	0
T22	0	11947	0	0
T29	90574	40	0	0
T32	0	1684	0	0
T34	0	33	0	0
T35	0	28	0	0
T50	0	27385	0	0
T58	260449	0	0	0

Priority_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	383420193	102552134	0	0
T3	12423	515	0	0
T8	1936	0	0	0
T9	0	23580	0	0
T13	3647	0	0	0
T14	2209	0	0	0
T15	1510	260	0	0
T16	2371	0	0	0
T17	197029	20135	0	0
T18	1469	146	0	0
T22	0	17027	0	0
T29	90574	10260	0	0
T32	0	5575	0	0
T58	260449	0	0	0
T71	0	6	0	0
T72	0	42858	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	383420193	96662454	0	0
T3	12423	514	0	0
T8	1936	0	0	0
T9	0	23580	0	0
T13	3647	0	0	0
T14	2209	0	0	0
T15	1510	260	0	0
T16	2371	0	0	0
T17	197029	20135	0	0
T18	1469	146	0	0
T22	0	9640	0	0
T29	90574	10260	0	0
T32	0	5575	0	0
T58	260449	0	0	0
T71	0	6	0	0
T72	0	42858	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	383420193	96662454	0	0
T3	12423	514	0	0
T8	1936	0	0	0
T9	0	23580	0	0
T13	3647	0	0	0
T14	2209	0	0	0
T15	1510	260	0	0
T16	2371	0	0	0
T17	197029	20135	0	0
T18	1469	146	0	0
T22	0	9640	0	0
T29	90574	10260	0	0
T32	0	5575	0	0
T58	260449	0	0	0
T71	0	6	0	0
T72	0	42858	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	383420193	102552134	0	0
T3	12423	515	0	0
T8	1936	0	0	0
T9	0	23580	0	0
T13	3647	0	0	0
T14	2209	0	0	0
T15	1510	260	0	0
T16	2371	0	0	0
T17	197029	20135	0	0
T18	1469	146	0	0
T22	0	17027	0	0
T29	90574	10260	0	0
T32	0	5575	0	0
T58	260449	0	0	0
T71	0	6	0	0
T72	0	42858	0	0

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	383420193	382579184	0	0
T1	1179	1082	0	0
T2	1863	1767	0	0
T3	12423	12335	0	0
T8	1936	1859	0	0
T13	3647	3552	0	0
T14	2209	2132	0	0
T15	1510	1455	0	0
T16	2371	2298	0	0
T17	197029	196939	0	0
T18	1469	1384	0	0

Line Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_host_arb.gen_input_bufs[1].gen_fixed_arbiter.u_arb

	Line No.	Total	Covered	Percent
TOTAL		16	14	87.50
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	87	1	0	0.00
CONT_ASSIGN	87	1	0	0.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	89	1	1	100.00
ALWAYS	105	6	6	100.00
CONT_ASSIGN	124	1	1	100.00
CONT_ASSIGN	128	1	1	100.00
CONT_ASSIGN	129	1	1	100.00
CONT_ASSIGN	132	1	1	100.00

84                                  // forward path
85         2/2                      assign req_tree[Pa]      = req_i[offset];
           Tests:       T1 T2 T3  | T1 T2 T3 
86                                  assign idx_tree[Pa]      = offset;
87         0/2     ==>              assign data_tree[Pa]     = data_i[offset];
88                                  // backward (grant) path
89         2/2                      assign gnt_o[offset]     = gnt_tree[Pa];
           Tests:       T1 T2 T3  | T1 T2 T3 
90                      
91                                end else begin : gen_tie_off
92                                  // forward path
93                                  assign req_tree[Pa]  = '0;
94                                  assign idx_tree[Pa]  = '0;
95                                  assign data_tree[Pa] = '0;
96                                  logic unused_sigs;
97                                  assign unused_sigs = gnt_tree[Pa];
98                                end
99                              // this creates the node assignments
100                             end else begin : gen_nodes
101                               // forward path
102                               logic sel; // local helper variable
103                               always_comb begin : p_node
104                                 // this always gives priority to the left child
105        1/1                      sel = ~req_tree[C0];
           Tests:       T1 T2 T3 
106                                 // propagate requests
107        1/1                      req_tree[Pa]  = req_tree[C0] | req_tree[C1];
           Tests:       T1 T2 T3 
108                                 // data and index muxes
109        1/1                      idx_tree[Pa]  = (sel) ? idx_tree[C1]  : idx_tree[C0];
           Tests:       T1 T2 T3 
110        1/1                      data_tree[Pa] = (sel) ? data_tree[C1] : data_tree[C0];
           Tests:       T1 T2 T3 
111                                 // propagate the grants back to the input
112        1/1                      gnt_tree[C0] = gnt_tree[Pa] & ~sel;
           Tests:       T1 T2 T3 
113        1/1                      gnt_tree[C1] = gnt_tree[Pa] &  sel;
           Tests:       T1 T2 T3 
114                               end
115                             end
116                           end : gen_level
117                         end : gen_tree
118                     
119                         // the results can be found at the tree root
120                         if (EnDataPort) begin : gen_data_port
121                           assign data_o      = data_tree[0];
122                         end else begin : gen_no_dataport
123                           logic [DW-1:0] unused_data;
124        1/1                assign unused_data = data_tree[0];
           Tests:       T1 T2 T8 
125                           assign data_o = '1;
126                         end
127                     
128        1/1              assign idx_o       = idx_tree[0];
           Tests:       T1 T2 T3 
129        1/1              assign valid_o     = req_tree[0];
           Tests:       T1 T2 T3 
130                     
131                         // this propagates a grant back to the input
132        1/1              assign gnt_tree[0] = valid_o & ready_i;
           Tests:       T1 T2 T3 

---

Cond Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_host_arb.gen_input_bufs[1].gen_fixed_arbiter.u_arb

	Total	Covered	Percent
Conditions	16	16	100.00
Logical	16	16	100.00
Non-Logical	0	0
Event	0	0

 LINE       107
 EXPRESSION (gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C0] | gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C1])
             ----------------------------------1----------------------------------   ----------------------------------2----------------------------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T3,T15,T17
1	0	Covered	T3,T9,T22

 LINE       109
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])

-1-	Status	Tests
0	Covered	T3,T9,T22
1	Covered	T1,T2,T3

 LINE       110
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])

-1-	Status	Tests
0	Covered	T3,T9,T22
1	Covered	T1,T2,T3

 LINE       112
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & ((~gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)))
             ----------------------------------1----------------------------------   -----------------------------2-----------------------------

-1-	-2-	Status	Tests
0	1	Covered	T3,T9,T22
1	0	Covered	T3,T15,T17
1	1	Covered	T3,T9,T22

 LINE       113
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)
             ----------------------------------1----------------------------------   ---------------------------2--------------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T3,T9,T22
1	1	Covered	T3,T15,T17

 LINE       132
 EXPRESSION (valid_o & ready_i)
             ---1---   ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T3,T9,T22
1	1	Covered	T3,T15,T17

---

Branch Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_host_arb.gen_input_bufs[1].gen_fixed_arbiter.u_arb

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
TERNARY	109	2	2	100.00
TERNARY	110	2	2	100.00

109                    idx_tree[Pa]  = (sel) ? idx_tree[C1]  : idx_tree[C0];
                                             -1-  
                                             ==>  
                                             ==>  

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T3,T9,T22

110                    data_tree[Pa] = (sel) ? data_tree[C1] : data_tree[C0];
                                             -1-  
                                             ==>  
                                             ==>  

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T3,T9,T22

---

Assert Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_host_arb.gen_input_bufs[1].gen_fixed_arbiter.u_arb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	13	13	100.00	13	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	13	13	100.00	13	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	383420193	382579184	0	0
CheckNGreaterZero_A	1058	1058	0	0
GntImpliesReady_A	383420193	96662511	0	0
GntImpliesValid_A	383420193	96662511	0	0
GrantKnown_A	383420193	382579184	0	0
IdxKnown_A	383420193	382579184	0	0
IndexIsCorrect_A	383420193	96662511	0	0
NoReadyValidNoGrant_A	383420193	41628259	0	0
Priority_A	383420193	102552199	0	0
ReadyAndValidImplyGrant_A	383420193	96662511	0	0
ReqAndReadyImplyGrant_A	383420193	96662511	0	0
ReqImpliesValid_A	383420193	102552199	0	0
ValidKnown_A	383420193	382579184	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	383420193	382579184	0	0
T1	1179	1082	0	0
T2	1863	1767	0	0
T3	12423	12335	0	0
T8	1936	1859	0	0
T13	3647	3552	0	0
T14	2209	2132	0	0
T15	1510	1455	0	0
T16	2371	2298	0	0
T17	197029	196939	0	0
T18	1469	1384	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1058	1058	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T8	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	383420193	96662511	0	0
T3	12423	514	0	0
T8	1936	0	0	0
T9	0	23580	0	0
T13	3647	0	0	0
T14	2209	0	0	0
T15	1510	260	0	0
T16	2371	0	0	0
T17	197029	20135	0	0
T18	1469	146	0	0
T22	0	9640	0	0
T29	90574	10260	0	0
T32	0	5575	0	0
T58	260449	0	0	0
T71	0	6	0	0
T72	0	42858	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	383420193	96662511	0	0
T3	12423	514	0	0
T8	1936	0	0	0
T9	0	23580	0	0
T13	3647	0	0	0
T14	2209	0	0	0
T15	1510	260	0	0
T16	2371	0	0	0
T17	197029	20135	0	0
T18	1469	146	0	0
T22	0	9640	0	0
T29	90574	10260	0	0
T32	0	5575	0	0
T58	260449	0	0	0
T71	0	6	0	0
T72	0	42858	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	383420193	382579184	0	0
T1	1179	1082	0	0
T2	1863	1767	0	0
T3	12423	12335	0	0
T8	1936	1859	0	0
T13	3647	3552	0	0
T14	2209	2132	0	0
T15	1510	1455	0	0
T16	2371	2298	0	0
T17	197029	196939	0	0
T18	1469	1384	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	383420193	382579184	0	0
T1	1179	1082	0	0
T2	1863	1767	0	0
T3	12423	12335	0	0
T8	1936	1859	0	0
T13	3647	3552	0	0
T14	2209	2132	0	0
T15	1510	1455	0	0
T16	2371	2298	0	0
T17	197029	196939	0	0
T18	1469	1384	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	383420193	96662511	0	0
T3	12423	514	0	0
T8	1936	0	0	0
T9	0	23580	0	0
T13	3647	0	0	0
T14	2209	0	0	0
T15	1510	260	0	0
T16	2371	0	0	0
T17	197029	20135	0	0
T18	1469	146	0	0
T22	0	9640	0	0
T29	90574	10260	0	0
T32	0	5575	0	0
T58	260449	0	0	0
T71	0	6	0	0
T72	0	42858	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	383420193	41628259	0	0
T3	12423	761	0	0
T8	1936	0	0	0
T9	0	721	0	0
T13	3647	0	0	0
T14	2209	0	0	0
T15	1510	0	0	0
T16	2371	0	0	0
T17	197029	1932	0	0
T18	1469	368	0	0
T22	0	11947	0	0
T29	90574	40	0	0
T32	0	1684	0	0
T34	0	33	0	0
T35	0	28	0	0
T50	0	27385	0	0
T58	260449	0	0	0

Priority_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	383420193	102552199	0	0
T3	12423	515	0	0
T8	1936	0	0	0
T9	0	23580	0	0
T13	3647	0	0	0
T14	2209	0	0	0
T15	1510	260	0	0
T16	2371	0	0	0
T17	197029	20135	0	0
T18	1469	146	0	0
T22	0	17027	0	0
T29	90574	10260	0	0
T32	0	5575	0	0
T58	260449	0	0	0
T71	0	6	0	0
T72	0	42858	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	383420193	96662511	0	0
T3	12423	514	0	0
T8	1936	0	0	0
T9	0	23580	0	0
T13	3647	0	0	0
T14	2209	0	0	0
T15	1510	260	0	0
T16	2371	0	0	0
T17	197029	20135	0	0
T18	1469	146	0	0
T22	0	9640	0	0
T29	90574	10260	0	0
T32	0	5575	0	0
T58	260449	0	0	0
T71	0	6	0	0
T72	0	42858	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	383420193	96662511	0	0
T3	12423	514	0	0
T8	1936	0	0	0
T9	0	23580	0	0
T13	3647	0	0	0
T14	2209	0	0	0
T15	1510	260	0	0
T16	2371	0	0	0
T17	197029	20135	0	0
T18	1469	146	0	0
T22	0	9640	0	0
T29	90574	10260	0	0
T32	0	5575	0	0
T58	260449	0	0	0
T71	0	6	0	0
T72	0	42858	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	383420193	102552199	0	0
T3	12423	515	0	0
T8	1936	0	0	0
T9	0	23580	0	0
T13	3647	0	0	0
T14	2209	0	0	0
T15	1510	260	0	0
T16	2371	0	0	0
T17	197029	20135	0	0
T18	1469	146	0	0
T22	0	17027	0	0
T29	90574	10260	0	0
T32	0	5575	0	0
T58	260449	0	0	0
T71	0	6	0	0
T72	0	42858	0	0

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	383420193	382579184	0	0
T1	1179	1082	0	0
T2	1863	1767	0	0
T3	12423	12335	0	0
T8	1936	1859	0	0
T13	3647	3552	0	0
T14	2209	2132	0	0
T15	1510	1455	0	0
T16	2371	2298	0	0
T17	197029	196939	0	0
T18	1469	1384	0	0