Unified Coverage Report :: Module :: prim_arbiter_fixed

Module : prim_arbiter_fixed

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.88	87.50	100.00			100.00	100.00

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_09_10/flash_ctrl-sim-vcs/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_eflash.gen_flash_cores[0].u_core.u_host_arb.gen_input_bufs[0].gen_fixed_arbiter.u_arb	96.88	87.50	100.00			100.00	100.00
tb.dut.u_eflash.gen_flash_cores[0].u_core.u_host_arb.gen_input_bufs[1].gen_fixed_arbiter.u_arb	96.88	87.50	100.00			100.00	100.00
tb.dut.u_eflash.gen_flash_cores[1].u_core.u_host_arb.gen_input_bufs[0].gen_fixed_arbiter.u_arb	96.88	87.50	100.00			100.00	100.00
tb.dut.u_eflash.gen_flash_cores[1].u_core.u_host_arb.gen_input_bufs[1].gen_fixed_arbiter.u_arb	96.88	87.50	100.00			100.00	100.00

---

Module Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_host_arb.gen_input_bufs[0].gen_fixed_arbiter.u_arb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.88	87.50	100.00			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.88	87.50	100.00			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.67	90.00	100.00			100.00		u_host_arb

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_host_arb.gen_input_bufs[1].gen_fixed_arbiter.u_arb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.88	87.50	100.00			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.88	87.50	100.00			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.67	90.00	100.00			100.00		u_host_arb

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_host_arb.gen_input_bufs[0].gen_fixed_arbiter.u_arb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.88	87.50	100.00			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.88	87.50	100.00			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.67	90.00	100.00			100.00		u_host_arb

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_host_arb.gen_input_bufs[1].gen_fixed_arbiter.u_arb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.88	87.50	100.00			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.88	87.50	100.00			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.67	90.00	100.00			100.00		u_host_arb

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Module : prim_arbiter_fixed

	Line No.	Total	Covered	Percent
TOTAL		16	14	87.50
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	87	1	0	0.00
CONT_ASSIGN	87	1	0	0.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	89	1	1	100.00
ALWAYS	105	6	6	100.00
CONT_ASSIGN	124	1	1	100.00
CONT_ASSIGN	128	1	1	100.00
CONT_ASSIGN	129	1	1	100.00
CONT_ASSIGN	132	1	1	100.00

84                                  // forward path
85         2/2                      assign req_tree[Pa]      = req_i[offset];
           Tests:       T1 T2 T3  | T1 T2 T3 
86                                  assign idx_tree[Pa]      = offset;
87         0/2     ==>              assign data_tree[Pa]     = data_i[offset];
88                                  // backward (grant) path
89         2/2                      assign gnt_o[offset]     = gnt_tree[Pa];
           Tests:       T1 T2 T3  | T1 T2 T3 
90                      
91                                end else begin : gen_tie_off
92                                  // forward path
93                                  assign req_tree[Pa]  = '0;
94                                  assign idx_tree[Pa]  = '0;
95                                  assign data_tree[Pa] = '0;
96                                  logic unused_sigs;
97                                  assign unused_sigs = gnt_tree[Pa];
98                                end
99                              // this creates the node assignments
100                             end else begin : gen_nodes
101                               // forward path
102                               logic sel; // local helper variable
103                               always_comb begin : p_node
104                                 // this always gives priority to the left child
105        1/1                      sel = ~req_tree[C0];
           Tests:       T1 T2 T3 
106                                 // propagate requests
107        1/1                      req_tree[Pa]  = req_tree[C0] | req_tree[C1];
           Tests:       T1 T2 T3 
108                                 // data and index muxes
109        1/1                      idx_tree[Pa]  = (sel) ? idx_tree[C1]  : idx_tree[C0];
           Tests:       T1 T2 T3 
110        1/1                      data_tree[Pa] = (sel) ? data_tree[C1] : data_tree[C0];
           Tests:       T1 T2 T3 
111                                 // propagate the grants back to the input
112        1/1                      gnt_tree[C0] = gnt_tree[Pa] & ~sel;
           Tests:       T1 T2 T3 
113        1/1                      gnt_tree[C1] = gnt_tree[Pa] &  sel;
           Tests:       T1 T2 T3 
114                               end
115                             end
116                           end : gen_level
117                         end : gen_tree
118                     
119                         // the results can be found at the tree root
120                         if (EnDataPort) begin : gen_data_port
121                           assign data_o      = data_tree[0];
122                         end else begin : gen_no_dataport
123                           logic [DW-1:0] unused_data;
124        1/1                assign unused_data = data_tree[0];
           Tests:       T1 T2 T16 
125                           assign data_o = '1;
126                         end
127                     
128        1/1              assign idx_o       = idx_tree[0];
           Tests:       T1 T2 T3 
129        1/1              assign valid_o     = req_tree[0];
           Tests:       T1 T2 T3 
130                     
131                         // this propagates a grant back to the input
132        1/1              assign gnt_tree[0] = valid_o & ready_i;
           Tests:       T1 T2 T3 

---

Cond Coverage for Module : prim_arbiter_fixed

	Total	Covered	Percent
Conditions	16	16	100.00
Logical	16	16	100.00
Non-Logical	0	0
Event	0	0

 LINE       107
 EXPRESSION (gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C0] | gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C1])
             ----------------------------------1----------------------------------   ----------------------------------2----------------------------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T3,T11

 LINE       109
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])

-1-	Status	Tests
0	Covered	T1,T3,T11
1	Covered	T1,T2,T3

 LINE       110
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])

-1-	Status	Tests
0	Covered	T1,T3,T11
1	Covered	T1,T2,T3

 LINE       112
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & ((~gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)))
             ----------------------------------1----------------------------------   -----------------------------2-----------------------------

-1-	-2-	Status	Tests
0	1	Covered	T11,T12,T34
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T3,T11

 LINE       113
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)
             ----------------------------------1----------------------------------   ---------------------------2--------------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T3,T11
1	1	Covered	T1,T2,T3

 LINE       132
 EXPRESSION (valid_o & ready_i)
             ---1---   ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T11,T12,T34
1	1	Covered	T1,T2,T3

---

Branch Coverage for Module : prim_arbiter_fixed

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
TERNARY	109	2	2	100.00
TERNARY	110	2	2	100.00

109                    idx_tree[Pa]  = (sel) ? idx_tree[C1]  : idx_tree[C0];
                                             -1-  
                                             ==>  
                                             ==>  

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T3,T11

110                    data_tree[Pa] = (sel) ? data_tree[C1] : data_tree[C0];
                                             -1-  
                                             ==>  
                                             ==>  

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T3,T11

---

Assert Coverage for Module : prim_arbiter_fixed

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	13	13	100.00	13	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	13	13	100.00	13	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	1598618636	1595547360	0	0
CheckNGreaterZero_A	4212	4212	0	0
GntImpliesReady_A	1598618636	409896513	0	0
GntImpliesValid_A	1598618636	409896513	0	0
GrantKnown_A	1598618636	1595547360	0	0
IdxKnown_A	1598618636	1595547360	0	0
IndexIsCorrect_A	1598618636	409896513	0	0
NoReadyValidNoGrant_A	1598618636	180194967	0	0
Priority_A	1598618636	433286664	0	0
ReadyAndValidImplyGrant_A	1598618636	409896513	0	0
ReqAndReadyImplyGrant_A	1598618636	409896513	0	0
ReqImpliesValid_A	1598618636	433286664	0	0
ValidKnown_A	1598618636	1595547360	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1598618636	1595547360	0	0
T1	5720	5416	0	0
T2	9456	9100	0	0
T3	36276	36072	0	0
T4	14000	11304	0	0
T10	15024	14660	0	0
T11	18432	18092	0	0
T16	9128	8872	0	0
T17	7456	7148	0	0
T18	622412	622192	0	0
T19	7348	6984	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	4212	4212	0	0
T1	4	4	0	0
T2	4	4	0	0
T3	4	4	0	0
T4	4	4	0	0
T10	4	4	0	0
T11	4	4	0	0
T16	4	4	0	0
T17	4	4	0	0
T18	4	4	0	0
T19	4	4	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1598618636	409896513	0	0
T1	2860	84	0	0
T2	4728	1132	0	0
T3	36276	1410	0	0
T4	14000	300	0	0
T10	15024	4442	0	0
T11	18432	4890	0	0
T16	9128	356	0	0
T17	7456	356	0	0
T18	622412	100760	0	0
T19	7348	356	0	0
T29	341014	161026	0	0
T30	0	24118	0	0
T33	389490	138096	0	0
T63	0	86762	0	0
T69	0	4	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1598618636	409896513	0	0
T1	2860	84	0	0
T2	4728	1132	0	0
T3	36276	1410	0	0
T4	14000	300	0	0
T10	15024	4442	0	0
T11	18432	4890	0	0
T16	9128	356	0	0
T17	7456	356	0	0
T18	622412	100760	0	0
T19	7348	356	0	0
T29	341014	161026	0	0
T30	0	24118	0	0
T33	389490	138096	0	0
T63	0	86762	0	0
T69	0	4	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1598618636	1595547360	0	0
T1	5720	5416	0	0
T2	9456	9100	0	0
T3	36276	36072	0	0
T4	14000	11304	0	0
T10	15024	14660	0	0
T11	18432	18092	0	0
T16	9128	8872	0	0
T17	7456	7148	0	0
T18	622412	622192	0	0
T19	7348	6984	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1598618636	1595547360	0	0
T1	5720	5416	0	0
T2	9456	9100	0	0
T3	36276	36072	0	0
T4	14000	11304	0	0
T10	15024	14660	0	0
T11	18432	18092	0	0
T16	9128	8872	0	0
T17	7456	7148	0	0
T18	622412	622192	0	0
T19	7348	6984	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1598618636	409896513	0	0
T1	2860	84	0	0
T2	4728	1132	0	0
T3	36276	1410	0	0
T4	14000	300	0	0
T10	15024	4442	0	0
T11	18432	4890	0	0
T16	9128	356	0	0
T17	7456	356	0	0
T18	622412	100760	0	0
T19	7348	356	0	0
T29	341014	161026	0	0
T30	0	24118	0	0
T33	389490	138096	0	0
T63	0	86762	0	0
T69	0	4	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1598618636	180194967	0	0
T1	2860	286	0	0
T2	4728	316	0	0
T3	36276	2254	0	0
T4	14000	1104	0	0
T10	15024	256	0	0
T11	18432	654	0	0
T12	0	27852	0	0
T16	9128	986	0	0
T17	7456	656	0	0
T18	622412	7732	0	0
T19	7348	986	0	0
T29	341014	0	0	0
T30	0	96	0	0
T33	389490	0	0	0
T34	0	102	0	0
T48	0	68966	0	0
T63	0	1666	0	0

Priority_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1598618636	433286664	0	0
T1	2860	84	0	0
T2	4728	1132	0	0
T3	36276	1410	0	0
T4	14000	300	0	0
T10	15024	4442	0	0
T11	18432	4892	0	0
T16	9128	356	0	0
T17	7456	356	0	0
T18	622412	100760	0	0
T19	7348	356	0	0
T29	341014	161026	0	0
T30	0	24118	0	0
T33	389490	138096	0	0
T63	0	86762	0	0
T69	0	4	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1598618636	409896513	0	0
T1	2860	84	0	0
T2	4728	1132	0	0
T3	36276	1410	0	0
T4	14000	300	0	0
T10	15024	4442	0	0
T11	18432	4890	0	0
T16	9128	356	0	0
T17	7456	356	0	0
T18	622412	100760	0	0
T19	7348	356	0	0
T29	341014	161026	0	0
T30	0	24118	0	0
T33	389490	138096	0	0
T63	0	86762	0	0
T69	0	4	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1598618636	409896513	0	0
T1	2860	84	0	0
T2	4728	1132	0	0
T3	36276	1410	0	0
T4	14000	300	0	0
T10	15024	4442	0	0
T11	18432	4890	0	0
T16	9128	356	0	0
T17	7456	356	0	0
T18	622412	100760	0	0
T19	7348	356	0	0
T29	341014	161026	0	0
T30	0	24118	0	0
T33	389490	138096	0	0
T63	0	86762	0	0
T69	0	4	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1598618636	433286664	0	0
T1	2860	84	0	0
T2	4728	1132	0	0
T3	36276	1410	0	0
T4	14000	300	0	0
T10	15024	4442	0	0
T11	18432	4892	0	0
T16	9128	356	0	0
T17	7456	356	0	0
T18	622412	100760	0	0
T19	7348	356	0	0
T29	341014	161026	0	0
T30	0	24118	0	0
T33	389490	138096	0	0
T63	0	86762	0	0
T69	0	4	0	0

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1598618636	1595547360	0	0
T1	5720	5416	0	0
T2	9456	9100	0	0
T3	36276	36072	0	0
T4	14000	11304	0	0
T10	15024	14660	0	0
T11	18432	18092	0	0
T16	9128	8872	0	0
T17	7456	7148	0	0
T18	622412	622192	0	0
T19	7348	6984	0	0

Line Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_host_arb.gen_input_bufs[0].gen_fixed_arbiter.u_arb

	Line No.	Total	Covered	Percent
TOTAL		16	14	87.50
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	87	1	0	0.00
CONT_ASSIGN	87	1	0	0.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	89	1	1	100.00
ALWAYS	105	6	6	100.00
CONT_ASSIGN	124	1	1	100.00
CONT_ASSIGN	128	1	1	100.00
CONT_ASSIGN	129	1	1	100.00
CONT_ASSIGN	132	1	1	100.00

84                                  // forward path
85         2/2                      assign req_tree[Pa]      = req_i[offset];
           Tests:       T1 T2 T3  | T1 T2 T3 
86                                  assign idx_tree[Pa]      = offset;
87         0/2     ==>              assign data_tree[Pa]     = data_i[offset];
88                                  // backward (grant) path
89         2/2                      assign gnt_o[offset]     = gnt_tree[Pa];
           Tests:       T1 T2 T3  | T1 T2 T3 
90                      
91                                end else begin : gen_tie_off
92                                  // forward path
93                                  assign req_tree[Pa]  = '0;
94                                  assign idx_tree[Pa]  = '0;
95                                  assign data_tree[Pa] = '0;
96                                  logic unused_sigs;
97                                  assign unused_sigs = gnt_tree[Pa];
98                                end
99                              // this creates the node assignments
100                             end else begin : gen_nodes
101                               // forward path
102                               logic sel; // local helper variable
103                               always_comb begin : p_node
104                                 // this always gives priority to the left child
105        1/1                      sel = ~req_tree[C0];
           Tests:       T1 T2 T3 
106                                 // propagate requests
107        1/1                      req_tree[Pa]  = req_tree[C0] | req_tree[C1];
           Tests:       T1 T2 T3 
108                                 // data and index muxes
109        1/1                      idx_tree[Pa]  = (sel) ? idx_tree[C1]  : idx_tree[C0];
           Tests:       T1 T2 T3 
110        1/1                      data_tree[Pa] = (sel) ? data_tree[C1] : data_tree[C0];
           Tests:       T1 T2 T3 
111                                 // propagate the grants back to the input
112        1/1                      gnt_tree[C0] = gnt_tree[Pa] & ~sel;
           Tests:       T1 T2 T3 
113        1/1                      gnt_tree[C1] = gnt_tree[Pa] &  sel;
           Tests:       T1 T2 T3 
114                               end
115                             end
116                           end : gen_level
117                         end : gen_tree
118                     
119                         // the results can be found at the tree root
120                         if (EnDataPort) begin : gen_data_port
121                           assign data_o      = data_tree[0];
122                         end else begin : gen_no_dataport
123                           logic [DW-1:0] unused_data;
124        1/1                assign unused_data = data_tree[0];
           Tests:       T1 T2 T16 
125                           assign data_o = '1;
126                         end
127                     
128        1/1              assign idx_o       = idx_tree[0];
           Tests:       T1 T2 T3 
129        1/1              assign valid_o     = req_tree[0];
           Tests:       T1 T2 T3 
130                     
131                         // this propagates a grant back to the input
132        1/1              assign gnt_tree[0] = valid_o & ready_i;
           Tests:       T1 T2 T3 

---

Cond Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_host_arb.gen_input_bufs[0].gen_fixed_arbiter.u_arb

	Total	Covered	Percent
Conditions	16	16	100.00
Logical	16	16	100.00
Non-Logical	0	0
Event	0	0

 LINE       107
 EXPRESSION (gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C0] | gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C1])
             ----------------------------------1----------------------------------   ----------------------------------2----------------------------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T3,T11

 LINE       109
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])

-1-	Status	Tests
0	Covered	T1,T3,T11
1	Covered	T1,T2,T3

 LINE       110
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])

-1-	Status	Tests
0	Covered	T1,T3,T11
1	Covered	T1,T2,T3

 LINE       112
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & ((~gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)))
             ----------------------------------1----------------------------------   -----------------------------2-----------------------------

-1-	-2-	Status	Tests
0	1	Covered	T12,T34,T48
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T3,T11

 LINE       113
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)
             ----------------------------------1----------------------------------   ---------------------------2--------------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T3,T11
1	1	Covered	T1,T2,T3

 LINE       132
 EXPRESSION (valid_o & ready_i)
             ---1---   ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T12,T34,T48
1	1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_host_arb.gen_input_bufs[0].gen_fixed_arbiter.u_arb

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
TERNARY	109	2	2	100.00
TERNARY	110	2	2	100.00

109                    idx_tree[Pa]  = (sel) ? idx_tree[C1]  : idx_tree[C0];
                                             -1-  
                                             ==>  
                                             ==>  

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T3,T11

110                    data_tree[Pa] = (sel) ? data_tree[C1] : data_tree[C0];
                                             -1-  
                                             ==>  
                                             ==>  

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T3,T11

---

Assert Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_host_arb.gen_input_bufs[0].gen_fixed_arbiter.u_arb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	13	13	100.00	13	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	13	13	100.00	13	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	399654659	398886840	0	0
CheckNGreaterZero_A	1053	1053	0	0
GntImpliesReady_A	399654659	105765575	0	0
GntImpliesValid_A	399654659	105765575	0	0
GrantKnown_A	399654659	398886840	0	0
IdxKnown_A	399654659	398886840	0	0
IndexIsCorrect_A	399654659	105765575	0	0
NoReadyValidNoGrant_A	399654659	46376075	0	0
Priority_A	399654659	111587478	0	0
ReadyAndValidImplyGrant_A	399654659	105765575	0	0
ReqAndReadyImplyGrant_A	399654659	105765575	0	0
ReqImpliesValid_A	399654659	111587478	0	0
ValidKnown_A	399654659	398886840	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	399654659	398886840	0	0
T1	1430	1354	0	0
T2	2364	2275	0	0
T3	9069	9018	0	0
T4	3500	2826	0	0
T10	3756	3665	0	0
T11	4608	4523	0	0
T16	2282	2218	0	0
T17	1864	1787	0	0
T18	155603	155548	0	0
T19	1837	1746	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1053	1053	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	399654659	105765575	0	0
T1	1430	42	0	0
T2	2364	566	0	0
T3	9069	447	0	0
T4	3500	150	0	0
T10	3756	2221	0	0
T11	4608	394	0	0
T16	2282	32	0	0
T17	1864	32	0	0
T18	155603	26711	0	0
T19	1837	178	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	399654659	105765575	0	0
T1	1430	42	0	0
T2	2364	566	0	0
T3	9069	447	0	0
T4	3500	150	0	0
T10	3756	2221	0	0
T11	4608	394	0	0
T16	2282	32	0	0
T17	1864	32	0	0
T18	155603	26711	0	0
T19	1837	178	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	399654659	398886840	0	0
T1	1430	1354	0	0
T2	2364	2275	0	0
T3	9069	9018	0	0
T4	3500	2826	0	0
T10	3756	3665	0	0
T11	4608	4523	0	0
T16	2282	2218	0	0
T17	1864	1787	0	0
T18	155603	155548	0	0
T19	1837	1746	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	399654659	398886840	0	0
T1	1430	1354	0	0
T2	2364	2275	0	0
T3	9069	9018	0	0
T4	3500	2826	0	0
T10	3756	3665	0	0
T11	4608	4523	0	0
T16	2282	2218	0	0
T17	1864	1787	0	0
T18	155603	155548	0	0
T19	1837	1746	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	399654659	105765575	0	0
T1	1430	42	0	0
T2	2364	566	0	0
T3	9069	447	0	0
T4	3500	150	0	0
T10	3756	2221	0	0
T11	4608	394	0	0
T16	2282	32	0	0
T17	1864	32	0	0
T18	155603	26711	0	0
T19	1837	178	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	399654659	46376075	0	0
T1	1430	143	0	0
T2	2364	158	0	0
T3	9069	747	0	0
T4	3500	552	0	0
T10	3756	128	0	0
T11	4608	157	0	0
T16	2282	128	0	0
T17	1864	128	0	0
T18	155603	1994	0	0
T19	1837	493	0	0

Priority_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	399654659	111587478	0	0
T1	1430	42	0	0
T2	2364	566	0	0
T3	9069	447	0	0
T4	3500	150	0	0
T10	3756	2221	0	0
T11	4608	394	0	0
T16	2282	32	0	0
T17	1864	32	0	0
T18	155603	26711	0	0
T19	1837	178	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	399654659	105765575	0	0
T1	1430	42	0	0
T2	2364	566	0	0
T3	9069	447	0	0
T4	3500	150	0	0
T10	3756	2221	0	0
T11	4608	394	0	0
T16	2282	32	0	0
T17	1864	32	0	0
T18	155603	26711	0	0
T19	1837	178	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	399654659	105765575	0	0
T1	1430	42	0	0
T2	2364	566	0	0
T3	9069	447	0	0
T4	3500	150	0	0
T10	3756	2221	0	0
T11	4608	394	0	0
T16	2282	32	0	0
T17	1864	32	0	0
T18	155603	26711	0	0
T19	1837	178	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	399654659	111587478	0	0
T1	1430	42	0	0
T2	2364	566	0	0
T3	9069	447	0	0
T4	3500	150	0	0
T10	3756	2221	0	0
T11	4608	394	0	0
T16	2282	32	0	0
T17	1864	32	0	0
T18	155603	26711	0	0
T19	1837	178	0	0

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	399654659	398886840	0	0
T1	1430	1354	0	0
T2	2364	2275	0	0
T3	9069	9018	0	0
T4	3500	2826	0	0
T10	3756	3665	0	0
T11	4608	4523	0	0
T16	2282	2218	0	0
T17	1864	1787	0	0
T18	155603	155548	0	0
T19	1837	1746	0	0

Line Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_host_arb.gen_input_bufs[1].gen_fixed_arbiter.u_arb

	Line No.	Total	Covered	Percent
TOTAL		16	14	87.50
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	87	1	0	0.00
CONT_ASSIGN	87	1	0	0.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	89	1	1	100.00
ALWAYS	105	6	6	100.00
CONT_ASSIGN	124	1	1	100.00
CONT_ASSIGN	128	1	1	100.00
CONT_ASSIGN	129	1	1	100.00
CONT_ASSIGN	132	1	1	100.00

84                                  // forward path
85         2/2                      assign req_tree[Pa]      = req_i[offset];
           Tests:       T1 T2 T3  | T1 T2 T3 
86                                  assign idx_tree[Pa]      = offset;
87         0/2     ==>              assign data_tree[Pa]     = data_i[offset];
88                                  // backward (grant) path
89         2/2                      assign gnt_o[offset]     = gnt_tree[Pa];
           Tests:       T1 T2 T3  | T1 T2 T3 
90                      
91                                end else begin : gen_tie_off
92                                  // forward path
93                                  assign req_tree[Pa]  = '0;
94                                  assign idx_tree[Pa]  = '0;
95                                  assign data_tree[Pa] = '0;
96                                  logic unused_sigs;
97                                  assign unused_sigs = gnt_tree[Pa];
98                                end
99                              // this creates the node assignments
100                             end else begin : gen_nodes
101                               // forward path
102                               logic sel; // local helper variable
103                               always_comb begin : p_node
104                                 // this always gives priority to the left child
105        1/1                      sel = ~req_tree[C0];
           Tests:       T1 T2 T3 
106                                 // propagate requests
107        1/1                      req_tree[Pa]  = req_tree[C0] | req_tree[C1];
           Tests:       T1 T2 T3 
108                                 // data and index muxes
109        1/1                      idx_tree[Pa]  = (sel) ? idx_tree[C1]  : idx_tree[C0];
           Tests:       T1 T2 T3 
110        1/1                      data_tree[Pa] = (sel) ? data_tree[C1] : data_tree[C0];
           Tests:       T1 T2 T3 
111                                 // propagate the grants back to the input
112        1/1                      gnt_tree[C0] = gnt_tree[Pa] & ~sel;
           Tests:       T1 T2 T3 
113        1/1                      gnt_tree[C1] = gnt_tree[Pa] &  sel;
           Tests:       T1 T2 T3 
114                               end
115                             end
116                           end : gen_level
117                         end : gen_tree
118                     
119                         // the results can be found at the tree root
120                         if (EnDataPort) begin : gen_data_port
121                           assign data_o      = data_tree[0];
122                         end else begin : gen_no_dataport
123                           logic [DW-1:0] unused_data;
124        1/1                assign unused_data = data_tree[0];
           Tests:       T1 T2 T16 
125                           assign data_o = '1;
126                         end
127                     
128        1/1              assign idx_o       = idx_tree[0];
           Tests:       T1 T2 T3 
129        1/1              assign valid_o     = req_tree[0];
           Tests:       T1 T2 T3 
130                     
131                         // this propagates a grant back to the input
132        1/1              assign gnt_tree[0] = valid_o & ready_i;
           Tests:       T1 T2 T3 

---

Cond Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_host_arb.gen_input_bufs[1].gen_fixed_arbiter.u_arb

	Total	Covered	Percent
Conditions	16	16	100.00
Logical	16	16	100.00
Non-Logical	0	0
Event	0	0

 LINE       107
 EXPRESSION (gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C0] | gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C1])
             ----------------------------------1----------------------------------   ----------------------------------2----------------------------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T3,T11

 LINE       109
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])

-1-	Status	Tests
0	Covered	T1,T3,T11
1	Covered	T1,T2,T3

 LINE       110
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])

-1-	Status	Tests
0	Covered	T1,T3,T11
1	Covered	T1,T2,T3

 LINE       112
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & ((~gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)))
             ----------------------------------1----------------------------------   -----------------------------2-----------------------------

-1-	-2-	Status	Tests
0	1	Covered	T12,T34,T48
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T3,T11

 LINE       113
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)
             ----------------------------------1----------------------------------   ---------------------------2--------------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T3,T11
1	1	Covered	T1,T2,T3

 LINE       132
 EXPRESSION (valid_o & ready_i)
             ---1---   ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T12,T34,T48
1	1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_host_arb.gen_input_bufs[1].gen_fixed_arbiter.u_arb

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
TERNARY	109	2	2	100.00
TERNARY	110	2	2	100.00

109                    idx_tree[Pa]  = (sel) ? idx_tree[C1]  : idx_tree[C0];
                                             -1-  
                                             ==>  
                                             ==>  

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T3,T11

110                    data_tree[Pa] = (sel) ? data_tree[C1] : data_tree[C0];
                                             -1-  
                                             ==>  
                                             ==>  

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T3,T11

---

Assert Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_host_arb.gen_input_bufs[1].gen_fixed_arbiter.u_arb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	13	13	100.00	13	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	13	13	100.00	13	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	399654659	398886840	0	0
CheckNGreaterZero_A	1053	1053	0	0
GntImpliesReady_A	399654659	105765642	0	0
GntImpliesValid_A	399654659	105765642	0	0
GrantKnown_A	399654659	398886840	0	0
IdxKnown_A	399654659	398886840	0	0
IndexIsCorrect_A	399654659	105765642	0	0
NoReadyValidNoGrant_A	399654659	46376063	0	0
Priority_A	399654659	111587557	0	0
ReadyAndValidImplyGrant_A	399654659	105765642	0	0
ReqAndReadyImplyGrant_A	399654659	105765642	0	0
ReqImpliesValid_A	399654659	111587557	0	0
ValidKnown_A	399654659	398886840	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	399654659	398886840	0	0
T1	1430	1354	0	0
T2	2364	2275	0	0
T3	9069	9018	0	0
T4	3500	2826	0	0
T10	3756	3665	0	0
T11	4608	4523	0	0
T16	2282	2218	0	0
T17	1864	1787	0	0
T18	155603	155548	0	0
T19	1837	1746	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1053	1053	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	399654659	105765642	0	0
T1	1430	42	0	0
T2	2364	566	0	0
T3	9069	447	0	0
T4	3500	150	0	0
T10	3756	2221	0	0
T11	4608	394	0	0
T16	2282	32	0	0
T17	1864	32	0	0
T18	155603	26711	0	0
T19	1837	178	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	399654659	105765642	0	0
T1	1430	42	0	0
T2	2364	566	0	0
T3	9069	447	0	0
T4	3500	150	0	0
T10	3756	2221	0	0
T11	4608	394	0	0
T16	2282	32	0	0
T17	1864	32	0	0
T18	155603	26711	0	0
T19	1837	178	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	399654659	398886840	0	0
T1	1430	1354	0	0
T2	2364	2275	0	0
T3	9069	9018	0	0
T4	3500	2826	0	0
T10	3756	3665	0	0
T11	4608	4523	0	0
T16	2282	2218	0	0
T17	1864	1787	0	0
T18	155603	155548	0	0
T19	1837	1746	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	399654659	398886840	0	0
T1	1430	1354	0	0
T2	2364	2275	0	0
T3	9069	9018	0	0
T4	3500	2826	0	0
T10	3756	3665	0	0
T11	4608	4523	0	0
T16	2282	2218	0	0
T17	1864	1787	0	0
T18	155603	155548	0	0
T19	1837	1746	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	399654659	105765642	0	0
T1	1430	42	0	0
T2	2364	566	0	0
T3	9069	447	0	0
T4	3500	150	0	0
T10	3756	2221	0	0
T11	4608	394	0	0
T16	2282	32	0	0
T17	1864	32	0	0
T18	155603	26711	0	0
T19	1837	178	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	399654659	46376063	0	0
T1	1430	143	0	0
T2	2364	158	0	0
T3	9069	747	0	0
T4	3500	552	0	0
T10	3756	128	0	0
T11	4608	157	0	0
T16	2282	128	0	0
T17	1864	128	0	0
T18	155603	1994	0	0
T19	1837	493	0	0

Priority_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	399654659	111587557	0	0
T1	1430	42	0	0
T2	2364	566	0	0
T3	9069	447	0	0
T4	3500	150	0	0
T10	3756	2221	0	0
T11	4608	394	0	0
T16	2282	32	0	0
T17	1864	32	0	0
T18	155603	26711	0	0
T19	1837	178	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	399654659	105765642	0	0
T1	1430	42	0	0
T2	2364	566	0	0
T3	9069	447	0	0
T4	3500	150	0	0
T10	3756	2221	0	0
T11	4608	394	0	0
T16	2282	32	0	0
T17	1864	32	0	0
T18	155603	26711	0	0
T19	1837	178	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	399654659	105765642	0	0
T1	1430	42	0	0
T2	2364	566	0	0
T3	9069	447	0	0
T4	3500	150	0	0
T10	3756	2221	0	0
T11	4608	394	0	0
T16	2282	32	0	0
T17	1864	32	0	0
T18	155603	26711	0	0
T19	1837	178	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	399654659	111587557	0	0
T1	1430	42	0	0
T2	2364	566	0	0
T3	9069	447	0	0
T4	3500	150	0	0
T10	3756	2221	0	0
T11	4608	394	0	0
T16	2282	32	0	0
T17	1864	32	0	0
T18	155603	26711	0	0
T19	1837	178	0	0

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	399654659	398886840	0	0
T1	1430	1354	0	0
T2	2364	2275	0	0
T3	9069	9018	0	0
T4	3500	2826	0	0
T10	3756	3665	0	0
T11	4608	4523	0	0
T16	2282	2218	0	0
T17	1864	1787	0	0
T18	155603	155548	0	0
T19	1837	1746	0	0

Line Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_host_arb.gen_input_bufs[0].gen_fixed_arbiter.u_arb

	Line No.	Total	Covered	Percent
TOTAL		16	14	87.50
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	87	1	0	0.00
CONT_ASSIGN	87	1	0	0.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	89	1	1	100.00
ALWAYS	105	6	6	100.00
CONT_ASSIGN	124	1	1	100.00
CONT_ASSIGN	128	1	1	100.00
CONT_ASSIGN	129	1	1	100.00
CONT_ASSIGN	132	1	1	100.00

84                                  // forward path
85         2/2                      assign req_tree[Pa]      = req_i[offset];
           Tests:       T1 T2 T3  | T1 T2 T3 
86                                  assign idx_tree[Pa]      = offset;
87         0/2     ==>              assign data_tree[Pa]     = data_i[offset];
88                                  // backward (grant) path
89         2/2                      assign gnt_o[offset]     = gnt_tree[Pa];
           Tests:       T1 T2 T3  | T1 T2 T3 
90                      
91                                end else begin : gen_tie_off
92                                  // forward path
93                                  assign req_tree[Pa]  = '0;
94                                  assign idx_tree[Pa]  = '0;
95                                  assign data_tree[Pa] = '0;
96                                  logic unused_sigs;
97                                  assign unused_sigs = gnt_tree[Pa];
98                                end
99                              // this creates the node assignments
100                             end else begin : gen_nodes
101                               // forward path
102                               logic sel; // local helper variable
103                               always_comb begin : p_node
104                                 // this always gives priority to the left child
105        1/1                      sel = ~req_tree[C0];
           Tests:       T1 T2 T3 
106                                 // propagate requests
107        1/1                      req_tree[Pa]  = req_tree[C0] | req_tree[C1];
           Tests:       T1 T2 T3 
108                                 // data and index muxes
109        1/1                      idx_tree[Pa]  = (sel) ? idx_tree[C1]  : idx_tree[C0];
           Tests:       T1 T2 T3 
110        1/1                      data_tree[Pa] = (sel) ? data_tree[C1] : data_tree[C0];
           Tests:       T1 T2 T3 
111                                 // propagate the grants back to the input
112        1/1                      gnt_tree[C0] = gnt_tree[Pa] & ~sel;
           Tests:       T1 T2 T3 
113        1/1                      gnt_tree[C1] = gnt_tree[Pa] &  sel;
           Tests:       T1 T2 T3 
114                               end
115                             end
116                           end : gen_level
117                         end : gen_tree
118                     
119                         // the results can be found at the tree root
120                         if (EnDataPort) begin : gen_data_port
121                           assign data_o      = data_tree[0];
122                         end else begin : gen_no_dataport
123                           logic [DW-1:0] unused_data;
124        1/1                assign unused_data = data_tree[0];
           Tests:       T1 T2 T16 
125                           assign data_o = '1;
126                         end
127                     
128        1/1              assign idx_o       = idx_tree[0];
           Tests:       T1 T2 T3 
129        1/1              assign valid_o     = req_tree[0];
           Tests:       T1 T2 T3 
130                     
131                         // this propagates a grant back to the input
132        1/1              assign gnt_tree[0] = valid_o & ready_i;
           Tests:       T1 T2 T3 

---

Cond Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_host_arb.gen_input_bufs[0].gen_fixed_arbiter.u_arb

	Total	Covered	Percent
Conditions	16	16	100.00
Logical	16	16	100.00
Non-Logical	0	0
Event	0	0

 LINE       107
 EXPRESSION (gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C0] | gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C1])
             ----------------------------------1----------------------------------   ----------------------------------2----------------------------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T3,T16,T17
1	0	Covered	T3,T11,T12

 LINE       109
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])

-1-	Status	Tests
0	Covered	T3,T11,T12
1	Covered	T1,T2,T3

 LINE       110
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])

-1-	Status	Tests
0	Covered	T3,T11,T12
1	Covered	T1,T2,T3

 LINE       112
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & ((~gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)))
             ----------------------------------1----------------------------------   -----------------------------2-----------------------------

-1-	-2-	Status	Tests
0	1	Covered	T11,T12,T34
1	0	Covered	T3,T16,T17
1	1	Covered	T3,T11,T12

 LINE       113
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)
             ----------------------------------1----------------------------------   ---------------------------2--------------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T3,T11,T12
1	1	Covered	T3,T16,T17

 LINE       132
 EXPRESSION (valid_o & ready_i)
             ---1---   ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T11,T12,T34
1	1	Covered	T3,T16,T17

---

Branch Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_host_arb.gen_input_bufs[0].gen_fixed_arbiter.u_arb

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
TERNARY	109	2	2	100.00
TERNARY	110	2	2	100.00

109                    idx_tree[Pa]  = (sel) ? idx_tree[C1]  : idx_tree[C0];
                                             -1-  
                                             ==>  
                                             ==>  

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T3,T11,T12

110                    data_tree[Pa] = (sel) ? data_tree[C1] : data_tree[C0];
                                             -1-  
                                             ==>  
                                             ==>  

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T3,T11,T12

---

Assert Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_host_arb.gen_input_bufs[0].gen_fixed_arbiter.u_arb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	13	13	100.00	13	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	13	13	100.00	13	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	399654659	398886840	0	0
CheckNGreaterZero_A	1053	1053	0	0
GntImpliesReady_A	399654659	99182645	0	0
GntImpliesValid_A	399654659	99182645	0	0
GrantKnown_A	399654659	398886840	0	0
IdxKnown_A	399654659	398886840	0	0
IndexIsCorrect_A	399654659	99182645	0	0
NoReadyValidNoGrant_A	399654659	43721447	0	0
Priority_A	399654659	105055779	0	0
ReadyAndValidImplyGrant_A	399654659	99182645	0	0
ReqAndReadyImplyGrant_A	399654659	99182645	0	0
ReqImpliesValid_A	399654659	105055779	0	0
ValidKnown_A	399654659	398886840	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	399654659	398886840	0	0
T1	1430	1354	0	0
T2	2364	2275	0	0
T3	9069	9018	0	0
T4	3500	2826	0	0
T10	3756	3665	0	0
T11	4608	4523	0	0
T16	2282	2218	0	0
T17	1864	1787	0	0
T18	155603	155548	0	0
T19	1837	1746	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1053	1053	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	399654659	99182645	0	0
T3	9069	258	0	0
T4	3500	0	0	0
T10	3756	0	0	0
T11	4608	2051	0	0
T16	2282	146	0	0
T17	1864	146	0	0
T18	155603	23669	0	0
T19	1837	0	0	0
T29	170507	80513	0	0
T30	0	12059	0	0
T33	194745	69048	0	0
T63	0	43381	0	0
T69	0	2	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	399654659	99182645	0	0
T3	9069	258	0	0
T4	3500	0	0	0
T10	3756	0	0	0
T11	4608	2051	0	0
T16	2282	146	0	0
T17	1864	146	0	0
T18	155603	23669	0	0
T19	1837	0	0	0
T29	170507	80513	0	0
T30	0	12059	0	0
T33	194745	69048	0	0
T63	0	43381	0	0
T69	0	2	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	399654659	398886840	0	0
T1	1430	1354	0	0
T2	2364	2275	0	0
T3	9069	9018	0	0
T4	3500	2826	0	0
T10	3756	3665	0	0
T11	4608	4523	0	0
T16	2282	2218	0	0
T17	1864	1787	0	0
T18	155603	155548	0	0
T19	1837	1746	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	399654659	398886840	0	0
T1	1430	1354	0	0
T2	2364	2275	0	0
T3	9069	9018	0	0
T4	3500	2826	0	0
T10	3756	3665	0	0
T11	4608	4523	0	0
T16	2282	2218	0	0
T17	1864	1787	0	0
T18	155603	155548	0	0
T19	1837	1746	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	399654659	99182645	0	0
T3	9069	258	0	0
T4	3500	0	0	0
T10	3756	0	0	0
T11	4608	2051	0	0
T16	2282	146	0	0
T17	1864	146	0	0
T18	155603	23669	0	0
T19	1837	0	0	0
T29	170507	80513	0	0
T30	0	12059	0	0
T33	194745	69048	0	0
T63	0	43381	0	0
T69	0	2	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	399654659	43721447	0	0
T3	9069	380	0	0
T4	3500	0	0	0
T10	3756	0	0	0
T11	4608	170	0	0
T12	0	13926	0	0
T16	2282	365	0	0
T17	1864	200	0	0
T18	155603	1872	0	0
T19	1837	0	0	0
T29	170507	0	0	0
T30	0	48	0	0
T33	194745	0	0	0
T34	0	51	0	0
T48	0	34483	0	0
T63	0	833	0	0

Priority_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	399654659	105055779	0	0
T3	9069	258	0	0
T4	3500	0	0	0
T10	3756	0	0	0
T11	4608	2052	0	0
T16	2282	146	0	0
T17	1864	146	0	0
T18	155603	23669	0	0
T19	1837	0	0	0
T29	170507	80513	0	0
T30	0	12059	0	0
T33	194745	69048	0	0
T63	0	43381	0	0
T69	0	2	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	399654659	99182645	0	0
T3	9069	258	0	0
T4	3500	0	0	0
T10	3756	0	0	0
T11	4608	2051	0	0
T16	2282	146	0	0
T17	1864	146	0	0
T18	155603	23669	0	0
T19	1837	0	0	0
T29	170507	80513	0	0
T30	0	12059	0	0
T33	194745	69048	0	0
T63	0	43381	0	0
T69	0	2	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	399654659	99182645	0	0
T3	9069	258	0	0
T4	3500	0	0	0
T10	3756	0	0	0
T11	4608	2051	0	0
T16	2282	146	0	0
T17	1864	146	0	0
T18	155603	23669	0	0
T19	1837	0	0	0
T29	170507	80513	0	0
T30	0	12059	0	0
T33	194745	69048	0	0
T63	0	43381	0	0
T69	0	2	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	399654659	105055779	0	0
T3	9069	258	0	0
T4	3500	0	0	0
T10	3756	0	0	0
T11	4608	2052	0	0
T16	2282	146	0	0
T17	1864	146	0	0
T18	155603	23669	0	0
T19	1837	0	0	0
T29	170507	80513	0	0
T30	0	12059	0	0
T33	194745	69048	0	0
T63	0	43381	0	0
T69	0	2	0	0

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	399654659	398886840	0	0
T1	1430	1354	0	0
T2	2364	2275	0	0
T3	9069	9018	0	0
T4	3500	2826	0	0
T10	3756	3665	0	0
T11	4608	4523	0	0
T16	2282	2218	0	0
T17	1864	1787	0	0
T18	155603	155548	0	0
T19	1837	1746	0	0

Line Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_host_arb.gen_input_bufs[1].gen_fixed_arbiter.u_arb

	Line No.	Total	Covered	Percent
TOTAL		16	14	87.50
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	87	1	0	0.00
CONT_ASSIGN	87	1	0	0.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	89	1	1	100.00
ALWAYS	105	6	6	100.00
CONT_ASSIGN	124	1	1	100.00
CONT_ASSIGN	128	1	1	100.00
CONT_ASSIGN	129	1	1	100.00
CONT_ASSIGN	132	1	1	100.00

84                                  // forward path
85         2/2                      assign req_tree[Pa]      = req_i[offset];
           Tests:       T1 T2 T3  | T1 T2 T3 
86                                  assign idx_tree[Pa]      = offset;
87         0/2     ==>              assign data_tree[Pa]     = data_i[offset];
88                                  // backward (grant) path
89         2/2                      assign gnt_o[offset]     = gnt_tree[Pa];
           Tests:       T1 T2 T3  | T1 T2 T3 
90                      
91                                end else begin : gen_tie_off
92                                  // forward path
93                                  assign req_tree[Pa]  = '0;
94                                  assign idx_tree[Pa]  = '0;
95                                  assign data_tree[Pa] = '0;
96                                  logic unused_sigs;
97                                  assign unused_sigs = gnt_tree[Pa];
98                                end
99                              // this creates the node assignments
100                             end else begin : gen_nodes
101                               // forward path
102                               logic sel; // local helper variable
103                               always_comb begin : p_node
104                                 // this always gives priority to the left child
105        1/1                      sel = ~req_tree[C0];
           Tests:       T1 T2 T3 
106                                 // propagate requests
107        1/1                      req_tree[Pa]  = req_tree[C0] | req_tree[C1];
           Tests:       T1 T2 T3 
108                                 // data and index muxes
109        1/1                      idx_tree[Pa]  = (sel) ? idx_tree[C1]  : idx_tree[C0];
           Tests:       T1 T2 T3 
110        1/1                      data_tree[Pa] = (sel) ? data_tree[C1] : data_tree[C0];
           Tests:       T1 T2 T3 
111                                 // propagate the grants back to the input
112        1/1                      gnt_tree[C0] = gnt_tree[Pa] & ~sel;
           Tests:       T1 T2 T3 
113        1/1                      gnt_tree[C1] = gnt_tree[Pa] &  sel;
           Tests:       T1 T2 T3 
114                               end
115                             end
116                           end : gen_level
117                         end : gen_tree
118                     
119                         // the results can be found at the tree root
120                         if (EnDataPort) begin : gen_data_port
121                           assign data_o      = data_tree[0];
122                         end else begin : gen_no_dataport
123                           logic [DW-1:0] unused_data;
124        1/1                assign unused_data = data_tree[0];
           Tests:       T1 T2 T16 
125                           assign data_o = '1;
126                         end
127                     
128        1/1              assign idx_o       = idx_tree[0];
           Tests:       T1 T2 T3 
129        1/1              assign valid_o     = req_tree[0];
           Tests:       T1 T2 T3 
130                     
131                         // this propagates a grant back to the input
132        1/1              assign gnt_tree[0] = valid_o & ready_i;
           Tests:       T1 T2 T3 

---

Cond Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_host_arb.gen_input_bufs[1].gen_fixed_arbiter.u_arb

	Total	Covered	Percent
Conditions	16	16	100.00
Logical	16	16	100.00
Non-Logical	0	0
Event	0	0

 LINE       107
 EXPRESSION (gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C0] | gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C1])
             ----------------------------------1----------------------------------   ----------------------------------2----------------------------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T3,T16,T17
1	0	Covered	T3,T11,T12

 LINE       109
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])

-1-	Status	Tests
0	Covered	T3,T11,T12
1	Covered	T1,T2,T3

 LINE       110
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])

-1-	Status	Tests
0	Covered	T3,T11,T12
1	Covered	T1,T2,T3

 LINE       112
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & ((~gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)))
             ----------------------------------1----------------------------------   -----------------------------2-----------------------------

-1-	-2-	Status	Tests
0	1	Covered	T11,T12,T34
1	0	Covered	T3,T16,T17
1	1	Covered	T3,T11,T12

 LINE       113
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)
             ----------------------------------1----------------------------------   ---------------------------2--------------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T3,T11,T12
1	1	Covered	T3,T16,T17

 LINE       132
 EXPRESSION (valid_o & ready_i)
             ---1---   ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T11,T12,T34
1	1	Covered	T3,T16,T17

---

Branch Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_host_arb.gen_input_bufs[1].gen_fixed_arbiter.u_arb

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
TERNARY	109	2	2	100.00
TERNARY	110	2	2	100.00

109                    idx_tree[Pa]  = (sel) ? idx_tree[C1]  : idx_tree[C0];
                                             -1-  
                                             ==>  
                                             ==>  

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T3,T11,T12

110                    data_tree[Pa] = (sel) ? data_tree[C1] : data_tree[C0];
                                             -1-  
                                             ==>  
                                             ==>  

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T3,T11,T12

---

Assert Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_host_arb.gen_input_bufs[1].gen_fixed_arbiter.u_arb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	13	13	100.00	13	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	13	13	100.00	13	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	399654659	398886840	0	0
CheckNGreaterZero_A	1053	1053	0	0
GntImpliesReady_A	399654659	99182651	0	0
GntImpliesValid_A	399654659	99182651	0	0
GrantKnown_A	399654659	398886840	0	0
IdxKnown_A	399654659	398886840	0	0
IndexIsCorrect_A	399654659	99182651	0	0
NoReadyValidNoGrant_A	399654659	43721382	0	0
Priority_A	399654659	105055850	0	0
ReadyAndValidImplyGrant_A	399654659	99182651	0	0
ReqAndReadyImplyGrant_A	399654659	99182651	0	0
ReqImpliesValid_A	399654659	105055850	0	0
ValidKnown_A	399654659	398886840	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	399654659	398886840	0	0
T1	1430	1354	0	0
T2	2364	2275	0	0
T3	9069	9018	0	0
T4	3500	2826	0	0
T10	3756	3665	0	0
T11	4608	4523	0	0
T16	2282	2218	0	0
T17	1864	1787	0	0
T18	155603	155548	0	0
T19	1837	1746	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1053	1053	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	399654659	99182651	0	0
T3	9069	258	0	0
T4	3500	0	0	0
T10	3756	0	0	0
T11	4608	2051	0	0
T16	2282	146	0	0
T17	1864	146	0	0
T18	155603	23669	0	0
T19	1837	0	0	0
T29	170507	80513	0	0
T30	0	12059	0	0
T33	194745	69048	0	0
T63	0	43381	0	0
T69	0	2	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	399654659	99182651	0	0
T3	9069	258	0	0
T4	3500	0	0	0
T10	3756	0	0	0
T11	4608	2051	0	0
T16	2282	146	0	0
T17	1864	146	0	0
T18	155603	23669	0	0
T19	1837	0	0	0
T29	170507	80513	0	0
T30	0	12059	0	0
T33	194745	69048	0	0
T63	0	43381	0	0
T69	0	2	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	399654659	398886840	0	0
T1	1430	1354	0	0
T2	2364	2275	0	0
T3	9069	9018	0	0
T4	3500	2826	0	0
T10	3756	3665	0	0
T11	4608	4523	0	0
T16	2282	2218	0	0
T17	1864	1787	0	0
T18	155603	155548	0	0
T19	1837	1746	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	399654659	398886840	0	0
T1	1430	1354	0	0
T2	2364	2275	0	0
T3	9069	9018	0	0
T4	3500	2826	0	0
T10	3756	3665	0	0
T11	4608	4523	0	0
T16	2282	2218	0	0
T17	1864	1787	0	0
T18	155603	155548	0	0
T19	1837	1746	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	399654659	99182651	0	0
T3	9069	258	0	0
T4	3500	0	0	0
T10	3756	0	0	0
T11	4608	2051	0	0
T16	2282	146	0	0
T17	1864	146	0	0
T18	155603	23669	0	0
T19	1837	0	0	0
T29	170507	80513	0	0
T30	0	12059	0	0
T33	194745	69048	0	0
T63	0	43381	0	0
T69	0	2	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	399654659	43721382	0	0
T3	9069	380	0	0
T4	3500	0	0	0
T10	3756	0	0	0
T11	4608	170	0	0
T12	0	13926	0	0
T16	2282	365	0	0
T17	1864	200	0	0
T18	155603	1872	0	0
T19	1837	0	0	0
T29	170507	0	0	0
T30	0	48	0	0
T33	194745	0	0	0
T34	0	51	0	0
T48	0	34483	0	0
T63	0	833	0	0

Priority_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	399654659	105055850	0	0
T3	9069	258	0	0
T4	3500	0	0	0
T10	3756	0	0	0
T11	4608	2052	0	0
T16	2282	146	0	0
T17	1864	146	0	0
T18	155603	23669	0	0
T19	1837	0	0	0
T29	170507	80513	0	0
T30	0	12059	0	0
T33	194745	69048	0	0
T63	0	43381	0	0
T69	0	2	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	399654659	99182651	0	0
T3	9069	258	0	0
T4	3500	0	0	0
T10	3756	0	0	0
T11	4608	2051	0	0
T16	2282	146	0	0
T17	1864	146	0	0
T18	155603	23669	0	0
T19	1837	0	0	0
T29	170507	80513	0	0
T30	0	12059	0	0
T33	194745	69048	0	0
T63	0	43381	0	0
T69	0	2	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	399654659	99182651	0	0
T3	9069	258	0	0
T4	3500	0	0	0
T10	3756	0	0	0
T11	4608	2051	0	0
T16	2282	146	0	0
T17	1864	146	0	0
T18	155603	23669	0	0
T19	1837	0	0	0
T29	170507	80513	0	0
T30	0	12059	0	0
T33	194745	69048	0	0
T63	0	43381	0	0
T69	0	2	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	399654659	105055850	0	0
T3	9069	258	0	0
T4	3500	0	0	0
T10	3756	0	0	0
T11	4608	2052	0	0
T16	2282	146	0	0
T17	1864	146	0	0
T18	155603	23669	0	0
T19	1837	0	0	0
T29	170507	80513	0	0
T30	0	12059	0	0
T33	194745	69048	0	0
T63	0	43381	0	0
T69	0	2	0	0

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	399654659	398886840	0	0
T1	1430	1354	0	0
T2	2364	2275	0	0
T3	9069	9018	0	0
T4	3500	2826	0	0
T10	3756	3665	0	0
T11	4608	4523	0	0
T16	2282	2218	0	0
T17	1864	1787	0	0
T18	155603	155548	0	0
T19	1837	1746	0	0