Unified Coverage Report :: Module :: prim_alert_sender

Module : prim_alert_sender

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/default/sim-vcs/../src/lowrisc_prim_alert_0/rtl/prim_alert_sender.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.gen_alert_senders[4].u_alert_sender	77.78			77.78
tb.dut.gen_alert_senders[0].u_alert_sender	100.00			100.00
tb.dut.gen_alert_senders[1].u_alert_sender	100.00			100.00
tb.dut.gen_alert_senders[2].u_alert_sender	100.00			100.00
tb.dut.gen_alert_senders[3].u_alert_sender	100.00			100.00

---

Module Instance : tb.dut.gen_alert_senders[4].u_alert_sender

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
77.78			77.78

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
77.78			77.78

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
94.85	97.12	94.40	98.44		100.00	84.29	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.gen_alert_senders[0].u_alert_sender

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
94.85	97.12	94.40	98.44		100.00	84.29	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.gen_alert_senders[1].u_alert_sender

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
94.85	97.12	94.40	98.44		100.00	84.29	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.gen_alert_senders[2].u_alert_sender

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
94.85	97.12	94.40	98.44		100.00	84.29	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.gen_alert_senders[3].u_alert_sender

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
94.85	97.12	94.40	98.44		100.00	84.29	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Toggle Coverage for Module : prim_alert_sender

	Total	Covered	Percent
Totals	10	10	100.00
Total Bits	20	20	100.00
Total Bits 0->1	10	10	100.00
Total Bits 1->0	10	10	100.00

Ports	10	10	100.00
Port Bits	20	20	100.00
Port Bits 0->1	10	10	100.00
Port Bits 1->0	10	10	100.00

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
clk_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
rst_ni	Yes	Yes	T4,T26,T27	Yes	T1,T2,T3	INPUT
alert_test_i	Yes	Yes	T120,T121,T122	Yes	T120,T121,T122	INPUT
alert_req_i	Yes	Yes	T18,T4,T70	Yes	T18,T4,T70	INPUT
alert_ack_o	Yes	Yes	T18,T4,T70	Yes	T18,T4,T70	OUTPUT
alert_state_o	Yes	Yes	T18,T4,T70	Yes	T18,T4,T70	OUTPUT
alert_rx_i.ack_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
alert_rx_i.ack_p	Yes	Yes	T18,T4,T70	Yes	T18,T4,T70	INPUT
alert_rx_i.ping_n	Unreachable	Unreachable		Unreachable		INPUT
alert_rx_i.ping_p	Unreachable	Unreachable		Unreachable		INPUT
alert_tx_o.alert_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
alert_tx_o.alert_p	Yes	Yes	T18,T4,T70	Yes	T18,T4,T70	OUTPUT

Toggle Coverage for Instance : tb.dut.gen_alert_senders[4].u_alert_sender

	Total	Covered	Percent
Totals	9	7	77.78
Total Bits	18	14	77.78
Total Bits 0->1	9	7	77.78
Total Bits 1->0	9	7	77.78

Ports	9	7	77.78
Port Bits	18	14	77.78
Port Bits 0->1	9	7	77.78
Port Bits 1->0	9	7	77.78

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
clk_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
rst_ni	Yes	Yes	T4,T26,T27	Yes	T1,T2,T3	INPUT
alert_test_i	Yes	Yes	T120,T121,T122	Yes	T120,T121,T122	INPUT
alert_req_i	Unreachable	Unreachable		Unreachable		INPUT
alert_ack_o	No	No		No		OUTPUT
alert_state_o	No	No		No		OUTPUT
alert_rx_i.ack_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
alert_rx_i.ack_p	Yes	Yes	T120,T121,T122	Yes	T120,T121,T122	INPUT
alert_rx_i.ping_n	Unreachable	Unreachable		Unreachable		INPUT
alert_rx_i.ping_p	Unreachable	Unreachable		Unreachable		INPUT
alert_tx_o.alert_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
alert_tx_o.alert_p	Yes	Yes	T120,T121,T122	Yes	T120,T121,T122	OUTPUT

Toggle Coverage for Instance : tb.dut.gen_alert_senders[0].u_alert_sender

	Total	Covered	Percent
Totals	10	10	100.00
Total Bits	20	20	100.00
Total Bits 0->1	10	10	100.00
Total Bits 1->0	10	10	100.00

Ports	10	10	100.00
Port Bits	20	20	100.00
Port Bits 0->1	10	10	100.00
Port Bits 1->0	10	10	100.00

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
clk_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
rst_ni	Yes	Yes	T4,T26,T27	Yes	T1,T2,T3	INPUT
alert_test_i	Yes	Yes	T120,T121,T122	Yes	T120,T121,T122	INPUT
alert_req_i	Yes	Yes	T18,T70,T11	Yes	T18,T70,T11	INPUT
alert_ack_o	Yes	Yes	T18,T70,T11	Yes	T18,T70,T11	OUTPUT
alert_state_o	Yes	Yes	T18,T70,T11	Yes	T18,T70,T11	OUTPUT
alert_rx_i.ack_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
alert_rx_i.ack_p	Yes	Yes	T18,T70,T11	Yes	T18,T70,T11	INPUT
alert_rx_i.ping_n	Unreachable	Unreachable		Unreachable		INPUT
alert_rx_i.ping_p	Unreachable	Unreachable		Unreachable		INPUT
alert_tx_o.alert_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
alert_tx_o.alert_p	Yes	Yes	T18,T70,T11	Yes	T18,T70,T11	OUTPUT

Toggle Coverage for Instance : tb.dut.gen_alert_senders[1].u_alert_sender

	Total	Covered	Percent
Totals	10	10	100.00
Total Bits	20	20	100.00
Total Bits 0->1	10	10	100.00
Total Bits 1->0	10	10	100.00

Ports	10	10	100.00
Port Bits	20	20	100.00
Port Bits 0->1	10	10	100.00
Port Bits 1->0	10	10	100.00

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
clk_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
rst_ni	Yes	Yes	T4,T26,T27	Yes	T1,T2,T3	INPUT
alert_test_i	Yes	Yes	T120,T121,T122	Yes	T120,T121,T122	INPUT
alert_req_i	Yes	Yes	T6,T138,T31	Yes	T6,T7,T138	INPUT
alert_ack_o	Yes	Yes	T6,T7,T31	Yes	T6,T7,T31	OUTPUT
alert_state_o	Yes	Yes	T6,T138,T31	Yes	T6,T7,T138	OUTPUT
alert_rx_i.ack_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
alert_rx_i.ack_p	Yes	Yes	T6,T7,T120	Yes	T6,T7,T120	INPUT
alert_rx_i.ping_n	Unreachable	Unreachable		Unreachable		INPUT
alert_rx_i.ping_p	Unreachable	Unreachable		Unreachable		INPUT
alert_tx_o.alert_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
alert_tx_o.alert_p	Yes	Yes	T6,T7,T138	Yes	T6,T7,T138	OUTPUT

Toggle Coverage for Instance : tb.dut.gen_alert_senders[2].u_alert_sender

	Total	Covered	Percent
Totals	10	10	100.00
Total Bits	20	20	100.00
Total Bits 0->1	10	10	100.00
Total Bits 1->0	10	10	100.00

Ports	10	10	100.00
Port Bits	20	20	100.00
Port Bits 0->1	10	10	100.00
Port Bits 1->0	10	10	100.00

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
clk_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
rst_ni	Yes	Yes	T4,T26,T27	Yes	T1,T2,T3	INPUT
alert_test_i	Yes	Yes	T120,T121,T122	Yes	T120,T121,T122	INPUT
alert_req_i	Yes	Yes	T4,T40,T41	Yes	T4,T40,T41	INPUT
alert_ack_o	Yes	Yes	T4,T40,T41	Yes	T4,T40,T41	OUTPUT
alert_state_o	Yes	Yes	T4,T40,T41	Yes	T4,T40,T41	OUTPUT
alert_rx_i.ack_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
alert_rx_i.ack_p	Yes	Yes	T4,T40,T41	Yes	T4,T40,T41	INPUT
alert_rx_i.ping_n	Unreachable	Unreachable		Unreachable		INPUT
alert_rx_i.ping_p	Unreachable	Unreachable		Unreachable		INPUT
alert_tx_o.alert_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
alert_tx_o.alert_p	Yes	Yes	T4,T40,T41	Yes	T4,T40,T41	OUTPUT

Toggle Coverage for Instance : tb.dut.gen_alert_senders[3].u_alert_sender

	Total	Covered	Percent
Totals	10	10	100.00
Total Bits	20	20	100.00
Total Bits 0->1	10	10	100.00
Total Bits 1->0	10	10	100.00

Ports	10	10	100.00
Port Bits	20	20	100.00
Port Bits 0->1	10	10	100.00
Port Bits 1->0	10	10	100.00

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
clk_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
rst_ni	Yes	Yes	T4,T26,T27	Yes	T1,T2,T3	INPUT
alert_test_i	Yes	Yes	T120,T121,T122	Yes	T120,T121,T122	INPUT
alert_req_i	Yes	Yes	T12,T13,T14	Yes	T12,T13,T14	INPUT
alert_ack_o	Yes	Yes	T259,T260,T261	Yes	T259,T260,T261	OUTPUT
alert_state_o	Yes	Yes	T12,T13,T14	Yes	T12,T13,T14	OUTPUT
alert_rx_i.ack_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
alert_rx_i.ack_p	Yes	Yes	T120,T121,T122	Yes	T120,T121,T122	INPUT
alert_rx_i.ping_n	Unreachable	Unreachable		Unreachable		INPUT
alert_rx_i.ping_p	Unreachable	Unreachable		Unreachable		INPUT
alert_tx_o.alert_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
alert_tx_o.alert_p	Yes	Yes	T120,T121,T122	Yes	T120,T121,T122	OUTPUT