Module Definition
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Module : tlul_data_integ_enc
SCORELINECONDTOGGLEFSMBRANCHASSERT

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_09_10/flash_ctrl-sim-vcs/default/sim-vcs/../src/lowrisc_tlul_trans_intg_0.1/rtl/tlul_data_integ_enc.sv

Module self-instances :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
tb.dut.u_reg_core.u_socket.gen_err_resp.err_resp.u_intg_gen.gen_data_intg.u_tlul_data_integ_enc
tb.dut.u_reg_core.u_reg_if.u_rsp_intg_gen.gen_data_intg.u_tlul_data_integ_enc
tb.dut.u_flash_hw_if.u_bus_intg
tb.dut.u_prog_tl_gate.u_tlul_err_resp.u_intg_gen.gen_data_intg.u_tlul_data_integ_enc
tb.dut.u_to_prog_fifo.u_tlul_data_integ_enc_instr
tb.dut.u_to_prog_fifo.u_tlul_data_integ_enc_data
tb.dut.u_to_rd_fifo.u_tlul_data_integ_enc_instr
tb.dut.u_to_rd_fifo.u_tlul_data_integ_enc_data
tb.dut.u_flash_ctrl_rd.u_bus_intg
tb.dut.u_tl_gate.u_tlul_err_resp.u_intg_gen.gen_data_intg.u_tlul_data_integ_enc
tb.dut.u_tl_adapter_eflash.u_tlul_data_integ_enc_instr
tb.dut.u_tl_adapter_eflash.u_tlul_data_integ_enc_data
tb.dut.u_eflash.u_flash.gen_generic.u_impl_generic.u_reg_top.u_rsp_intg_gen.gen_data_intg.u_tlul_data_integ_enc
tb.dut.u_eflash.gen_flash_cores[0].u_core.u_rd.u_bus_inv_data_intg
tb.dut.u_eflash.gen_flash_cores[0].u_core.u_rd.gen_rd.gen_bus_words_intg[0].u_bus_intg
tb.dut.u_eflash.gen_flash_cores[0].u_core.u_rd.gen_rd.gen_bus_words_intg[1].u_bus_intg
tb.dut.u_eflash.gen_flash_cores[1].u_core.u_rd.u_bus_inv_data_intg
tb.dut.u_eflash.gen_flash_cores[1].u_core.u_rd.gen_rd.gen_bus_words_intg[0].u_bus_intg
tb.dut.u_eflash.gen_flash_cores[1].u_core.u_rd.gen_rd.gen_bus_words_intg[1].u_bus_intg



Module Instance : tb.dut.u_reg_core.u_socket.gen_err_resp.err_resp.u_intg_gen.gen_data_intg.u_tlul_data_integ_enc

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 u_intg_gen


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
u_data_gen 100.00 100.00



Module Instance : tb.dut.u_reg_core.u_reg_if.u_rsp_intg_gen.gen_data_intg.u_tlul_data_integ_enc

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
90.00 80.00 100.00 u_rsp_intg_gen


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
u_data_gen 100.00 100.00



Module Instance : tb.dut.u_flash_hw_if.u_bus_intg

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
96.58 99.17 94.79 92.11 96.81 100.00 u_flash_hw_if


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
u_data_gen 100.00 100.00



Module Instance : tb.dut.u_prog_tl_gate.u_tlul_err_resp.u_intg_gen.gen_data_intg.u_tlul_data_integ_enc

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 u_intg_gen


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
u_data_gen 100.00 100.00



Module Instance : tb.dut.u_to_prog_fifo.u_tlul_data_integ_enc_instr

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
0.00 0.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
78.34 92.65 64.66 71.43 84.62 u_to_prog_fifo


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
u_data_gen 0.00 0.00



Module Instance : tb.dut.u_to_prog_fifo.u_tlul_data_integ_enc_data

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
0.00 0.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
78.34 92.65 64.66 71.43 84.62 u_to_prog_fifo


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
u_data_gen 0.00 0.00



Module Instance : tb.dut.u_to_rd_fifo.u_tlul_data_integ_enc_instr

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
0.00 0.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
88.86 95.83 73.39 86.21 100.00 u_to_rd_fifo


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
u_data_gen 0.00 0.00



Module Instance : tb.dut.u_to_rd_fifo.u_tlul_data_integ_enc_data

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
0.00 0.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
88.86 95.83 73.39 86.21 100.00 u_to_rd_fifo


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
u_data_gen 0.00 0.00



Module Instance : tb.dut.u_flash_ctrl_rd.u_bus_intg

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
0.00 0.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
96.86 100.00 96.97 100.00 90.48 u_flash_ctrl_rd


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
u_data_gen 0.00 0.00



Module Instance : tb.dut.u_tl_gate.u_tlul_err_resp.u_intg_gen.gen_data_intg.u_tlul_data_integ_enc

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 u_intg_gen


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
u_data_gen 100.00 100.00



Module Instance : tb.dut.u_tl_adapter_eflash.u_tlul_data_integ_enc_instr

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
0.00 0.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
91.44 97.18 78.91 89.66 100.00 u_tl_adapter_eflash


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
u_data_gen 0.00 0.00



Module Instance : tb.dut.u_tl_adapter_eflash.u_tlul_data_integ_enc_data

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
0.00 0.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
91.44 97.18 78.91 89.66 100.00 u_tl_adapter_eflash


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
u_data_gen 0.00 0.00



Module Instance : tb.dut.u_eflash.u_flash.gen_generic.u_impl_generic.u_reg_top.u_rsp_intg_gen.gen_data_intg.u_tlul_data_integ_enc

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 u_rsp_intg_gen


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
u_data_gen 100.00 100.00



Module Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_rd.u_bus_inv_data_intg

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
0.00 0.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
98.09 100.00 92.36 100.00 100.00 u_rd


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
u_data_gen 0.00 0.00



Module Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_rd.gen_rd.gen_bus_words_intg[0].u_bus_intg

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
98.09 100.00 92.36 100.00 100.00 u_rd


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
u_data_gen 100.00 100.00



Module Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_rd.gen_rd.gen_bus_words_intg[1].u_bus_intg

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
98.09 100.00 92.36 100.00 100.00 u_rd


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
u_data_gen 100.00 100.00



Module Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_rd.u_bus_inv_data_intg

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
0.00 0.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
97.71 100.00 90.83 100.00 100.00 u_rd


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
u_data_gen 0.00 0.00



Module Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_rd.gen_rd.gen_bus_words_intg[0].u_bus_intg

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
97.71 100.00 90.83 100.00 100.00 u_rd


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
u_data_gen 100.00 100.00



Module Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_rd.gen_rd.gen_bus_words_intg[1].u_bus_intg

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
97.71 100.00 90.83 100.00 100.00 u_rd


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
u_data_gen 100.00 100.00

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