Unified Coverage Report :: Module Instance :: tb.dut.u_reg_core.u_socket.fifo_h.reqfifo

Module Instance : tb.dut.u_reg_core.u_socket.fifo_h.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		fifo_h

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_reg_core.u_socket.fifo_h.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		fifo_h

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_reg_core.u_socket.gen_dfifo[0].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[0].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_reg_core.u_socket.gen_dfifo[0].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[0].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_reg_core.u_socket.gen_dfifo[1].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[1].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Instance : tb.dut.u_reg_core.u_socket.fifo_h.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

43                          // device facing
44         1/1              assign rvalid_o = wvalid_i;
           Tests:       T1 T2 T3 
45         1/1              assign rdata_o = wdata_i;
           Tests:       T1 T2 T3 
46                      
47                          // host facing
48         1/1              assign wready_o = rready_i;
           Tests:       T1 T2 T3 
49         1/1              assign full_o = rready_i;
           Tests:       T1 T2 T3 
50                      
51                          // this avoids lint warnings
52                          logic unused_clr;
53         unreachable      assign unused_clr = clr_i;

---

Assert Coverage for Instance : tb.dut.u_reg_core.u_socket.fifo_h.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	385925313	34119604	0	0
DepthKnown_A	385925313	385008202	0	0
RvalidKnown_A	385925313	385008202	0	0
WreadyKnown_A	385925313	385008202	0	0
gen_passthru_fifo.paramCheckPass	1273	1273	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	385925313	34119604	0	0
T1	1179	20	0	0
T2	1863	420	0	0
T3	12423	4039	0	0
T8	1936	295	0	0
T13	3647	1298	0	0
T14	2209	527	0	0
T15	1510	240	0	0
T16	2371	537	0	0
T17	197029	17839	0	0
T18	1469	539	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	385925313	385008202	0	0
T1	1179	1082	0	0
T2	1863	1767	0	0
T3	12423	12335	0	0
T8	1936	1859	0	0
T13	3647	3552	0	0
T14	2209	2132	0	0
T15	1510	1455	0	0
T16	2371	2298	0	0
T17	197029	196939	0	0
T18	1469	1384	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	385925313	385008202	0	0
T1	1179	1082	0	0
T2	1863	1767	0	0
T3	12423	12335	0	0
T8	1936	1859	0	0
T13	3647	3552	0	0
T14	2209	2132	0	0
T15	1510	1455	0	0
T16	2371	2298	0	0
T17	197029	196939	0	0
T18	1469	1384	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	385925313	385008202	0	0
T1	1179	1082	0	0
T2	1863	1767	0	0
T3	12423	12335	0	0
T8	1936	1859	0	0
T13	3647	3552	0	0
T14	2209	2132	0	0
T15	1510	1455	0	0
T16	2371	2298	0	0
T17	197029	196939	0	0
T18	1469	1384	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	1273	1273	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T8	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0

Line Coverage for Instance : tb.dut.u_reg_core.u_socket.fifo_h.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

43                          // device facing
44         1/1              assign rvalid_o = wvalid_i;
           Tests:       T1 T2 T3 
45         1/1              assign rdata_o = wdata_i;
           Tests:       T1 T2 T3 
46                      
47                          // host facing
48         1/1              assign wready_o = rready_i;
           Tests:       T1 T2 T3 
49         1/1              assign full_o = rready_i;
           Tests:       T1 T2 T3 
50                      
51                          // this avoids lint warnings
52                          logic unused_clr;
53         unreachable      assign unused_clr = clr_i;

---

Assert Coverage for Instance : tb.dut.u_reg_core.u_socket.fifo_h.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	385925313	44864746	0	0
DepthKnown_A	385925313	385008202	0	0
RvalidKnown_A	385925313	385008202	0	0
WreadyKnown_A	385925313	385008202	0	0
gen_passthru_fifo.paramCheckPass	1273	1273	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	385925313	44864746	0	0
T1	1179	45	0	0
T2	1863	364	0	0
T3	12423	4039	0	0
T8	1936	295	0	0
T13	3647	1298	0	0
T14	2209	527	0	0
T15	1510	240	0	0
T16	2371	537	0	0
T17	197029	80141	0	0
T18	1469	539	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	385925313	385008202	0	0
T1	1179	1082	0	0
T2	1863	1767	0	0
T3	12423	12335	0	0
T8	1936	1859	0	0
T13	3647	3552	0	0
T14	2209	2132	0	0
T15	1510	1455	0	0
T16	2371	2298	0	0
T17	197029	196939	0	0
T18	1469	1384	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	385925313	385008202	0	0
T1	1179	1082	0	0
T2	1863	1767	0	0
T3	12423	12335	0	0
T8	1936	1859	0	0
T13	3647	3552	0	0
T14	2209	2132	0	0
T15	1510	1455	0	0
T16	2371	2298	0	0
T17	197029	196939	0	0
T18	1469	1384	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	385925313	385008202	0	0
T1	1179	1082	0	0
T2	1863	1767	0	0
T3	12423	12335	0	0
T8	1936	1859	0	0
T13	3647	3552	0	0
T14	2209	2132	0	0
T15	1510	1455	0	0
T16	2371	2298	0	0
T17	197029	196939	0	0
T18	1469	1384	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	1273	1273	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T8	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0

Line Coverage for Instance : tb.dut.u_reg_core.u_socket.gen_dfifo[0].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

43                          // device facing
44         1/1              assign rvalid_o = wvalid_i;
           Tests:       T2 T3 T8 
45         1/1              assign rdata_o = wdata_i;
           Tests:       T1 T2 T3 
46                      
47                          // host facing
48         1/1              assign wready_o = rready_i;
           Tests:       T1 T2 T3 
49         1/1              assign full_o = rready_i;
           Tests:       T1 T2 T3 
50                      
51                          // this avoids lint warnings
52                          logic unused_clr;
53         unreachable      assign unused_clr = clr_i;

---

Assert Coverage for Instance : tb.dut.u_reg_core.u_socket.gen_dfifo[0].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	385925313	2178867	0	0
DepthKnown_A	385925313	385008202	0	0
RvalidKnown_A	385925313	385008202	0	0
WreadyKnown_A	385925313	385008202	0	0
gen_passthru_fifo.paramCheckPass	1273	1273	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	385925313	2178867	0	0
T2	1863	54	0	0
T3	12423	0	0	0
T8	1936	11	0	0
T9	0	1478	0	0
T13	3647	78	0	0
T14	2209	0	0	0
T15	1510	0	0	0
T16	2371	0	0	0
T17	197029	1016	0	0
T18	1469	0	0	0
T29	90574	145	0	0
T32	0	640	0	0
T58	0	1840	0	0
T65	0	50	0	0
T71	0	26	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	385925313	385008202	0	0
T1	1179	1082	0	0
T2	1863	1767	0	0
T3	12423	12335	0	0
T8	1936	1859	0	0
T13	3647	3552	0	0
T14	2209	2132	0	0
T15	1510	1455	0	0
T16	2371	2298	0	0
T17	197029	196939	0	0
T18	1469	1384	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	385925313	385008202	0	0
T1	1179	1082	0	0
T2	1863	1767	0	0
T3	12423	12335	0	0
T8	1936	1859	0	0
T13	3647	3552	0	0
T14	2209	2132	0	0
T15	1510	1455	0	0
T16	2371	2298	0	0
T17	197029	196939	0	0
T18	1469	1384	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	385925313	385008202	0	0
T1	1179	1082	0	0
T2	1863	1767	0	0
T3	12423	12335	0	0
T8	1936	1859	0	0
T13	3647	3552	0	0
T14	2209	2132	0	0
T15	1510	1455	0	0
T16	2371	2298	0	0
T17	197029	196939	0	0
T18	1469	1384	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	1273	1273	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T8	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0

Line Coverage for Instance : tb.dut.u_reg_core.u_socket.gen_dfifo[0].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

43                          // device facing
44         1/1              assign rvalid_o = wvalid_i;
           Tests:       T1 T2 T3 
45         1/1              assign rdata_o = wdata_i;
           Tests:       T1 T2 T3 
46                      
47                          // host facing
48         1/1              assign wready_o = rready_i;
           Tests:       T1 T2 T3 
49         1/1              assign full_o = rready_i;
           Tests:       T1 T2 T3 
50                      
51                          // this avoids lint warnings
52                          logic unused_clr;
53         unreachable      assign unused_clr = clr_i;

---

Assert Coverage for Instance : tb.dut.u_reg_core.u_socket.gen_dfifo[0].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	385925313	3648360	0	0
DepthKnown_A	385925313	385008202	0	0
RvalidKnown_A	385925313	385008202	0	0
WreadyKnown_A	385925313	385008202	0	0
gen_passthru_fifo.paramCheckPass	1273	1273	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	385925313	3648360	0	0
T2	1863	10	0	0
T3	12423	0	0	0
T8	1936	11	0	0
T9	0	1478	0	0
T13	3647	78	0	0
T14	2209	0	0	0
T15	1510	0	0	0
T16	2371	0	0	0
T17	197029	4531	0	0
T18	1469	0	0	0
T29	90574	444	0	0
T32	0	640	0	0
T58	0	1840	0	0
T65	0	50	0	0
T71	0	26	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	385925313	385008202	0	0
T1	1179	1082	0	0
T2	1863	1767	0	0
T3	12423	12335	0	0
T8	1936	1859	0	0
T13	3647	3552	0	0
T14	2209	2132	0	0
T15	1510	1455	0	0
T16	2371	2298	0	0
T17	197029	196939	0	0
T18	1469	1384	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	385925313	385008202	0	0
T1	1179	1082	0	0
T2	1863	1767	0	0
T3	12423	12335	0	0
T8	1936	1859	0	0
T13	3647	3552	0	0
T14	2209	2132	0	0
T15	1510	1455	0	0
T16	2371	2298	0	0
T17	197029	196939	0	0
T18	1469	1384	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	385925313	385008202	0	0
T1	1179	1082	0	0
T2	1863	1767	0	0
T3	12423	12335	0	0
T8	1936	1859	0	0
T13	3647	3552	0	0
T14	2209	2132	0	0
T15	1510	1455	0	0
T16	2371	2298	0	0
T17	197029	196939	0	0
T18	1469	1384	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	1273	1273	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T8	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0

Line Coverage for Instance : tb.dut.u_reg_core.u_socket.gen_dfifo[1].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

43                          // device facing
44         1/1              assign rvalid_o = wvalid_i;
           Tests:       T2 T3 T8 
45         1/1              assign rdata_o = wdata_i;
           Tests:       T1 T2 T3 
46                      
47                          // host facing
48         1/1              assign wready_o = rready_i;
           Tests:       T1 T2 T3 
49         1/1              assign full_o = rready_i;
           Tests:       T1 T2 T3 
50                      
51                          // this avoids lint warnings
52                          logic unused_clr;
53         unreachable      assign unused_clr = clr_i;

---

Assert Coverage for Instance : tb.dut.u_reg_core.u_socket.gen_dfifo[1].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	385925313	3765154	0	0
DepthKnown_A	385925313	385008202	0	0
RvalidKnown_A	385925313	385008202	0	0
WreadyKnown_A	385925313	385008202	0	0
gen_passthru_fifo.paramCheckPass	1273	1273	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	385925313	3765154	0	0
T2	1863	32	0	0
T3	12423	638	0	0
T8	1936	11	0	0
T13	3647	0	0	0
T14	2209	146	0	0
T15	1510	0	0	0
T16	2371	146	0	0
T17	197029	2424	0	0
T18	1469	146	0	0
T29	90574	47	0	0
T32	0	1451	0	0
T58	0	3792	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	385925313	385008202	0	0
T1	1179	1082	0	0
T2	1863	1767	0	0
T3	12423	12335	0	0
T8	1936	1859	0	0
T13	3647	3552	0	0
T14	2209	2132	0	0
T15	1510	1455	0	0
T16	2371	2298	0	0
T17	197029	196939	0	0
T18	1469	1384	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	385925313	385008202	0	0
T1	1179	1082	0	0
T2	1863	1767	0	0
T3	12423	12335	0	0
T8	1936	1859	0	0
T13	3647	3552	0	0
T14	2209	2132	0	0
T15	1510	1455	0	0
T16	2371	2298	0	0
T17	197029	196939	0	0
T18	1469	1384	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	385925313	385008202	0	0
T1	1179	1082	0	0
T2	1863	1767	0	0
T3	12423	12335	0	0
T8	1936	1859	0	0
T13	3647	3552	0	0
T14	2209	2132	0	0
T15	1510	1455	0	0
T16	2371	2298	0	0
T17	197029	196939	0	0
T18	1469	1384	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	1273	1273	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T8	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0