Line Coverage for Instance : tb.dut.u_reg_core.u_socket.fifo_h.reqfifo
| Line No. | Total | Covered | Percent |
TOTAL | | 4 | 4 | 100.00 |
CONT_ASSIGN | 44 | 1 | 1 | 100.00 |
CONT_ASSIGN | 45 | 1 | 1 | 100.00 |
CONT_ASSIGN | 48 | 1 | 1 | 100.00 |
CONT_ASSIGN | 49 | 1 | 1 | 100.00 |
CONT_ASSIGN | 53 | 0 | 0 | |
43 // device facing
44 1/1 assign rvalid_o = wvalid_i;
Tests: T1 T2 T3
45 1/1 assign rdata_o = wdata_i;
Tests: T1 T2 T3
46
47 // host facing
48 1/1 assign wready_o = rready_i;
Tests: T1 T2 T3
49 1/1 assign full_o = rready_i;
Tests: T1 T2 T3
50
51 // this avoids lint warnings
52 logic unused_clr;
53 unreachable assign unused_clr = clr_i;
Assert Coverage for Instance : tb.dut.u_reg_core.u_socket.fifo_h.reqfifo
Assertion Details
DataKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
393570196 |
37821817 |
0 |
0 |
T1 |
2070 |
526 |
0 |
0 |
T2 |
3480 |
1298 |
0 |
0 |
T3 |
1887 |
537 |
0 |
0 |
T4 |
4370 |
386 |
0 |
0 |
T5 |
677 |
116 |
0 |
0 |
T8 |
45213 |
3761 |
0 |
0 |
T9 |
1406 |
61 |
0 |
0 |
T10 |
2124 |
154 |
0 |
0 |
T16 |
1541 |
594 |
0 |
0 |
T17 |
1625 |
58 |
0 |
0 |
DataKnown_AKnownEnable
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
393570196 |
392677850 |
0 |
0 |
T1 |
2070 |
1970 |
0 |
0 |
T2 |
3480 |
3381 |
0 |
0 |
T3 |
1887 |
1822 |
0 |
0 |
T4 |
4370 |
3912 |
0 |
0 |
T5 |
677 |
579 |
0 |
0 |
T8 |
45213 |
45151 |
0 |
0 |
T9 |
1406 |
1318 |
0 |
0 |
T10 |
2124 |
2046 |
0 |
0 |
T16 |
1541 |
1471 |
0 |
0 |
T17 |
1625 |
1542 |
0 |
0 |
DepthKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
393570196 |
392677850 |
0 |
0 |
T1 |
2070 |
1970 |
0 |
0 |
T2 |
3480 |
3381 |
0 |
0 |
T3 |
1887 |
1822 |
0 |
0 |
T4 |
4370 |
3912 |
0 |
0 |
T5 |
677 |
579 |
0 |
0 |
T8 |
45213 |
45151 |
0 |
0 |
T9 |
1406 |
1318 |
0 |
0 |
T10 |
2124 |
2046 |
0 |
0 |
T16 |
1541 |
1471 |
0 |
0 |
T17 |
1625 |
1542 |
0 |
0 |
RvalidKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
393570196 |
392677850 |
0 |
0 |
T1 |
2070 |
1970 |
0 |
0 |
T2 |
3480 |
3381 |
0 |
0 |
T3 |
1887 |
1822 |
0 |
0 |
T4 |
4370 |
3912 |
0 |
0 |
T5 |
677 |
579 |
0 |
0 |
T8 |
45213 |
45151 |
0 |
0 |
T9 |
1406 |
1318 |
0 |
0 |
T10 |
2124 |
2046 |
0 |
0 |
T16 |
1541 |
1471 |
0 |
0 |
T17 |
1625 |
1542 |
0 |
0 |
WreadyKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
393570196 |
392677850 |
0 |
0 |
T1 |
2070 |
1970 |
0 |
0 |
T2 |
3480 |
3381 |
0 |
0 |
T3 |
1887 |
1822 |
0 |
0 |
T4 |
4370 |
3912 |
0 |
0 |
T5 |
677 |
579 |
0 |
0 |
T8 |
45213 |
45151 |
0 |
0 |
T9 |
1406 |
1318 |
0 |
0 |
T10 |
2124 |
2046 |
0 |
0 |
T16 |
1541 |
1471 |
0 |
0 |
T17 |
1625 |
1542 |
0 |
0 |
gen_passthru_fifo.paramCheckPass
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
1266 |
1266 |
0 |
0 |
T1 |
1 |
1 |
0 |
0 |
T2 |
1 |
1 |
0 |
0 |
T3 |
1 |
1 |
0 |
0 |
T4 |
1 |
1 |
0 |
0 |
T5 |
1 |
1 |
0 |
0 |
T8 |
1 |
1 |
0 |
0 |
T9 |
1 |
1 |
0 |
0 |
T10 |
1 |
1 |
0 |
0 |
T16 |
1 |
1 |
0 |
0 |
T17 |
1 |
1 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_reg_core.u_socket.fifo_h.rspfifo
| Line No. | Total | Covered | Percent |
TOTAL | | 4 | 4 | 100.00 |
CONT_ASSIGN | 44 | 1 | 1 | 100.00 |
CONT_ASSIGN | 45 | 1 | 1 | 100.00 |
CONT_ASSIGN | 48 | 1 | 1 | 100.00 |
CONT_ASSIGN | 49 | 1 | 1 | 100.00 |
CONT_ASSIGN | 53 | 0 | 0 | |
43 // device facing
44 1/1 assign rvalid_o = wvalid_i;
Tests: T1 T2 T3
45 1/1 assign rdata_o = wdata_i;
Tests: T1 T2 T3
46
47 // host facing
48 1/1 assign wready_o = rready_i;
Tests: T1 T2 T3
49 1/1 assign full_o = rready_i;
Tests: T1 T2 T3
50
51 // this avoids lint warnings
52 logic unused_clr;
53 unreachable assign unused_clr = clr_i;
Assert Coverage for Instance : tb.dut.u_reg_core.u_socket.fifo_h.rspfifo
Assertion Details
DataKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
393570196 |
44142033 |
0 |
0 |
T1 |
2070 |
526 |
0 |
0 |
T2 |
3480 |
1298 |
0 |
0 |
T3 |
1887 |
537 |
0 |
0 |
T4 |
4370 |
380 |
0 |
0 |
T5 |
677 |
116 |
0 |
0 |
T8 |
45213 |
16883 |
0 |
0 |
T9 |
1406 |
61 |
0 |
0 |
T10 |
2124 |
153 |
0 |
0 |
T16 |
1541 |
594 |
0 |
0 |
T17 |
1625 |
58 |
0 |
0 |
DataKnown_AKnownEnable
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
393570196 |
392677850 |
0 |
0 |
T1 |
2070 |
1970 |
0 |
0 |
T2 |
3480 |
3381 |
0 |
0 |
T3 |
1887 |
1822 |
0 |
0 |
T4 |
4370 |
3912 |
0 |
0 |
T5 |
677 |
579 |
0 |
0 |
T8 |
45213 |
45151 |
0 |
0 |
T9 |
1406 |
1318 |
0 |
0 |
T10 |
2124 |
2046 |
0 |
0 |
T16 |
1541 |
1471 |
0 |
0 |
T17 |
1625 |
1542 |
0 |
0 |
DepthKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
393570196 |
392677850 |
0 |
0 |
T1 |
2070 |
1970 |
0 |
0 |
T2 |
3480 |
3381 |
0 |
0 |
T3 |
1887 |
1822 |
0 |
0 |
T4 |
4370 |
3912 |
0 |
0 |
T5 |
677 |
579 |
0 |
0 |
T8 |
45213 |
45151 |
0 |
0 |
T9 |
1406 |
1318 |
0 |
0 |
T10 |
2124 |
2046 |
0 |
0 |
T16 |
1541 |
1471 |
0 |
0 |
T17 |
1625 |
1542 |
0 |
0 |
RvalidKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
393570196 |
392677850 |
0 |
0 |
T1 |
2070 |
1970 |
0 |
0 |
T2 |
3480 |
3381 |
0 |
0 |
T3 |
1887 |
1822 |
0 |
0 |
T4 |
4370 |
3912 |
0 |
0 |
T5 |
677 |
579 |
0 |
0 |
T8 |
45213 |
45151 |
0 |
0 |
T9 |
1406 |
1318 |
0 |
0 |
T10 |
2124 |
2046 |
0 |
0 |
T16 |
1541 |
1471 |
0 |
0 |
T17 |
1625 |
1542 |
0 |
0 |
WreadyKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
393570196 |
392677850 |
0 |
0 |
T1 |
2070 |
1970 |
0 |
0 |
T2 |
3480 |
3381 |
0 |
0 |
T3 |
1887 |
1822 |
0 |
0 |
T4 |
4370 |
3912 |
0 |
0 |
T5 |
677 |
579 |
0 |
0 |
T8 |
45213 |
45151 |
0 |
0 |
T9 |
1406 |
1318 |
0 |
0 |
T10 |
2124 |
2046 |
0 |
0 |
T16 |
1541 |
1471 |
0 |
0 |
T17 |
1625 |
1542 |
0 |
0 |
gen_passthru_fifo.paramCheckPass
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
1266 |
1266 |
0 |
0 |
T1 |
1 |
1 |
0 |
0 |
T2 |
1 |
1 |
0 |
0 |
T3 |
1 |
1 |
0 |
0 |
T4 |
1 |
1 |
0 |
0 |
T5 |
1 |
1 |
0 |
0 |
T8 |
1 |
1 |
0 |
0 |
T9 |
1 |
1 |
0 |
0 |
T10 |
1 |
1 |
0 |
0 |
T16 |
1 |
1 |
0 |
0 |
T17 |
1 |
1 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_reg_core.u_socket.gen_dfifo[0].fifo_d.reqfifo
| Line No. | Total | Covered | Percent |
TOTAL | | 4 | 4 | 100.00 |
CONT_ASSIGN | 44 | 1 | 1 | 100.00 |
CONT_ASSIGN | 45 | 1 | 1 | 100.00 |
CONT_ASSIGN | 48 | 1 | 1 | 100.00 |
CONT_ASSIGN | 49 | 1 | 1 | 100.00 |
CONT_ASSIGN | 53 | 0 | 0 | |
43 // device facing
44 1/1 assign rvalid_o = wvalid_i;
Tests: T1 T2 T3
45 1/1 assign rdata_o = wdata_i;
Tests: T1 T2 T3
46
47 // host facing
48 1/1 assign wready_o = rready_i;
Tests: T1 T2 T3
49 1/1 assign full_o = rready_i;
Tests: T1 T2 T3
50
51 // this avoids lint warnings
52 logic unused_clr;
53 unreachable assign unused_clr = clr_i;
Assert Coverage for Instance : tb.dut.u_reg_core.u_socket.gen_dfifo[0].fifo_d.reqfifo
Assertion Details
DataKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
393570196 |
2094801 |
0 |
0 |
T2 |
3480 |
78 |
0 |
0 |
T3 |
1887 |
0 |
0 |
0 |
T4 |
4370 |
28 |
0 |
0 |
T5 |
677 |
0 |
0 |
0 |
T6 |
1297 |
153 |
0 |
0 |
T8 |
45213 |
0 |
0 |
0 |
T9 |
1406 |
0 |
0 |
0 |
T10 |
2124 |
10 |
0 |
0 |
T12 |
0 |
116 |
0 |
0 |
T16 |
1541 |
0 |
0 |
0 |
T17 |
1625 |
0 |
0 |
0 |
T20 |
0 |
16 |
0 |
0 |
T30 |
0 |
1070 |
0 |
0 |
T31 |
0 |
2 |
0 |
0 |
T48 |
0 |
830 |
0 |
0 |
T67 |
0 |
1222 |
0 |
0 |
DataKnown_AKnownEnable
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
393570196 |
392677850 |
0 |
0 |
T1 |
2070 |
1970 |
0 |
0 |
T2 |
3480 |
3381 |
0 |
0 |
T3 |
1887 |
1822 |
0 |
0 |
T4 |
4370 |
3912 |
0 |
0 |
T5 |
677 |
579 |
0 |
0 |
T8 |
45213 |
45151 |
0 |
0 |
T9 |
1406 |
1318 |
0 |
0 |
T10 |
2124 |
2046 |
0 |
0 |
T16 |
1541 |
1471 |
0 |
0 |
T17 |
1625 |
1542 |
0 |
0 |
DepthKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
393570196 |
392677850 |
0 |
0 |
T1 |
2070 |
1970 |
0 |
0 |
T2 |
3480 |
3381 |
0 |
0 |
T3 |
1887 |
1822 |
0 |
0 |
T4 |
4370 |
3912 |
0 |
0 |
T5 |
677 |
579 |
0 |
0 |
T8 |
45213 |
45151 |
0 |
0 |
T9 |
1406 |
1318 |
0 |
0 |
T10 |
2124 |
2046 |
0 |
0 |
T16 |
1541 |
1471 |
0 |
0 |
T17 |
1625 |
1542 |
0 |
0 |
RvalidKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
393570196 |
392677850 |
0 |
0 |
T1 |
2070 |
1970 |
0 |
0 |
T2 |
3480 |
3381 |
0 |
0 |
T3 |
1887 |
1822 |
0 |
0 |
T4 |
4370 |
3912 |
0 |
0 |
T5 |
677 |
579 |
0 |
0 |
T8 |
45213 |
45151 |
0 |
0 |
T9 |
1406 |
1318 |
0 |
0 |
T10 |
2124 |
2046 |
0 |
0 |
T16 |
1541 |
1471 |
0 |
0 |
T17 |
1625 |
1542 |
0 |
0 |
WreadyKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
393570196 |
392677850 |
0 |
0 |
T1 |
2070 |
1970 |
0 |
0 |
T2 |
3480 |
3381 |
0 |
0 |
T3 |
1887 |
1822 |
0 |
0 |
T4 |
4370 |
3912 |
0 |
0 |
T5 |
677 |
579 |
0 |
0 |
T8 |
45213 |
45151 |
0 |
0 |
T9 |
1406 |
1318 |
0 |
0 |
T10 |
2124 |
2046 |
0 |
0 |
T16 |
1541 |
1471 |
0 |
0 |
T17 |
1625 |
1542 |
0 |
0 |
gen_passthru_fifo.paramCheckPass
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
1266 |
1266 |
0 |
0 |
T1 |
1 |
1 |
0 |
0 |
T2 |
1 |
1 |
0 |
0 |
T3 |
1 |
1 |
0 |
0 |
T4 |
1 |
1 |
0 |
0 |
T5 |
1 |
1 |
0 |
0 |
T8 |
1 |
1 |
0 |
0 |
T9 |
1 |
1 |
0 |
0 |
T10 |
1 |
1 |
0 |
0 |
T16 |
1 |
1 |
0 |
0 |
T17 |
1 |
1 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_reg_core.u_socket.gen_dfifo[0].fifo_d.rspfifo
| Line No. | Total | Covered | Percent |
TOTAL | | 4 | 4 | 100.00 |
CONT_ASSIGN | 44 | 1 | 1 | 100.00 |
CONT_ASSIGN | 45 | 1 | 1 | 100.00 |
CONT_ASSIGN | 48 | 1 | 1 | 100.00 |
CONT_ASSIGN | 49 | 1 | 1 | 100.00 |
CONT_ASSIGN | 53 | 0 | 0 | |
43 // device facing
44 1/1 assign rvalid_o = wvalid_i;
Tests: T1 T2 T3
45 1/1 assign rdata_o = wdata_i;
Tests: T1 T2 T3
46
47 // host facing
48 1/1 assign wready_o = rready_i;
Tests: T1 T2 T3
49 1/1 assign full_o = rready_i;
Tests: T1 T2 T3
50
51 // this avoids lint warnings
52 logic unused_clr;
53 unreachable assign unused_clr = clr_i;
Assert Coverage for Instance : tb.dut.u_reg_core.u_socket.gen_dfifo[0].fifo_d.rspfifo
Assertion Details
DataKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
393570196 |
2857201 |
0 |
0 |
T2 |
3480 |
78 |
0 |
0 |
T3 |
1887 |
0 |
0 |
0 |
T4 |
4370 |
22 |
0 |
0 |
T5 |
677 |
0 |
0 |
0 |
T6 |
1297 |
28 |
0 |
0 |
T8 |
45213 |
0 |
0 |
0 |
T9 |
1406 |
0 |
0 |
0 |
T10 |
2124 |
10 |
0 |
0 |
T12 |
0 |
116 |
0 |
0 |
T16 |
1541 |
0 |
0 |
0 |
T17 |
1625 |
0 |
0 |
0 |
T20 |
0 |
16 |
0 |
0 |
T30 |
0 |
1070 |
0 |
0 |
T31 |
0 |
2 |
0 |
0 |
T48 |
0 |
830 |
0 |
0 |
T67 |
0 |
1222 |
0 |
0 |
DataKnown_AKnownEnable
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
393570196 |
392677850 |
0 |
0 |
T1 |
2070 |
1970 |
0 |
0 |
T2 |
3480 |
3381 |
0 |
0 |
T3 |
1887 |
1822 |
0 |
0 |
T4 |
4370 |
3912 |
0 |
0 |
T5 |
677 |
579 |
0 |
0 |
T8 |
45213 |
45151 |
0 |
0 |
T9 |
1406 |
1318 |
0 |
0 |
T10 |
2124 |
2046 |
0 |
0 |
T16 |
1541 |
1471 |
0 |
0 |
T17 |
1625 |
1542 |
0 |
0 |
DepthKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
393570196 |
392677850 |
0 |
0 |
T1 |
2070 |
1970 |
0 |
0 |
T2 |
3480 |
3381 |
0 |
0 |
T3 |
1887 |
1822 |
0 |
0 |
T4 |
4370 |
3912 |
0 |
0 |
T5 |
677 |
579 |
0 |
0 |
T8 |
45213 |
45151 |
0 |
0 |
T9 |
1406 |
1318 |
0 |
0 |
T10 |
2124 |
2046 |
0 |
0 |
T16 |
1541 |
1471 |
0 |
0 |
T17 |
1625 |
1542 |
0 |
0 |
RvalidKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
393570196 |
392677850 |
0 |
0 |
T1 |
2070 |
1970 |
0 |
0 |
T2 |
3480 |
3381 |
0 |
0 |
T3 |
1887 |
1822 |
0 |
0 |
T4 |
4370 |
3912 |
0 |
0 |
T5 |
677 |
579 |
0 |
0 |
T8 |
45213 |
45151 |
0 |
0 |
T9 |
1406 |
1318 |
0 |
0 |
T10 |
2124 |
2046 |
0 |
0 |
T16 |
1541 |
1471 |
0 |
0 |
T17 |
1625 |
1542 |
0 |
0 |
WreadyKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
393570196 |
392677850 |
0 |
0 |
T1 |
2070 |
1970 |
0 |
0 |
T2 |
3480 |
3381 |
0 |
0 |
T3 |
1887 |
1822 |
0 |
0 |
T4 |
4370 |
3912 |
0 |
0 |
T5 |
677 |
579 |
0 |
0 |
T8 |
45213 |
45151 |
0 |
0 |
T9 |
1406 |
1318 |
0 |
0 |
T10 |
2124 |
2046 |
0 |
0 |
T16 |
1541 |
1471 |
0 |
0 |
T17 |
1625 |
1542 |
0 |
0 |
gen_passthru_fifo.paramCheckPass
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
1266 |
1266 |
0 |
0 |
T1 |
1 |
1 |
0 |
0 |
T2 |
1 |
1 |
0 |
0 |
T3 |
1 |
1 |
0 |
0 |
T4 |
1 |
1 |
0 |
0 |
T5 |
1 |
1 |
0 |
0 |
T8 |
1 |
1 |
0 |
0 |
T9 |
1 |
1 |
0 |
0 |
T10 |
1 |
1 |
0 |
0 |
T16 |
1 |
1 |
0 |
0 |
T17 |
1 |
1 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_reg_core.u_socket.gen_dfifo[1].fifo_d.reqfifo
| Line No. | Total | Covered | Percent |
TOTAL | | 4 | 4 | 100.00 |
CONT_ASSIGN | 44 | 1 | 1 | 100.00 |
CONT_ASSIGN | 45 | 1 | 1 | 100.00 |
CONT_ASSIGN | 48 | 1 | 1 | 100.00 |
CONT_ASSIGN | 49 | 1 | 1 | 100.00 |
CONT_ASSIGN | 53 | 0 | 0 | |
43 // device facing
44 1/1 assign rvalid_o = wvalid_i;
Tests: T1 T2 T3
45 1/1 assign rdata_o = wdata_i;
Tests: T1 T2 T3
46
47 // host facing
48 1/1 assign wready_o = rready_i;
Tests: T1 T2 T3
49 1/1 assign full_o = rready_i;
Tests: T1 T2 T3
50
51 // this avoids lint warnings
52 logic unused_clr;
53 unreachable assign unused_clr = clr_i;
Assert Coverage for Instance : tb.dut.u_reg_core.u_socket.gen_dfifo[1].fifo_d.reqfifo
Assertion Details
DataKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
393570196 |
3719631 |
0 |
0 |
T1 |
2070 |
146 |
0 |
0 |
T2 |
3480 |
0 |
0 |
0 |
T3 |
1887 |
146 |
0 |
0 |
T4 |
4370 |
0 |
0 |
0 |
T5 |
677 |
11 |
0 |
0 |
T6 |
0 |
5 |
0 |
0 |
T8 |
45213 |
621 |
0 |
0 |
T9 |
1406 |
0 |
0 |
0 |
T10 |
2124 |
21 |
0 |
0 |
T11 |
0 |
5 |
0 |
0 |
T16 |
1541 |
146 |
0 |
0 |
T17 |
1625 |
0 |
0 |
0 |
T25 |
0 |
226 |
0 |
0 |
T31 |
0 |
72 |
0 |
0 |
DataKnown_AKnownEnable
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
393570196 |
392677850 |
0 |
0 |
T1 |
2070 |
1970 |
0 |
0 |
T2 |
3480 |
3381 |
0 |
0 |
T3 |
1887 |
1822 |
0 |
0 |
T4 |
4370 |
3912 |
0 |
0 |
T5 |
677 |
579 |
0 |
0 |
T8 |
45213 |
45151 |
0 |
0 |
T9 |
1406 |
1318 |
0 |
0 |
T10 |
2124 |
2046 |
0 |
0 |
T16 |
1541 |
1471 |
0 |
0 |
T17 |
1625 |
1542 |
0 |
0 |
DepthKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
393570196 |
392677850 |
0 |
0 |
T1 |
2070 |
1970 |
0 |
0 |
T2 |
3480 |
3381 |
0 |
0 |
T3 |
1887 |
1822 |
0 |
0 |
T4 |
4370 |
3912 |
0 |
0 |
T5 |
677 |
579 |
0 |
0 |
T8 |
45213 |
45151 |
0 |
0 |
T9 |
1406 |
1318 |
0 |
0 |
T10 |
2124 |
2046 |
0 |
0 |
T16 |
1541 |
1471 |
0 |
0 |
T17 |
1625 |
1542 |
0 |
0 |
RvalidKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
393570196 |
392677850 |
0 |
0 |
T1 |
2070 |
1970 |
0 |
0 |
T2 |
3480 |
3381 |
0 |
0 |
T3 |
1887 |
1822 |
0 |
0 |
T4 |
4370 |
3912 |
0 |
0 |
T5 |
677 |
579 |
0 |
0 |
T8 |
45213 |
45151 |
0 |
0 |
T9 |
1406 |
1318 |
0 |
0 |
T10 |
2124 |
2046 |
0 |
0 |
T16 |
1541 |
1471 |
0 |
0 |
T17 |
1625 |
1542 |
0 |
0 |
WreadyKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
393570196 |
392677850 |
0 |
0 |
T1 |
2070 |
1970 |
0 |
0 |
T2 |
3480 |
3381 |
0 |
0 |
T3 |
1887 |
1822 |
0 |
0 |
T4 |
4370 |
3912 |
0 |
0 |
T5 |
677 |
579 |
0 |
0 |
T8 |
45213 |
45151 |
0 |
0 |
T9 |
1406 |
1318 |
0 |
0 |
T10 |
2124 |
2046 |
0 |
0 |
T16 |
1541 |
1471 |
0 |
0 |
T17 |
1625 |
1542 |
0 |
0 |
gen_passthru_fifo.paramCheckPass
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
1266 |
1266 |
0 |
0 |
T1 |
1 |
1 |
0 |
0 |
T2 |
1 |
1 |
0 |
0 |
T3 |
1 |
1 |
0 |
0 |
T4 |
1 |
1 |
0 |
0 |
T5 |
1 |
1 |
0 |
0 |
T8 |
1 |
1 |
0 |
0 |
T9 |
1 |
1 |
0 |
0 |
T10 |
1 |
1 |
0 |
0 |
T16 |
1 |
1 |
0 |
0 |
T17 |
1 |
1 |
0 |
0 |