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Module Instance : tb.dut.u_to_prog_fifo.u_rspfifo

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
72.94 92.31 47.06 85.71 66.67


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
71.00 91.43 57.14 68.75 66.67


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
78.34 92.65 64.66 71.43 84.62 u_to_prog_fifo


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_normal_fifo.u_fifo_cnt 71.04 90.91 66.67 55.56


Module Instance : tb.dut.u_prog_fifo

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
95.83 100.00 83.33 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
97.73 100.00 90.91 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
94.85 97.12 94.40 98.44 100.00 84.29 dut


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_normal_fifo.u_fifo_cnt 100.00 100.00 100.00 100.00


Module Instance : tb.dut.u_to_rd_fifo.u_reqfifo

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
92.19 100.00 68.75 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
86.36 100.00 71.79 70.00 90.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
88.86 95.83 73.39 86.21 100.00 u_to_rd_fifo


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_normal_fifo.u_fifo_cnt 77.64 100.00 73.91 70.00 66.67


Module Instance : tb.dut.u_to_rd_fifo.u_sramreqfifo

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
90.62 100.00 62.50 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
85.85 100.00 69.23 70.00 90.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
88.86 95.83 73.39 86.21 100.00 u_to_rd_fifo


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_normal_fifo.u_fifo_cnt 77.64 100.00 73.91 70.00 66.67


Module Instance : tb.dut.u_to_rd_fifo.u_rspfifo

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
93.75 100.00 75.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
90.08 100.00 78.72 80.00 91.67 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
88.86 95.83 73.39 86.21 100.00 u_to_rd_fifo


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_normal_fifo.u_fifo_cnt 82.32 100.00 82.61 80.00 66.67

Go back
Module Instances:
tb.dut.u_to_prog_fifo.u_rspfifo
tb.dut.u_prog_fifo
tb.dut.u_to_rd_fifo.u_reqfifo
tb.dut.u_to_rd_fifo.u_sramreqfifo
tb.dut.u_to_rd_fifo.u_rspfifo
Line Coverage for Instance : tb.dut.u_to_prog_fifo.u_rspfifo
Line No.TotalCoveredPercent
TOTAL131292.31
ALWAYS6944100.00
CONT_ASSIGN8111100.00
CONT_ASSIGN8211100.00
CONT_ASSIGN10000
CONT_ASSIGN10111100.00
CONT_ASSIGN108100.00
ALWAYS11111100.00
CONT_ASSIGN11611100.00
CONT_ASSIGN13011100.00
CONT_ASSIGN13111100.00
CONT_ASSIGN13811100.00

68 always_ff @(posedge clk_i or negedge rst_ni) begin 69 1/1 if (!rst_ni) begin Tests: T1 T2 T3  70 1/1 under_rst <= 1'b1; Tests: T1 T2 T3  71 1/1 end else if (under_rst) begin Tests: T1 T2 T3  72 1/1 under_rst <= ~under_rst; Tests: T1 T2 T3  73 end MISSING_ELSE 74 end 75 76 logic empty; 77 78 // full and not ready for write are two different concepts. 79 // The latter can be '0' when under reset, while the former is an indication that no more 80 // entries can be written. 81 1/1 assign wready_o = ~full_o & ~under_rst; Tests: T1 T2 T3  82 1/1 assign rvalid_o = ~empty & ~under_rst; Tests: T1 T2 T3  83 84 prim_fifo_sync_cnt #( 85 .Depth(Depth), 86 .Secure(Secure) 87 ) u_fifo_cnt ( 88 .clk_i, 89 .rst_ni, 90 .clr_i, 91 .incr_wptr_i(fifo_incr_wptr), 92 .incr_rptr_i(fifo_incr_rptr), 93 .wptr_o(fifo_wptr), 94 .rptr_o(fifo_rptr), 95 .full_o, 96 .empty_o(fifo_empty), 97 .depth_o, 98 .err_o 99 ); 100 unreachable assign fifo_incr_wptr = wvalid_i & wready_o & ~under_rst; 101 1/1 assign fifo_incr_rptr = rvalid_o & rready_i & ~under_rst; Tests: T1 T2 T3  102 103 // the generate blocks below are needed to avoid lint errors due to array indexing 104 // in the where the fifo only has one storage element 105 logic [Depth-1:0][Width-1:0] storage; 106 logic [Width-1:0] storage_rdata; 107 if (Depth == 1) begin : gen_depth_eq1 108 0/1 ==> assign storage_rdata = storage[0]; 109 110 always_ff @(posedge clk_i) 111 1/1 if (fifo_incr_wptr) begin Tests: T1 T2 T3  112 unreachable storage[0] <= wdata_i; 113 end MISSING_ELSE 114 115 logic unused_ptrs; 116 1/1 assign unused_ptrs = ^{fifo_wptr, fifo_rptr}; Tests: T1 T2 T3  117 118 // fifo with more than one storage element 119 end else begin : gen_depth_gt1 120 assign storage_rdata = storage[fifo_rptr]; 121 122 always_ff @(posedge clk_i) 123 if (fifo_incr_wptr) begin 124 storage[fifo_wptr] <= wdata_i; 125 end 126 end 127 128 logic [Width-1:0] rdata_int; 129 if (Pass == 1'b1) begin : gen_pass 130 1/1 assign rdata_int = (fifo_empty && wvalid_i) ? wdata_i : storage_rdata; Tests: T1 T2 T3  131 1/1 assign empty = fifo_empty & ~wvalid_i; Tests: T1 T2 T3  132 end else begin : gen_nopass 133 assign rdata_int = storage_rdata; 134 assign empty = fifo_empty; 135 end 136 137 if (OutputZeroIfEmpty == 1'b1) begin : gen_output_zero 138 1/1 assign rdata_o = empty ? Width'(0) : rdata_int; Tests: T1 T2 T3 

Cond Coverage for Instance : tb.dut.u_to_prog_fifo.u_rspfifo
TotalCoveredPercent
Conditions17847.06
Logical17847.06
Non-Logical00
Event00

 LINE       81
 EXPRESSION (((~full_o)) & ((~gen_normal_fifo.under_rst)))
             -----1-----   ---------------2--------------
-1--2-StatusTests
01Not Covered
10CoveredT1,T2,T3
11CoveredT1,T2,T3

 LINE       82
 EXPRESSION (((~gen_normal_fifo.empty)) & ((~gen_normal_fifo.under_rst)))
             -------------1------------   ---------------2--------------
-1--2-StatusTests
01CoveredT1,T2,T3
10Not Covered
11Not Covered

 LINE       100
 EXPRESSION (wvalid_i & wready_o & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------
-1--2--3-StatusTests
011CoveredT1,T2,T3
101Unreachable
110Unreachable
111Unreachable

 LINE       101
 EXPRESSION (rvalid_o & rready_i & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------
-1--2--3-StatusTests
011Not Covered
101Not Covered
110Not Covered
111Not Covered

 LINE       130
 EXPRESSION ((gen_normal_fifo.fifo_empty && wvalid_i) ? wdata_i : gen_normal_fifo.storage_rdata)
             --------------------1-------------------
-1-StatusTests
0CoveredT1,T2,T3
1Unreachable

 LINE       130
 SUB-EXPRESSION (gen_normal_fifo.fifo_empty && wvalid_i)
                 -------------1------------    ----2---
-1--2-StatusTests
01Unreachable
10CoveredT1,T2,T3
11Unreachable

 LINE       131
 EXPRESSION (gen_normal_fifo.fifo_empty & ((~wvalid_i)))
             -------------1------------   ------2------
-1--2-StatusTests
01Not Covered
10Unreachable
11CoveredT1,T2,T3

 LINE       138
 EXPRESSION (gen_normal_fifo.empty ? (40'(0)) : gen_normal_fifo.rdata_int)
             ----------1----------
-1-StatusTests
0Not Covered
1CoveredT1,T2,T3

Branch Coverage for Instance : tb.dut.u_to_prog_fifo.u_rspfifo
Line No.TotalCoveredPercent
Branches 7 6 85.71
TERNARY 130 1 1 100.00
TERNARY 138 2 1 50.00
IF 69 3 3 100.00
IF 111 1 1 100.00


130 assign rdata_int = (fifo_empty && wvalid_i) ? wdata_i : storage_rdata; -1- ==> (Unreachable) ==>

Branches:
-1-StatusTests
1 Unreachable
0 Covered T1,T2,T3


138 assign rdata_o = empty ? Width'(0) : rdata_int; -1- ==> ==>

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Not Covered


69 if (!rst_ni) begin -1- 70 under_rst <= 1'b1; ==> 71 end else if (under_rst) begin -2- 72 under_rst <= ~under_rst; ==> 73 end MISSING_ELSE ==>

Branches:
-1--2-StatusTests
1 - Covered T1,T2,T3
0 1 Covered T1,T2,T3
0 0 Covered T1,T2,T3


111 if (fifo_incr_wptr) begin -1- 112 storage[0] <= wdata_i; ==> (Unreachable) 113 end MISSING_ELSE ==>

Branches:
-1-StatusTests
1 Unreachable
0 Covered T1,T2,T3


Assert Coverage for Instance : tb.dut.u_to_prog_fifo.u_rspfifo
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 6 6 100.00 4 66.67
Cover properties 0 0 0
Cover sequences 0 0 0
Total 6 6 100.00 4 66.67




Assertion Details

Name   Attempts   Real Successes   Failures   Incomplete   
DataKnown_A 361909267 0 0 0
DataKnown_AKnownEnable 361909267 361047510 0 0
DepthKnown_A 361909267 361047510 0 0
RvalidKnown_A 361909267 361047510 0 0
WreadyKnown_A 361909267 361047510 0 0
gen_normal_fifo.depthShallNotExceedParamDepth 361909267 0 0 0


DataKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 361909267 0 0 0

DataKnown_AKnownEnable
NameAttemptsReal SuccessesFailuresIncomplete
Total 361909267 361047510 0 0
T1 1577 1514 0 0
T2 1916 1822 0 0
T3 33100 33039 0 0
T4 4218 3512 0 0
T9 4035 3976 0 0
T10 6277 6206 0 0
T15 1455 1381 0 0
T16 2031 1975 0 0
T17 1869 1775 0 0
T18 195519 195455 0 0

DepthKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 361909267 361047510 0 0
T1 1577 1514 0 0
T2 1916 1822 0 0
T3 33100 33039 0 0
T4 4218 3512 0 0
T9 4035 3976 0 0
T10 6277 6206 0 0
T15 1455 1381 0 0
T16 2031 1975 0 0
T17 1869 1775 0 0
T18 195519 195455 0 0

RvalidKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 361909267 361047510 0 0
T1 1577 1514 0 0
T2 1916 1822 0 0
T3 33100 33039 0 0
T4 4218 3512 0 0
T9 4035 3976 0 0
T10 6277 6206 0 0
T15 1455 1381 0 0
T16 2031 1975 0 0
T17 1869 1775 0 0
T18 195519 195455 0 0

WreadyKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 361909267 361047510 0 0
T1 1577 1514 0 0
T2 1916 1822 0 0
T3 33100 33039 0 0
T4 4218 3512 0 0
T9 4035 3976 0 0
T10 6277 6206 0 0
T15 1455 1381 0 0
T16 2031 1975 0 0
T17 1869 1775 0 0
T18 195519 195455 0 0

gen_normal_fifo.depthShallNotExceedParamDepth
NameAttemptsReal SuccessesFailuresIncomplete
Total 361909267 0 0 0

Line Coverage for Instance : tb.dut.u_prog_fifo
Line No.TotalCoveredPercent
TOTAL1414100.00
ALWAYS6944100.00
CONT_ASSIGN8111100.00
CONT_ASSIGN8211100.00
CONT_ASSIGN10011100.00
CONT_ASSIGN10111100.00
CONT_ASSIGN12011100.00
ALWAYS12322100.00
CONT_ASSIGN13011100.00
CONT_ASSIGN13111100.00
CONT_ASSIGN13811100.00

68 always_ff @(posedge clk_i or negedge rst_ni) begin 69 1/1 if (!rst_ni) begin Tests: T1 T2 T3  70 1/1 under_rst <= 1'b1; Tests: T1 T2 T3  71 1/1 end else if (under_rst) begin Tests: T1 T2 T3  72 1/1 under_rst <= ~under_rst; Tests: T1 T2 T3  73 end MISSING_ELSE 74 end 75 76 logic empty; 77 78 // full and not ready for write are two different concepts. 79 // The latter can be '0' when under reset, while the former is an indication that no more 80 // entries can be written. 81 1/1 assign wready_o = ~full_o & ~under_rst; Tests: T1 T2 T3  82 1/1 assign rvalid_o = ~empty & ~under_rst; Tests: T1 T2 T3  83 84 prim_fifo_sync_cnt #( 85 .Depth(Depth), 86 .Secure(Secure) 87 ) u_fifo_cnt ( 88 .clk_i, 89 .rst_ni, 90 .clr_i, 91 .incr_wptr_i(fifo_incr_wptr), 92 .incr_rptr_i(fifo_incr_rptr), 93 .wptr_o(fifo_wptr), 94 .rptr_o(fifo_rptr), 95 .full_o, 96 .empty_o(fifo_empty), 97 .depth_o, 98 .err_o 99 ); 100 1/1 assign fifo_incr_wptr = wvalid_i & wready_o & ~under_rst; Tests: T1 T2 T3  101 1/1 assign fifo_incr_rptr = rvalid_o & rready_i & ~under_rst; Tests: T1 T2 T3  102 103 // the generate blocks below are needed to avoid lint errors due to array indexing 104 // in the where the fifo only has one storage element 105 logic [Depth-1:0][Width-1:0] storage; 106 logic [Width-1:0] storage_rdata; 107 if (Depth == 1) begin : gen_depth_eq1 108 assign storage_rdata = storage[0]; 109 110 always_ff @(posedge clk_i) 111 if (fifo_incr_wptr) begin 112 storage[0] <= wdata_i; 113 end 114 115 logic unused_ptrs; 116 assign unused_ptrs = ^{fifo_wptr, fifo_rptr}; 117 118 // fifo with more than one storage element 119 end else begin : gen_depth_gt1 120 1/1 assign storage_rdata = storage[fifo_rptr]; Tests: T1 T2 T3  121 122 always_ff @(posedge clk_i) 123 1/1 if (fifo_incr_wptr) begin Tests: T1 T2 T3  124 1/1 storage[fifo_wptr] <= wdata_i; Tests: T2 T9 T10  125 end MISSING_ELSE 126 end 127 128 logic [Width-1:0] rdata_int; 129 if (Pass == 1'b1) begin : gen_pass 130 1/1 assign rdata_int = (fifo_empty && wvalid_i) ? wdata_i : storage_rdata; Tests: T1 T2 T3  131 1/1 assign empty = fifo_empty & ~wvalid_i; Tests: T1 T2 T3  132 end else begin : gen_nopass 133 assign rdata_int = storage_rdata; 134 assign empty = fifo_empty; 135 end 136 137 if (OutputZeroIfEmpty == 1'b1) begin : gen_output_zero 138 1/1 assign rdata_o = empty ? Width'(0) : rdata_int; Tests: T1 T2 T3 

Cond Coverage for Instance : tb.dut.u_prog_fifo
TotalCoveredPercent
Conditions242083.33
Logical242083.33
Non-Logical00
Event00

 LINE       81
 EXPRESSION (((~full_o)) & ((~gen_normal_fifo.under_rst)))
             -----1-----   ---------------2--------------
-1--2-StatusTests
01CoveredT2,T9,T10
10CoveredT1,T2,T3
11CoveredT1,T2,T3

 LINE       82
 EXPRESSION (((~gen_normal_fifo.empty)) & ((~gen_normal_fifo.under_rst)))
             -------------1------------   ---------------2--------------
-1--2-StatusTests
01CoveredT1,T2,T3
10Not Covered
11CoveredT2,T9,T10

 LINE       100
 EXPRESSION (wvalid_i & wready_o & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------
-1--2--3-StatusTests
011CoveredT1,T2,T3
101CoveredT2,T59,T6
110Not Covered
111CoveredT2,T9,T10

 LINE       101
 EXPRESSION (rvalid_o & rready_i & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------
-1--2--3-StatusTests
011Not Covered
101CoveredT2,T9,T10
110Not Covered
111CoveredT2,T9,T10

 LINE       130
 EXPRESSION ((gen_normal_fifo.fifo_empty && wvalid_i) ? wdata_i : gen_normal_fifo.storage_rdata)
             --------------------1-------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT2,T9,T10

 LINE       130
 SUB-EXPRESSION (gen_normal_fifo.fifo_empty && wvalid_i)
                 -------------1------------    ----2---
-1--2-StatusTests
01CoveredT2,T9,T10
10CoveredT1,T2,T3
11CoveredT2,T9,T10

 LINE       131
 EXPRESSION (gen_normal_fifo.fifo_empty & ((~wvalid_i)))
             -------------1------------   ------2------
-1--2-StatusTests
01CoveredT2,T9,T10
10CoveredT2,T9,T10
11CoveredT1,T2,T3

 LINE       138
 EXPRESSION (gen_normal_fifo.empty ? (39'(0)) : gen_normal_fifo.rdata_int)
             ----------1----------
-1-StatusTests
0CoveredT2,T9,T10
1CoveredT1,T2,T3

Branch Coverage for Instance : tb.dut.u_prog_fifo
Line No.TotalCoveredPercent
Branches 9 9 100.00
TERNARY 130 2 2 100.00
TERNARY 138 2 2 100.00
IF 69 3 3 100.00
IF 111 2 2 100.00


130 assign rdata_int = (fifo_empty && wvalid_i) ? wdata_i : storage_rdata; -1- ==> ==>

Branches:
-1-StatusTests
1 Covered T2,T9,T10
0 Covered T1,T2,T3


138 assign rdata_o = empty ? Width'(0) : rdata_int; -1- ==> ==>

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T2,T9,T10


69 if (!rst_ni) begin -1- 70 under_rst <= 1'b1; ==> 71 end else if (under_rst) begin -2- 72 under_rst <= ~under_rst; ==> 73 end MISSING_ELSE ==>

Branches:
-1--2-StatusTests
1 - Covered T1,T2,T3
0 1 Covered T1,T2,T3
0 0 Covered T1,T2,T3


111 if (fifo_incr_wptr) begin -1- 112 storage[0] <= wdata_i; ==> 113 end MISSING_ELSE ==>

Branches:
-1-StatusTests
1 Covered T2,T9,T10
0 Covered T1,T2,T3


Assert Coverage for Instance : tb.dut.u_prog_fifo
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 6 6 100.00 6 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 6 6 100.00 6 100.00




Assertion Details

Name   Attempts   Real Successes   Failures   Incomplete   
DataKnown_A 361909267 154842548 0 0
DataKnown_AKnownEnable 361909267 361047510 0 0
DepthKnown_A 361909267 361047510 0 0
RvalidKnown_A 361909267 361047510 0 0
WreadyKnown_A 361909267 361047510 0 0
gen_normal_fifo.depthShallNotExceedParamDepth 361909267 154842548 0 0


DataKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 361909267 154842548 0 0
T2 1916 277 0 0
T3 33100 0 0 0
T4 4218 0 0 0
T9 4035 2190 0 0
T10 6277 3236 0 0
T11 0 31787 0 0
T15 1455 0 0 0
T16 2031 0 0 0
T17 1869 0 0 0
T18 195519 13523 0 0
T20 137786 1121 0 0
T26 0 8384 0 0
T27 0 79800 0 0
T37 0 104366 0 0
T76 0 20283 0 0

DataKnown_AKnownEnable
NameAttemptsReal SuccessesFailuresIncomplete
Total 361909267 361047510 0 0
T1 1577 1514 0 0
T2 1916 1822 0 0
T3 33100 33039 0 0
T4 4218 3512 0 0
T9 4035 3976 0 0
T10 6277 6206 0 0
T15 1455 1381 0 0
T16 2031 1975 0 0
T17 1869 1775 0 0
T18 195519 195455 0 0

DepthKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 361909267 361047510 0 0
T1 1577 1514 0 0
T2 1916 1822 0 0
T3 33100 33039 0 0
T4 4218 3512 0 0
T9 4035 3976 0 0
T10 6277 6206 0 0
T15 1455 1381 0 0
T16 2031 1975 0 0
T17 1869 1775 0 0
T18 195519 195455 0 0

RvalidKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 361909267 361047510 0 0
T1 1577 1514 0 0
T2 1916 1822 0 0
T3 33100 33039 0 0
T4 4218 3512 0 0
T9 4035 3976 0 0
T10 6277 6206 0 0
T15 1455 1381 0 0
T16 2031 1975 0 0
T17 1869 1775 0 0
T18 195519 195455 0 0

WreadyKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 361909267 361047510 0 0
T1 1577 1514 0 0
T2 1916 1822 0 0
T3 33100 33039 0 0
T4 4218 3512 0 0
T9 4035 3976 0 0
T10 6277 6206 0 0
T15 1455 1381 0 0
T16 2031 1975 0 0
T17 1869 1775 0 0
T18 195519 195455 0 0

gen_normal_fifo.depthShallNotExceedParamDepth
NameAttemptsReal SuccessesFailuresIncomplete
Total 361909267 154842548 0 0
T2 1916 277 0 0
T3 33100 0 0 0
T4 4218 0 0 0
T9 4035 2190 0 0
T10 6277 3236 0 0
T11 0 31787 0 0
T15 1455 0 0 0
T16 2031 0 0 0
T17 1869 0 0 0
T18 195519 13523 0 0
T20 137786 1121 0 0
T26 0 8384 0 0
T27 0 79800 0 0
T37 0 104366 0 0
T76 0 20283 0 0

Line Coverage for Instance : tb.dut.u_to_rd_fifo.u_reqfifo
Line No.TotalCoveredPercent
TOTAL1515100.00
ALWAYS6944100.00
CONT_ASSIGN8111100.00
CONT_ASSIGN8211100.00
CONT_ASSIGN10011100.00
CONT_ASSIGN10111100.00
CONT_ASSIGN10811100.00
ALWAYS11122100.00
CONT_ASSIGN11611100.00
CONT_ASSIGN13311100.00
CONT_ASSIGN13411100.00
CONT_ASSIGN13811100.00

68 always_ff @(posedge clk_i or negedge rst_ni) begin 69 1/1 if (!rst_ni) begin Tests: T1 T2 T3  70 1/1 under_rst <= 1'b1; Tests: T1 T2 T3  71 1/1 end else if (under_rst) begin Tests: T1 T2 T3  72 1/1 under_rst <= ~under_rst; Tests: T1 T2 T3  73 end MISSING_ELSE 74 end 75 76 logic empty; 77 78 // full and not ready for write are two different concepts. 79 // The latter can be '0' when under reset, while the former is an indication that no more 80 // entries can be written. 81 1/1 assign wready_o = ~full_o & ~under_rst; Tests: T1 T2 T3  82 1/1 assign rvalid_o = ~empty & ~under_rst; Tests: T1 T2 T3  83 84 prim_fifo_sync_cnt #( 85 .Depth(Depth), 86 .Secure(Secure) 87 ) u_fifo_cnt ( 88 .clk_i, 89 .rst_ni, 90 .clr_i, 91 .incr_wptr_i(fifo_incr_wptr), 92 .incr_rptr_i(fifo_incr_rptr), 93 .wptr_o(fifo_wptr), 94 .rptr_o(fifo_rptr), 95 .full_o, 96 .empty_o(fifo_empty), 97 .depth_o, 98 .err_o 99 ); 100 1/1 assign fifo_incr_wptr = wvalid_i & wready_o & ~under_rst; Tests: T1 T2 T3  101 1/1 assign fifo_incr_rptr = rvalid_o & rready_i & ~under_rst; Tests: T1 T2 T3  102 103 // the generate blocks below are needed to avoid lint errors due to array indexing 104 // in the where the fifo only has one storage element 105 logic [Depth-1:0][Width-1:0] storage; 106 logic [Width-1:0] storage_rdata; 107 if (Depth == 1) begin : gen_depth_eq1 108 1/1 assign storage_rdata = storage[0]; Tests: T2 T3 T15  109 110 always_ff @(posedge clk_i) 111 1/1 if (fifo_incr_wptr) begin Tests: T1 T2 T3  112 1/1 storage[0] <= wdata_i; Tests: T2 T3 T15  113 end MISSING_ELSE 114 115 logic unused_ptrs; 116 1/1 assign unused_ptrs = ^{fifo_wptr, fifo_rptr}; Tests: T1 T2 T3  117 118 // fifo with more than one storage element 119 end else begin : gen_depth_gt1 120 assign storage_rdata = storage[fifo_rptr]; 121 122 always_ff @(posedge clk_i) 123 if (fifo_incr_wptr) begin 124 storage[fifo_wptr] <= wdata_i; 125 end 126 end 127 128 logic [Width-1:0] rdata_int; 129 if (Pass == 1'b1) begin : gen_pass 130 assign rdata_int = (fifo_empty && wvalid_i) ? wdata_i : storage_rdata; 131 assign empty = fifo_empty & ~wvalid_i; 132 end else begin : gen_nopass 133 1/1 assign rdata_int = storage_rdata; Tests: T2 T3 T15  134 1/1 assign empty = fifo_empty; Tests: T1 T2 T3  135 end 136 137 if (OutputZeroIfEmpty == 1'b1) begin : gen_output_zero 138 1/1 assign rdata_o = empty ? Width'(0) : rdata_int; Tests: T1 T2 T3 

Cond Coverage for Instance : tb.dut.u_to_rd_fifo.u_reqfifo
TotalCoveredPercent
Conditions161168.75
Logical161168.75
Non-Logical00
Event00

 LINE       81
 EXPRESSION (((~full_o)) & ((~gen_normal_fifo.under_rst)))
             -----1-----   ---------------2--------------
-1--2-StatusTests
01CoveredT2,T3,T15
10CoveredT1,T2,T3
11CoveredT1,T2,T3

 LINE       82
 EXPRESSION (((~gen_normal_fifo.empty)) & ((~gen_normal_fifo.under_rst)))
             -------------1------------   ---------------2--------------
-1--2-StatusTests
01CoveredT1,T2,T3
10Not Covered
11CoveredT2,T3,T15

 LINE       100
 EXPRESSION (wvalid_i & wready_o & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------
-1--2--3-StatusTests
011CoveredT1,T2,T3
101Not Covered
110Not Covered
111CoveredT2,T3,T15

 LINE       101
 EXPRESSION (rvalid_o & rready_i & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------
-1--2--3-StatusTests
011Not Covered
101CoveredT3,T15,T10
110Not Covered
111CoveredT2,T3,T15

 LINE       138
 EXPRESSION (gen_normal_fifo.empty ? (17'(0)) : gen_normal_fifo.rdata_int)
             ----------1----------
-1-StatusTests
0CoveredT2,T3,T15
1CoveredT1,T2,T3

Branch Coverage for Instance : tb.dut.u_to_rd_fifo.u_reqfifo
Line No.TotalCoveredPercent
Branches 7 7 100.00
TERNARY 138 2 2 100.00
IF 69 3 3 100.00
IF 111 2 2 100.00


138 assign rdata_o = empty ? Width'(0) : rdata_int; -1- ==> ==>

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T2,T3,T15


69 if (!rst_ni) begin -1- 70 under_rst <= 1'b1; ==> 71 end else if (under_rst) begin -2- 72 under_rst <= ~under_rst; ==> 73 end MISSING_ELSE ==>

Branches:
-1--2-StatusTests
1 - Covered T1,T2,T3
0 1 Covered T1,T2,T3
0 0 Covered T1,T2,T3


111 if (fifo_incr_wptr) begin -1- 112 storage[0] <= wdata_i; ==> 113 end MISSING_ELSE ==>

Branches:
-1-StatusTests
1 Covered T2,T3,T15
0 Covered T1,T2,T3


Assert Coverage for Instance : tb.dut.u_to_rd_fifo.u_reqfifo
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 6 6 100.00 6 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 6 6 100.00 6 100.00




Assertion Details

Name   Attempts   Real Successes   Failures   Incomplete   
DataKnown_A 361909267 4687481 0 0
DataKnown_AKnownEnable 361909267 361047510 0 0
DepthKnown_A 361909267 361047510 0 0
RvalidKnown_A 361909267 361047510 0 0
WreadyKnown_A 361909267 361047510 0 0
gen_normal_fifo.depthShallNotExceedParamDepth 361909267 4687481 0 0


DataKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 361909267 4687481 0 0
T2 1916 20 0 0
T3 33100 643 0 0
T4 4218 0 0 0
T9 4035 0 0 0
T10 6277 116 0 0
T15 1455 5 0 0
T16 2031 146 0 0
T17 1869 146 0 0
T18 195519 10627 0 0
T20 137786 88 0 0
T26 0 185 0 0
T70 0 146 0 0

DataKnown_AKnownEnable
NameAttemptsReal SuccessesFailuresIncomplete
Total 361909267 361047510 0 0
T1 1577 1514 0 0
T2 1916 1822 0 0
T3 33100 33039 0 0
T4 4218 3512 0 0
T9 4035 3976 0 0
T10 6277 6206 0 0
T15 1455 1381 0 0
T16 2031 1975 0 0
T17 1869 1775 0 0
T18 195519 195455 0 0

DepthKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 361909267 361047510 0 0
T1 1577 1514 0 0
T2 1916 1822 0 0
T3 33100 33039 0 0
T4 4218 3512 0 0
T9 4035 3976 0 0
T10 6277 6206 0 0
T15 1455 1381 0 0
T16 2031 1975 0 0
T17 1869 1775 0 0
T18 195519 195455 0 0

RvalidKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 361909267 361047510 0 0
T1 1577 1514 0 0
T2 1916 1822 0 0
T3 33100 33039 0 0
T4 4218 3512 0 0
T9 4035 3976 0 0
T10 6277 6206 0 0
T15 1455 1381 0 0
T16 2031 1975 0 0
T17 1869 1775 0 0
T18 195519 195455 0 0

WreadyKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 361909267 361047510 0 0
T1 1577 1514 0 0
T2 1916 1822 0 0
T3 33100 33039 0 0
T4 4218 3512 0 0
T9 4035 3976 0 0
T10 6277 6206 0 0
T15 1455 1381 0 0
T16 2031 1975 0 0
T17 1869 1775 0 0
T18 195519 195455 0 0

gen_normal_fifo.depthShallNotExceedParamDepth
NameAttemptsReal SuccessesFailuresIncomplete
Total 361909267 4687481 0 0
T2 1916 20 0 0
T3 33100 643 0 0
T4 4218 0 0 0
T9 4035 0 0 0
T10 6277 116 0 0
T15 1455 5 0 0
T16 2031 146 0 0
T17 1869 146 0 0
T18 195519 10627 0 0
T20 137786 88 0 0
T26 0 185 0 0
T70 0 146 0 0

Line Coverage for Instance : tb.dut.u_to_rd_fifo.u_sramreqfifo
Line No.TotalCoveredPercent
TOTAL1515100.00
ALWAYS6944100.00
CONT_ASSIGN8111100.00
CONT_ASSIGN8211100.00
CONT_ASSIGN10011100.00
CONT_ASSIGN10111100.00
CONT_ASSIGN10811100.00
ALWAYS11122100.00
CONT_ASSIGN11611100.00
CONT_ASSIGN13311100.00
CONT_ASSIGN13411100.00
CONT_ASSIGN13811100.00

68 always_ff @(posedge clk_i or negedge rst_ni) begin 69 1/1 if (!rst_ni) begin Tests: T1 T2 T3  70 1/1 under_rst <= 1'b1; Tests: T1 T2 T3  71 1/1 end else if (under_rst) begin Tests: T1 T2 T3  72 1/1 under_rst <= ~under_rst; Tests: T1 T2 T3  73 end MISSING_ELSE 74 end 75 76 logic empty; 77 78 // full and not ready for write are two different concepts. 79 // The latter can be '0' when under reset, while the former is an indication that no more 80 // entries can be written. 81 1/1 assign wready_o = ~full_o & ~under_rst; Tests: T1 T2 T3  82 1/1 assign rvalid_o = ~empty & ~under_rst; Tests: T1 T2 T3  83 84 prim_fifo_sync_cnt #( 85 .Depth(Depth), 86 .Secure(Secure) 87 ) u_fifo_cnt ( 88 .clk_i, 89 .rst_ni, 90 .clr_i, 91 .incr_wptr_i(fifo_incr_wptr), 92 .incr_rptr_i(fifo_incr_rptr), 93 .wptr_o(fifo_wptr), 94 .rptr_o(fifo_rptr), 95 .full_o, 96 .empty_o(fifo_empty), 97 .depth_o, 98 .err_o 99 ); 100 1/1 assign fifo_incr_wptr = wvalid_i & wready_o & ~under_rst; Tests: T1 T2 T3  101 1/1 assign fifo_incr_rptr = rvalid_o & rready_i & ~under_rst; Tests: T1 T2 T3  102 103 // the generate blocks below are needed to avoid lint errors due to array indexing 104 // in the where the fifo only has one storage element 105 logic [Depth-1:0][Width-1:0] storage; 106 logic [Width-1:0] storage_rdata; 107 if (Depth == 1) begin : gen_depth_eq1 108 1/1 assign storage_rdata = storage[0]; Tests: T2 T3 T15  109 110 always_ff @(posedge clk_i) 111 1/1 if (fifo_incr_wptr) begin Tests: T1 T2 T3  112 1/1 storage[0] <= wdata_i; Tests: T2 T3 T15  113 end MISSING_ELSE 114 115 logic unused_ptrs; 116 1/1 assign unused_ptrs = ^{fifo_wptr, fifo_rptr}; Tests: T1 T2 T3  117 118 // fifo with more than one storage element 119 end else begin : gen_depth_gt1 120 assign storage_rdata = storage[fifo_rptr]; 121 122 always_ff @(posedge clk_i) 123 if (fifo_incr_wptr) begin 124 storage[fifo_wptr] <= wdata_i; 125 end 126 end 127 128 logic [Width-1:0] rdata_int; 129 if (Pass == 1'b1) begin : gen_pass 130 assign rdata_int = (fifo_empty && wvalid_i) ? wdata_i : storage_rdata; 131 assign empty = fifo_empty & ~wvalid_i; 132 end else begin : gen_nopass 133 1/1 assign rdata_int = storage_rdata; Tests: T2 T3 T15  134 1/1 assign empty = fifo_empty; Tests: T1 T2 T3  135 end 136 137 if (OutputZeroIfEmpty == 1'b1) begin : gen_output_zero 138 1/1 assign rdata_o = empty ? Width'(0) : rdata_int; Tests: T1 T2 T3 

Cond Coverage for Instance : tb.dut.u_to_rd_fifo.u_sramreqfifo
TotalCoveredPercent
Conditions161062.50
Logical161062.50
Non-Logical00
Event00

 LINE       81
 EXPRESSION (((~full_o)) & ((~gen_normal_fifo.under_rst)))
             -----1-----   ---------------2--------------
-1--2-StatusTests
01CoveredT2,T3,T15
10CoveredT1,T2,T3
11CoveredT1,T2,T3

 LINE       82
 EXPRESSION (((~gen_normal_fifo.empty)) & ((~gen_normal_fifo.under_rst)))
             -------------1------------   ---------------2--------------
-1--2-StatusTests
01CoveredT1,T2,T3
10Not Covered
11CoveredT2,T3,T15

 LINE       100
 EXPRESSION (wvalid_i & wready_o & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------
-1--2--3-StatusTests
011CoveredT1,T2,T3
101Not Covered
110Not Covered
111CoveredT2,T3,T15

 LINE       101
 EXPRESSION (rvalid_o & rready_i & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------
-1--2--3-StatusTests
011Not Covered
101Not Covered
110Not Covered
111CoveredT2,T3,T15

 LINE       138
 EXPRESSION (gen_normal_fifo.empty ? (5'(0)) : gen_normal_fifo.rdata_int)
             ----------1----------
-1-StatusTests
0CoveredT2,T3,T15
1CoveredT1,T2,T3

Branch Coverage for Instance : tb.dut.u_to_rd_fifo.u_sramreqfifo
Line No.TotalCoveredPercent
Branches 7 7 100.00
TERNARY 138 2 2 100.00
IF 69 3 3 100.00
IF 111 2 2 100.00


138 assign rdata_o = empty ? Width'(0) : rdata_int; -1- ==> ==>

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T2,T3,T15


69 if (!rst_ni) begin -1- 70 under_rst <= 1'b1; ==> 71 end else if (under_rst) begin -2- 72 under_rst <= ~under_rst; ==> 73 end MISSING_ELSE ==>

Branches:
-1--2-StatusTests
1 - Covered T1,T2,T3
0 1 Covered T1,T2,T3
0 0 Covered T1,T2,T3


111 if (fifo_incr_wptr) begin -1- 112 storage[0] <= wdata_i; ==> 113 end MISSING_ELSE ==>

Branches:
-1-StatusTests
1 Covered T2,T3,T15
0 Covered T1,T2,T3


Assert Coverage for Instance : tb.dut.u_to_rd_fifo.u_sramreqfifo
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 6 6 100.00 6 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 6 6 100.00 6 100.00




Assertion Details

Name   Attempts   Real Successes   Failures   Incomplete   
DataKnown_A 361909267 3113131 0 0
DataKnown_AKnownEnable 361909267 361047510 0 0
DepthKnown_A 361909267 361047510 0 0
RvalidKnown_A 361909267 361047510 0 0
WreadyKnown_A 361909267 361047510 0 0
gen_normal_fifo.depthShallNotExceedParamDepth 361909267 3113131 0 0


DataKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 361909267 3113131 0 0
T2 1916 20 0 0
T3 33100 643 0 0
T4 4218 0 0 0
T9 4035 0 0 0
T10 6277 116 0 0
T15 1455 5 0 0
T16 2031 146 0 0
T17 1869 146 0 0
T18 195519 2380 0 0
T20 137786 88 0 0
T26 0 41 0 0
T70 0 146 0 0

DataKnown_AKnownEnable
NameAttemptsReal SuccessesFailuresIncomplete
Total 361909267 361047510 0 0
T1 1577 1514 0 0
T2 1916 1822 0 0
T3 33100 33039 0 0
T4 4218 3512 0 0
T9 4035 3976 0 0
T10 6277 6206 0 0
T15 1455 1381 0 0
T16 2031 1975 0 0
T17 1869 1775 0 0
T18 195519 195455 0 0

DepthKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 361909267 361047510 0 0
T1 1577 1514 0 0
T2 1916 1822 0 0
T3 33100 33039 0 0
T4 4218 3512 0 0
T9 4035 3976 0 0
T10 6277 6206 0 0
T15 1455 1381 0 0
T16 2031 1975 0 0
T17 1869 1775 0 0
T18 195519 195455 0 0

RvalidKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 361909267 361047510 0 0
T1 1577 1514 0 0
T2 1916 1822 0 0
T3 33100 33039 0 0
T4 4218 3512 0 0
T9 4035 3976 0 0
T10 6277 6206 0 0
T15 1455 1381 0 0
T16 2031 1975 0 0
T17 1869 1775 0 0
T18 195519 195455 0 0

WreadyKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 361909267 361047510 0 0
T1 1577 1514 0 0
T2 1916 1822 0 0
T3 33100 33039 0 0
T4 4218 3512 0 0
T9 4035 3976 0 0
T10 6277 6206 0 0
T15 1455 1381 0 0
T16 2031 1975 0 0
T17 1869 1775 0 0
T18 195519 195455 0 0

gen_normal_fifo.depthShallNotExceedParamDepth
NameAttemptsReal SuccessesFailuresIncomplete
Total 361909267 3113131 0 0
T2 1916 20 0 0
T3 33100 643 0 0
T4 4218 0 0 0
T9 4035 0 0 0
T10 6277 116 0 0
T15 1455 5 0 0
T16 2031 146 0 0
T17 1869 146 0 0
T18 195519 2380 0 0
T20 137786 88 0 0
T26 0 41 0 0
T70 0 146 0 0

Line Coverage for Instance : tb.dut.u_to_rd_fifo.u_rspfifo
Line No.TotalCoveredPercent
TOTAL1515100.00
ALWAYS6944100.00
CONT_ASSIGN8111100.00
CONT_ASSIGN8211100.00
CONT_ASSIGN10011100.00
CONT_ASSIGN10111100.00
CONT_ASSIGN10811100.00
ALWAYS11122100.00
CONT_ASSIGN11611100.00
CONT_ASSIGN13011100.00
CONT_ASSIGN13111100.00
CONT_ASSIGN13811100.00

68 always_ff @(posedge clk_i or negedge rst_ni) begin 69 1/1 if (!rst_ni) begin Tests: T1 T2 T3  70 1/1 under_rst <= 1'b1; Tests: T1 T2 T3  71 1/1 end else if (under_rst) begin Tests: T1 T2 T3  72 1/1 under_rst <= ~under_rst; Tests: T1 T2 T3  73 end MISSING_ELSE 74 end 75 76 logic empty; 77 78 // full and not ready for write are two different concepts. 79 // The latter can be '0' when under reset, while the former is an indication that no more 80 // entries can be written. 81 1/1 assign wready_o = ~full_o & ~under_rst; Tests: T1 T2 T3  82 1/1 assign rvalid_o = ~empty & ~under_rst; Tests: T1 T2 T3  83 84 prim_fifo_sync_cnt #( 85 .Depth(Depth), 86 .Secure(Secure) 87 ) u_fifo_cnt ( 88 .clk_i, 89 .rst_ni, 90 .clr_i, 91 .incr_wptr_i(fifo_incr_wptr), 92 .incr_rptr_i(fifo_incr_rptr), 93 .wptr_o(fifo_wptr), 94 .rptr_o(fifo_rptr), 95 .full_o, 96 .empty_o(fifo_empty), 97 .depth_o, 98 .err_o 99 ); 100 1/1 assign fifo_incr_wptr = wvalid_i & wready_o & ~under_rst; Tests: T1 T2 T3  101 1/1 assign fifo_incr_rptr = rvalid_o & rready_i & ~under_rst; Tests: T1 T2 T3  102 103 // the generate blocks below are needed to avoid lint errors due to array indexing 104 // in the where the fifo only has one storage element 105 logic [Depth-1:0][Width-1:0] storage; 106 logic [Width-1:0] storage_rdata; 107 if (Depth == 1) begin : gen_depth_eq1 108 1/1 assign storage_rdata = storage[0]; Tests: T2 T3 T15  109 110 always_ff @(posedge clk_i) 111 1/1 if (fifo_incr_wptr) begin Tests: T1 T2 T3  112 1/1 storage[0] <= wdata_i; Tests: T2 T3 T15  113 end MISSING_ELSE 114 115 logic unused_ptrs; 116 1/1 assign unused_ptrs = ^{fifo_wptr, fifo_rptr}; Tests: T1 T2 T3  117 118 // fifo with more than one storage element 119 end else begin : gen_depth_gt1 120 assign storage_rdata = storage[fifo_rptr]; 121 122 always_ff @(posedge clk_i) 123 if (fifo_incr_wptr) begin 124 storage[fifo_wptr] <= wdata_i; 125 end 126 end 127 128 logic [Width-1:0] rdata_int; 129 if (Pass == 1'b1) begin : gen_pass 130 1/1 assign rdata_int = (fifo_empty && wvalid_i) ? wdata_i : storage_rdata; Tests: T1 T2 T3  131 1/1 assign empty = fifo_empty & ~wvalid_i; Tests: T1 T2 T3  132 end else begin : gen_nopass 133 assign rdata_int = storage_rdata; 134 assign empty = fifo_empty; 135 end 136 137 if (OutputZeroIfEmpty == 1'b1) begin : gen_output_zero 138 1/1 assign rdata_o = empty ? Width'(0) : rdata_int; Tests: T1 T2 T3 

Cond Coverage for Instance : tb.dut.u_to_rd_fifo.u_rspfifo
TotalCoveredPercent
Conditions241875.00
Logical241875.00
Non-Logical00
Event00

 LINE       81
 EXPRESSION (((~full_o)) & ((~gen_normal_fifo.under_rst)))
             -----1-----   ---------------2--------------
-1--2-StatusTests
01CoveredT18,T26,T58
10CoveredT1,T2,T3
11CoveredT1,T2,T3

 LINE       82
 EXPRESSION (((~gen_normal_fifo.empty)) & ((~gen_normal_fifo.under_rst)))
             -------------1------------   ---------------2--------------
-1--2-StatusTests
01CoveredT1,T2,T3
10Not Covered
11CoveredT2,T3,T15

 LINE       100
 EXPRESSION (wvalid_i & wready_o & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------
-1--2--3-StatusTests
011CoveredT1,T2,T3
101Not Covered
110Not Covered
111CoveredT2,T3,T15

 LINE       101
 EXPRESSION (rvalid_o & rready_i & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------
-1--2--3-StatusTests
011Not Covered
101CoveredT3,T15,T10
110Not Covered
111CoveredT2,T3,T15

 LINE       130
 EXPRESSION ((gen_normal_fifo.fifo_empty && wvalid_i) ? wdata_i : gen_normal_fifo.storage_rdata)
             --------------------1-------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT2,T3,T15

 LINE       130
 SUB-EXPRESSION (gen_normal_fifo.fifo_empty && wvalid_i)
                 -------------1------------    ----2---
-1--2-StatusTests
01Not Covered
10CoveredT1,T2,T3
11CoveredT2,T3,T15

 LINE       131
 EXPRESSION (gen_normal_fifo.fifo_empty & ((~wvalid_i)))
             -------------1------------   ------2------
-1--2-StatusTests
01CoveredT18,T26,T58
10CoveredT2,T3,T15
11CoveredT1,T2,T3

 LINE       138
 EXPRESSION (gen_normal_fifo.empty ? (40'(0)) : gen_normal_fifo.rdata_int)
             ----------1----------
-1-StatusTests
0CoveredT2,T3,T15
1CoveredT1,T2,T3

Branch Coverage for Instance : tb.dut.u_to_rd_fifo.u_rspfifo
Line No.TotalCoveredPercent
Branches 9 9 100.00
TERNARY 130 2 2 100.00
TERNARY 138 2 2 100.00
IF 69 3 3 100.00
IF 111 2 2 100.00


130 assign rdata_int = (fifo_empty && wvalid_i) ? wdata_i : storage_rdata; -1- ==> ==>

Branches:
-1-StatusTests
1 Covered T2,T3,T15
0 Covered T1,T2,T3


138 assign rdata_o = empty ? Width'(0) : rdata_int; -1- ==> ==>

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T2,T3,T15


69 if (!rst_ni) begin -1- 70 under_rst <= 1'b1; ==> 71 end else if (under_rst) begin -2- 72 under_rst <= ~under_rst; ==> 73 end MISSING_ELSE ==>

Branches:
-1--2-StatusTests
1 - Covered T1,T2,T3
0 1 Covered T1,T2,T3
0 0 Covered T1,T2,T3


111 if (fifo_incr_wptr) begin -1- 112 storage[0] <= wdata_i; ==> 113 end MISSING_ELSE ==>

Branches:
-1-StatusTests
1 Covered T2,T3,T15
0 Covered T1,T2,T3


Assert Coverage for Instance : tb.dut.u_to_rd_fifo.u_rspfifo
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 6 6 100.00 6 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 6 6 100.00 6 100.00




Assertion Details

Name   Attempts   Real Successes   Failures   Incomplete   
DataKnown_A 361651110 4671701 0 0
DataKnown_AKnownEnable 361909267 361047510 0 0
DepthKnown_A 361909267 361047510 0 0
RvalidKnown_A 361909267 361047510 0 0
WreadyKnown_A 361909267 361047510 0 0
gen_normal_fifo.depthShallNotExceedParamDepth 361909267 4687481 0 0


DataKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 361651110 4671701 0 0
T2 1916 20 0 0
T3 33100 643 0 0
T4 4218 0 0 0
T9 4035 0 0 0
T10 6277 116 0 0
T15 1455 5 0 0
T16 2031 146 0 0
T17 1869 146 0 0
T18 195519 10627 0 0
T20 137786 88 0 0
T26 0 185 0 0
T70 0 146 0 0

DataKnown_AKnownEnable
NameAttemptsReal SuccessesFailuresIncomplete
Total 361909267 361047510 0 0
T1 1577 1514 0 0
T2 1916 1822 0 0
T3 33100 33039 0 0
T4 4218 3512 0 0
T9 4035 3976 0 0
T10 6277 6206 0 0
T15 1455 1381 0 0
T16 2031 1975 0 0
T17 1869 1775 0 0
T18 195519 195455 0 0

DepthKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 361909267 361047510 0 0
T1 1577 1514 0 0
T2 1916 1822 0 0
T3 33100 33039 0 0
T4 4218 3512 0 0
T9 4035 3976 0 0
T10 6277 6206 0 0
T15 1455 1381 0 0
T16 2031 1975 0 0
T17 1869 1775 0 0
T18 195519 195455 0 0

RvalidKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 361909267 361047510 0 0
T1 1577 1514 0 0
T2 1916 1822 0 0
T3 33100 33039 0 0
T4 4218 3512 0 0
T9 4035 3976 0 0
T10 6277 6206 0 0
T15 1455 1381 0 0
T16 2031 1975 0 0
T17 1869 1775 0 0
T18 195519 195455 0 0

WreadyKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 361909267 361047510 0 0
T1 1577 1514 0 0
T2 1916 1822 0 0
T3 33100 33039 0 0
T4 4218 3512 0 0
T9 4035 3976 0 0
T10 6277 6206 0 0
T15 1455 1381 0 0
T16 2031 1975 0 0
T17 1869 1775 0 0
T18 195519 195455 0 0

gen_normal_fifo.depthShallNotExceedParamDepth
NameAttemptsReal SuccessesFailuresIncomplete
Total 361909267 4687481 0 0
T2 1916 20 0 0
T3 33100 643 0 0
T4 4218 0 0 0
T9 4035 0 0 0
T10 6277 116 0 0
T15 1455 5 0 0
T16 2031 146 0 0
T17 1869 146 0 0
T18 195519 10627 0 0
T20 137786 88 0 0
T26 0 185 0 0
T70 0 146 0 0