Unified Coverage Report :: Module Instance :: tb.dut.u_eflash.gen_flash_cores[1].u_core.u_rd.u_rd_storage

Module Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_rd.u_rd_storage

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
90.62	100.00	62.50			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.90	100.00	79.49	100.00		90.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
97.27	100.00	89.08			100.00	100.00	u_rd

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_normal_fifo.u_fifo_cnt	89.49	100.00	91.30	100.00		66.67

Module Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_rd.u_mask_storage

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
92.19	100.00	68.75			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.75	100.00	80.56			94.44	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
97.27	100.00	89.08			100.00	100.00	u_rd

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_normal_fifo.u_fifo_cnt	93.64	100.00	90.00			90.91

Module Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_rd.u_addr_xor_storage

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
92.19	100.00	68.75			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.53	100.00	86.11			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
97.27	100.00	89.08			100.00	100.00	u_rd

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_normal_fifo.u_fifo_cnt	100.00	100.00	100.00			100.00

Line Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_rd.u_rd_storage

	Line No.	Total	Covered	Percent
TOTAL		14	14	100.00
ALWAYS	69	4	4	100.00
CONT_ASSIGN	81	1	1	100.00
CONT_ASSIGN	82	1	1	100.00
CONT_ASSIGN	100	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
CONT_ASSIGN	120	1	1	100.00
ALWAYS	123	2	2	100.00
CONT_ASSIGN	133	1	1	100.00
CONT_ASSIGN	134	1	1	100.00
CONT_ASSIGN	138	1	1	100.00

68                          always_ff @(posedge clk_i or negedge rst_ni) begin
69         1/1                if (!rst_ni) begin
           Tests:       T1 T2 T3 
70         1/1                  under_rst <= 1'b1;
           Tests:       T1 T2 T3 
71         1/1                end else if (under_rst) begin
           Tests:       T1 T2 T3 
72         1/1                  under_rst <= ~under_rst;
           Tests:       T1 T2 T3 
73                            end
                        MISSING_ELSE
74                          end
75                      
76                          logic empty;
77                      
78                          // full and not ready for write are two different concepts.
79                          // The latter can be '0' when under reset, while the former is an indication that no more
80                          // entries can be written.
81         1/1              assign wready_o = ~full_o & ~under_rst;
           Tests:       T1 T2 T3 
82         1/1              assign rvalid_o = ~empty & ~under_rst;
           Tests:       T1 T2 T3 
83                      
84                          prim_fifo_sync_cnt #(
85                            .Depth(Depth),
86                            .Secure(Secure)
87                          ) u_fifo_cnt (
88                            .clk_i,
89                            .rst_ni,
90                            .clr_i,
91                            .incr_wptr_i(fifo_incr_wptr),
92                            .incr_rptr_i(fifo_incr_rptr),
93                            .wptr_o(fifo_wptr),
94                            .rptr_o(fifo_rptr),
95                            .full_o,
96                            .empty_o(fifo_empty),
97                            .depth_o,
98                            .err_o
99                          );
100        1/1              assign fifo_incr_wptr = wvalid_i & wready_o & ~under_rst;
           Tests:       T1 T2 T3 
101        1/1              assign fifo_incr_rptr = rvalid_o & rready_i & ~under_rst;
           Tests:       T1 T2 T3 
102                     
103                         // the generate blocks below are needed to avoid lint errors due to array indexing
104                         // in the where the fifo only has one storage element
105                         logic [Depth-1:0][Width-1:0] storage;
106                         logic [Width-1:0] storage_rdata;
107                         if (Depth == 1) begin : gen_depth_eq1
108                           assign storage_rdata = storage[0];
109                     
110                           always_ff @(posedge clk_i)
111                             if (fifo_incr_wptr) begin
112                               storage[0] <= wdata_i;
113                             end
114                     
115                           logic unused_ptrs;
116                           assign unused_ptrs = ^{fifo_wptr, fifo_rptr};
117                     
118                         // fifo with more than one storage element
119                         end else begin : gen_depth_gt1
120        1/1                assign storage_rdata = storage[fifo_rptr];
           Tests:       T1 T2 T3 
121                     
122                           always_ff @(posedge clk_i)
123        1/1                  if (fifo_incr_wptr) begin
           Tests:       T1 T2 T3 
124        1/1                    storage[fifo_wptr] <= wdata_i;
           Tests:       T3 T16 T10 
125                             end
                        MISSING_ELSE
126                         end
127                     
128                         logic [Width-1:0] rdata_int;
129                         if (Pass == 1'b1) begin : gen_pass
130                           assign rdata_int = (fifo_empty && wvalid_i) ? wdata_i : storage_rdata;
131                           assign empty = fifo_empty & ~wvalid_i;
132                         end else begin : gen_nopass
133        1/1                assign rdata_int = storage_rdata;
           Tests:       T3 T16 T10 
134        1/1                assign empty = fifo_empty;
           Tests:       T1 T2 T3 
135                         end
136                     
137                         if (OutputZeroIfEmpty == 1'b1) begin : gen_output_zero
138        1/1                assign rdata_o = empty ? Width'(0) : rdata_int;
           Tests:       T1 T2 T3 

---

Cond Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_rd.u_rd_storage

	Total	Covered	Percent
Conditions	16	10	62.50
Logical	16	10	62.50
Non-Logical	0	0
Event	0	0

 LINE       81
 EXPRESSION (((~full_o)) & ((~gen_normal_fifo.under_rst)))
             -----1-----   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       82
 EXPRESSION (((~gen_normal_fifo.empty)) & ((~gen_normal_fifo.under_rst)))
             -------------1------------   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T3,T16,T10

 LINE       100
 EXPRESSION (wvalid_i & wready_o & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Not Covered
1	1	0	Not Covered
1	1	1	Covered	T3,T16,T10

 LINE       101
 EXPRESSION (rvalid_o & rready_i & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------

-1-	-2-	-3-	Status	Tests
0	1	1	Not Covered
1	0	1	Covered	T17,T11,T76
1	1	0	Not Covered
1	1	1	Covered	T3,T16,T10

 LINE       138
 EXPRESSION (gen_normal_fifo.empty ? (76'(0)) : gen_normal_fifo.rdata_int)
             ----------1----------

-1-	Status	Tests
0	Covered	T3,T16,T10
1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_rd.u_rd_storage

	Line No.	Total	Covered	Percent
Branches		7	7	100.00
TERNARY	138	2	2	100.00
IF	69	3	3	100.00
IF	111	2	2	100.00

138              assign rdata_o = empty ? Width'(0) : rdata_int;
                                        -1-  
                                        ==>  
                                        ==>  

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T3,T16,T10

69               if (!rst_ni) begin
                 -1-  
70                 under_rst <= 1'b1;
                   ==>
71               end else if (under_rst) begin
                          -2-  
72                 under_rst <= ~under_rst;
                   ==>
73               end
                 MISSING_ELSE
                 ==>

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
0	0	Covered	T1,T2,T3

111                if (fifo_incr_wptr) begin
                   -1-     
112                  storage[0] <= wdata_i;
                     ==>
113                end
                   MISSING_ELSE
                   ==>

Branches:

-1-	Status	Tests
1	Covered	T3,T16,T10
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_rd.u_rd_storage

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	6	6	100.00	6	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	6	6	100.00	6	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	361651110	12500383	0	0
DataKnown_AKnownEnable	361651110	360789353	0	0
DepthKnown_A	361651110	360789353	0	0
RvalidKnown_A	361651110	360789353	0	0
WreadyKnown_A	361651110	360789353	0	0
gen_normal_fifo.depthShallNotExceedParamDepth	361651110	12500383	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	361651110	12500383	0	0
T3	33100	208	0	0
T4	4218	0	0	0
T9	4035	0	0	0
T10	6277	119	0	0
T11	0	181	0	0
T15	1455	0	0	0
T16	2031	73	0	0
T17	1869	146	0	0
T18	195519	716	0	0
T20	137786	0	0	0
T26	94815	23	0	0
T37	0	2103	0	0
T67	0	18312	0	0
T76	0	260	0	0

DataKnown_AKnownEnable

Name	Attempts	Real Successes	Failures	Incomplete
Total	361651110	360789353	0	0
T1	1577	1514	0	0
T2	1916	1822	0	0
T3	33100	33039	0	0
T4	4218	3512	0	0
T9	4035	3976	0	0
T10	6277	6206	0	0
T15	1455	1381	0	0
T16	2031	1975	0	0
T17	1869	1775	0	0
T18	195519	195455	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	361651110	360789353	0	0
T1	1577	1514	0	0
T2	1916	1822	0	0
T3	33100	33039	0	0
T4	4218	3512	0	0
T9	4035	3976	0	0
T10	6277	6206	0	0
T15	1455	1381	0	0
T16	2031	1975	0	0
T17	1869	1775	0	0
T18	195519	195455	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	361651110	360789353	0	0
T1	1577	1514	0	0
T2	1916	1822	0	0
T3	33100	33039	0	0
T4	4218	3512	0	0
T9	4035	3976	0	0
T10	6277	6206	0	0
T15	1455	1381	0	0
T16	2031	1975	0	0
T17	1869	1775	0	0
T18	195519	195455	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	361651110	360789353	0	0
T1	1577	1514	0	0
T2	1916	1822	0	0
T3	33100	33039	0	0
T4	4218	3512	0	0
T9	4035	3976	0	0
T10	6277	6206	0	0
T15	1455	1381	0	0
T16	2031	1975	0	0
T17	1869	1775	0	0
T18	195519	195455	0	0

gen_normal_fifo.depthShallNotExceedParamDepth

Name	Attempts	Real Successes	Failures	Incomplete
Total	361651110	12500383	0	0
T3	33100	208	0	0
T4	4218	0	0	0
T9	4035	0	0	0
T10	6277	119	0	0
T11	0	181	0	0
T15	1455	0	0	0
T16	2031	73	0	0
T17	1869	146	0	0
T18	195519	716	0	0
T20	137786	0	0	0
T26	94815	23	0	0
T37	0	2103	0	0
T67	0	18312	0	0
T76	0	260	0	0

Line Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_rd.u_mask_storage

	Line No.	Total	Covered	Percent
TOTAL		14	14	100.00
ALWAYS	69	4	4	100.00
CONT_ASSIGN	81	1	1	100.00
CONT_ASSIGN	82	1	1	100.00
CONT_ASSIGN	100	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
CONT_ASSIGN	120	1	1	100.00
ALWAYS	123	2	2	100.00
CONT_ASSIGN	133	1	1	100.00
CONT_ASSIGN	134	1	1	100.00
CONT_ASSIGN	138	1	1	100.00

68                          always_ff @(posedge clk_i or negedge rst_ni) begin
69         1/1                if (!rst_ni) begin
           Tests:       T1 T2 T3 
70         1/1                  under_rst <= 1'b1;
           Tests:       T1 T2 T3 
71         1/1                end else if (under_rst) begin
           Tests:       T1 T2 T3 
72         1/1                  under_rst <= ~under_rst;
           Tests:       T1 T2 T3 
73                            end
                        MISSING_ELSE
74                          end
75                      
76                          logic empty;
77                      
78                          // full and not ready for write are two different concepts.
79                          // The latter can be '0' when under reset, while the former is an indication that no more
80                          // entries can be written.
81         1/1              assign wready_o = ~full_o & ~under_rst;
           Tests:       T1 T2 T3 
82         1/1              assign rvalid_o = ~empty & ~under_rst;
           Tests:       T1 T2 T3 
83                      
84                          prim_fifo_sync_cnt #(
85                            .Depth(Depth),
86                            .Secure(Secure)
87                          ) u_fifo_cnt (
88                            .clk_i,
89                            .rst_ni,
90                            .clr_i,
91                            .incr_wptr_i(fifo_incr_wptr),
92                            .incr_rptr_i(fifo_incr_rptr),
93                            .wptr_o(fifo_wptr),
94                            .rptr_o(fifo_rptr),
95                            .full_o,
96                            .empty_o(fifo_empty),
97                            .depth_o,
98                            .err_o
99                          );
100        1/1              assign fifo_incr_wptr = wvalid_i & wready_o & ~under_rst;
           Tests:       T1 T2 T3 
101        1/1              assign fifo_incr_rptr = rvalid_o & rready_i & ~under_rst;
           Tests:       T1 T2 T3 
102                     
103                         // the generate blocks below are needed to avoid lint errors due to array indexing
104                         // in the where the fifo only has one storage element
105                         logic [Depth-1:0][Width-1:0] storage;
106                         logic [Width-1:0] storage_rdata;
107                         if (Depth == 1) begin : gen_depth_eq1
108                           assign storage_rdata = storage[0];
109                     
110                           always_ff @(posedge clk_i)
111                             if (fifo_incr_wptr) begin
112                               storage[0] <= wdata_i;
113                             end
114                     
115                           logic unused_ptrs;
116                           assign unused_ptrs = ^{fifo_wptr, fifo_rptr};
117                     
118                         // fifo with more than one storage element
119                         end else begin : gen_depth_gt1
120        1/1                assign storage_rdata = storage[fifo_rptr];
           Tests:       T1 T2 T3 
121                     
122                           always_ff @(posedge clk_i)
123        1/1                  if (fifo_incr_wptr) begin
           Tests:       T1 T2 T3 
124        1/1                    storage[fifo_wptr] <= wdata_i;
           Tests:       T17 T11 T76 
125                             end
                        MISSING_ELSE
126                         end
127                     
128                         logic [Width-1:0] rdata_int;
129                         if (Pass == 1'b1) begin : gen_pass
130                           assign rdata_int = (fifo_empty && wvalid_i) ? wdata_i : storage_rdata;
131                           assign empty = fifo_empty & ~wvalid_i;
132                         end else begin : gen_nopass
133        1/1                assign rdata_int = storage_rdata;
           Tests:       T17 T11 T76 
134        1/1                assign empty = fifo_empty;
           Tests:       T1 T2 T3 
135                         end
136                     
137                         if (OutputZeroIfEmpty == 1'b1) begin : gen_output_zero
138        1/1                assign rdata_o = empty ? Width'(0) : rdata_int;
           Tests:       T1 T2 T3 

---

Cond Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_rd.u_mask_storage

	Total	Covered	Percent
Conditions	16	11	68.75
Logical	16	11	68.75
Non-Logical	0	0
Event	0	0

 LINE       81
 EXPRESSION (((~full_o)) & ((~gen_normal_fifo.under_rst)))
             -----1-----   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       82
 EXPRESSION (((~gen_normal_fifo.empty)) & ((~gen_normal_fifo.under_rst)))
             -------------1------------   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T17,T11,T76

 LINE       100
 EXPRESSION (wvalid_i & wready_o & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Not Covered
1	1	0	Not Covered
1	1	1	Covered	T17,T11,T76

 LINE       101
 EXPRESSION (rvalid_o & rready_i & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T3,T16,T10
1	0	1	Covered	T17,T11,T76
1	1	0	Not Covered
1	1	1	Covered	T17,T11,T76

 LINE       138
 EXPRESSION (gen_normal_fifo.empty ? (64'(0)) : gen_normal_fifo.rdata_int)
             ----------1----------

-1-	Status	Tests
0	Covered	T17,T11,T76
1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_rd.u_mask_storage

	Line No.	Total	Covered	Percent
Branches		7	7	100.00
TERNARY	138	2	2	100.00
IF	69	3	3	100.00
IF	111	2	2	100.00

138              assign rdata_o = empty ? Width'(0) : rdata_int;
                                        -1-  
                                        ==>  
                                        ==>  

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T17,T11,T76

69               if (!rst_ni) begin
                 -1-  
70                 under_rst <= 1'b1;
                   ==>
71               end else if (under_rst) begin
                          -2-  
72                 under_rst <= ~under_rst;
                   ==>
73               end
                 MISSING_ELSE
                 ==>

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
0	0	Covered	T1,T2,T3

111                if (fifo_incr_wptr) begin
                   -1-     
112                  storage[0] <= wdata_i;
                     ==>
113                end
                   MISSING_ELSE
                   ==>

Branches:

-1-	Status	Tests
1	Covered	T17,T11,T76
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_rd.u_mask_storage

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	6	6	100.00	6	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	6	6	100.00	6	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	361909267	11260858	0	0
DataKnown_AKnownEnable	361909267	361047510	0	0
DepthKnown_A	361909267	361047510	0	0
RvalidKnown_A	361909267	361047510	0	0
WreadyKnown_A	361909267	361047510	0	0
gen_normal_fifo.depthShallNotExceedParamDepth	361909267	11260858	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	361909267	11260858	0	0
T4	4218	0	0	0
T11	44559	180	0	0
T17	1869	146	0	0
T18	195519	0	0	0
T20	137786	0	0	0
T26	94815	0	0	0
T27	298904	0	0	0
T37	414356	0	0	0
T40	0	24	0	0
T41	0	8	0	0
T42	0	33	0	0
T55	0	19244	0	0
T62	0	66	0	0
T63	0	20860	0	0
T67	0	9519	0	0
T70	1526	0	0	0
T76	35846	260	0	0

DataKnown_AKnownEnable

Name	Attempts	Real Successes	Failures	Incomplete
Total	361909267	361047510	0	0
T1	1577	1514	0	0
T2	1916	1822	0	0
T3	33100	33039	0	0
T4	4218	3512	0	0
T9	4035	3976	0	0
T10	6277	6206	0	0
T15	1455	1381	0	0
T16	2031	1975	0	0
T17	1869	1775	0	0
T18	195519	195455	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	361909267	361047510	0	0
T1	1577	1514	0	0
T2	1916	1822	0	0
T3	33100	33039	0	0
T4	4218	3512	0	0
T9	4035	3976	0	0
T10	6277	6206	0	0
T15	1455	1381	0	0
T16	2031	1975	0	0
T17	1869	1775	0	0
T18	195519	195455	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	361909267	361047510	0	0
T1	1577	1514	0	0
T2	1916	1822	0	0
T3	33100	33039	0	0
T4	4218	3512	0	0
T9	4035	3976	0	0
T10	6277	6206	0	0
T15	1455	1381	0	0
T16	2031	1975	0	0
T17	1869	1775	0	0
T18	195519	195455	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	361909267	361047510	0	0
T1	1577	1514	0	0
T2	1916	1822	0	0
T3	33100	33039	0	0
T4	4218	3512	0	0
T9	4035	3976	0	0
T10	6277	6206	0	0
T15	1455	1381	0	0
T16	2031	1975	0	0
T17	1869	1775	0	0
T18	195519	195455	0	0

gen_normal_fifo.depthShallNotExceedParamDepth

Name	Attempts	Real Successes	Failures	Incomplete
Total	361909267	11260858	0	0
T4	4218	0	0	0
T11	44559	180	0	0
T17	1869	146	0	0
T18	195519	0	0	0
T20	137786	0	0	0
T26	94815	0	0	0
T27	298904	0	0	0
T37	414356	0	0	0
T40	0	24	0	0
T41	0	8	0	0
T42	0	33	0	0
T55	0	19244	0	0
T62	0	66	0	0
T63	0	20860	0	0
T67	0	9519	0	0
T70	1526	0	0	0
T76	35846	260	0	0

Line Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_rd.u_addr_xor_storage

	Line No.	Total	Covered	Percent
TOTAL		14	14	100.00
ALWAYS	69	4	4	100.00
CONT_ASSIGN	81	1	1	100.00
CONT_ASSIGN	82	1	1	100.00
CONT_ASSIGN	100	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
CONT_ASSIGN	120	1	1	100.00
ALWAYS	123	2	2	100.00
CONT_ASSIGN	133	1	1	100.00
CONT_ASSIGN	134	1	1	100.00
CONT_ASSIGN	138	1	1	100.00

68                          always_ff @(posedge clk_i or negedge rst_ni) begin
69         1/1                if (!rst_ni) begin
           Tests:       T1 T2 T3 
70         1/1                  under_rst <= 1'b1;
           Tests:       T1 T2 T3 
71         1/1                end else if (under_rst) begin
           Tests:       T1 T2 T3 
72         1/1                  under_rst <= ~under_rst;
           Tests:       T1 T2 T3 
73                            end
                        MISSING_ELSE
74                          end
75                      
76                          logic empty;
77                      
78                          // full and not ready for write are two different concepts.
79                          // The latter can be '0' when under reset, while the former is an indication that no more
80                          // entries can be written.
81         1/1              assign wready_o = ~full_o & ~under_rst;
           Tests:       T1 T2 T3 
82         1/1              assign rvalid_o = ~empty & ~under_rst;
           Tests:       T1 T2 T3 
83                      
84                          prim_fifo_sync_cnt #(
85                            .Depth(Depth),
86                            .Secure(Secure)
87                          ) u_fifo_cnt (
88                            .clk_i,
89                            .rst_ni,
90                            .clr_i,
91                            .incr_wptr_i(fifo_incr_wptr),
92                            .incr_rptr_i(fifo_incr_rptr),
93                            .wptr_o(fifo_wptr),
94                            .rptr_o(fifo_rptr),
95                            .full_o,
96                            .empty_o(fifo_empty),
97                            .depth_o,
98                            .err_o
99                          );
100        1/1              assign fifo_incr_wptr = wvalid_i & wready_o & ~under_rst;
           Tests:       T1 T2 T3 
101        1/1              assign fifo_incr_rptr = rvalid_o & rready_i & ~under_rst;
           Tests:       T1 T2 T3 
102                     
103                         // the generate blocks below are needed to avoid lint errors due to array indexing
104                         // in the where the fifo only has one storage element
105                         logic [Depth-1:0][Width-1:0] storage;
106                         logic [Width-1:0] storage_rdata;
107                         if (Depth == 1) begin : gen_depth_eq1
108                           assign storage_rdata = storage[0];
109                     
110                           always_ff @(posedge clk_i)
111                             if (fifo_incr_wptr) begin
112                               storage[0] <= wdata_i;
113                             end
114                     
115                           logic unused_ptrs;
116                           assign unused_ptrs = ^{fifo_wptr, fifo_rptr};
117                     
118                         // fifo with more than one storage element
119                         end else begin : gen_depth_gt1
120        1/1                assign storage_rdata = storage[fifo_rptr];
           Tests:       T1 T2 T3 
121                     
122                           always_ff @(posedge clk_i)
123        1/1                  if (fifo_incr_wptr) begin
           Tests:       T1 T2 T3 
124        1/1                    storage[fifo_wptr] <= wdata_i;
           Tests:       T3 T16 T10 
125                             end
                        MISSING_ELSE
126                         end
127                     
128                         logic [Width-1:0] rdata_int;
129                         if (Pass == 1'b1) begin : gen_pass
130                           assign rdata_int = (fifo_empty && wvalid_i) ? wdata_i : storage_rdata;
131                           assign empty = fifo_empty & ~wvalid_i;
132                         end else begin : gen_nopass
133        1/1                assign rdata_int = storage_rdata;
           Tests:       T3 T16 T10 
134        1/1                assign empty = fifo_empty;
           Tests:       T1 T2 T3 
135                         end
136                     
137                         if (OutputZeroIfEmpty == 1'b1) begin : gen_output_zero
138        1/1                assign rdata_o = empty ? Width'(0) : rdata_int;
           Tests:       T1 T2 T3 

---

Cond Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_rd.u_addr_xor_storage

	Total	Covered	Percent
Conditions	16	11	68.75
Logical	16	11	68.75
Non-Logical	0	0
Event	0	0

 LINE       81
 EXPRESSION (((~full_o)) & ((~gen_normal_fifo.under_rst)))
             -----1-----   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T3,T10,T11
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       82
 EXPRESSION (((~gen_normal_fifo.empty)) & ((~gen_normal_fifo.under_rst)))
             -------------1------------   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T3,T16,T10

 LINE       100
 EXPRESSION (wvalid_i & wready_o & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Not Covered
1	1	0	Not Covered
1	1	1	Covered	T3,T16,T10

 LINE       101
 EXPRESSION (rvalid_o & rready_i & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------

-1-	-2-	-3-	Status	Tests
0	1	1	Not Covered
1	0	1	Covered	T3,T16,T10
1	1	0	Not Covered
1	1	1	Covered	T3,T16,T10

 LINE       138
 EXPRESSION (gen_normal_fifo.empty ? (16'(0)) : gen_normal_fifo.rdata_int)
             ----------1----------

-1-	Status	Tests
0	Covered	T3,T16,T10
1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_rd.u_addr_xor_storage

	Line No.	Total	Covered	Percent
Branches		7	7	100.00
TERNARY	138	2	2	100.00
IF	69	3	3	100.00
IF	111	2	2	100.00

138              assign rdata_o = empty ? Width'(0) : rdata_int;
                                        -1-  
                                        ==>  
                                        ==>  

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T3,T16,T10

69               if (!rst_ni) begin
                 -1-  
70                 under_rst <= 1'b1;
                   ==>
71               end else if (under_rst) begin
                          -2-  
72                 under_rst <= ~under_rst;
                   ==>
73               end
                 MISSING_ELSE
                 ==>

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
0	0	Covered	T1,T2,T3

111                if (fifo_incr_wptr) begin
                   -1-     
112                  storage[0] <= wdata_i;
                     ==>
113                end
                   MISSING_ELSE
                   ==>

Branches:

-1-	Status	Tests
1	Covered	T3,T16,T10
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_rd.u_addr_xor_storage

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	6	6	100.00	6	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	6	6	100.00	6	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	361909267	47247416	0	0
DataKnown_AKnownEnable	361909267	361047510	0	0
DepthKnown_A	361909267	361047510	0	0
RvalidKnown_A	361909267	361047510	0	0
WreadyKnown_A	361909267	361047510	0	0
gen_normal_fifo.depthShallNotExceedParamDepth	361909267	47247416	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	361909267	47247416	0	0
T3	33100	590	0	0
T4	4218	0	0	0
T9	4035	0	0	0
T10	6277	362	0	0
T11	0	429	0	0
T15	1455	0	0	0
T16	2031	219	0	0
T17	1869	365	0	0
T18	195519	2148	0	0
T20	137786	0	0	0
T26	94815	46	0	0
T37	0	6301	0	0
T67	0	19977	0	0
T76	0	642	0	0

DataKnown_AKnownEnable

Name	Attempts	Real Successes	Failures	Incomplete
Total	361909267	361047510	0	0
T1	1577	1514	0	0
T2	1916	1822	0	0
T3	33100	33039	0	0
T4	4218	3512	0	0
T9	4035	3976	0	0
T10	6277	6206	0	0
T15	1455	1381	0	0
T16	2031	1975	0	0
T17	1869	1775	0	0
T18	195519	195455	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	361909267	361047510	0	0
T1	1577	1514	0	0
T2	1916	1822	0	0
T3	33100	33039	0	0
T4	4218	3512	0	0
T9	4035	3976	0	0
T10	6277	6206	0	0
T15	1455	1381	0	0
T16	2031	1975	0	0
T17	1869	1775	0	0
T18	195519	195455	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	361909267	361047510	0	0
T1	1577	1514	0	0
T2	1916	1822	0	0
T3	33100	33039	0	0
T4	4218	3512	0	0
T9	4035	3976	0	0
T10	6277	6206	0	0
T15	1455	1381	0	0
T16	2031	1975	0	0
T17	1869	1775	0	0
T18	195519	195455	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	361909267	361047510	0	0
T1	1577	1514	0	0
T2	1916	1822	0	0
T3	33100	33039	0	0
T4	4218	3512	0	0
T9	4035	3976	0	0
T10	6277	6206	0	0
T15	1455	1381	0	0
T16	2031	1975	0	0
T17	1869	1775	0	0
T18	195519	195455	0	0

gen_normal_fifo.depthShallNotExceedParamDepth

Name	Attempts	Real Successes	Failures	Incomplete
Total	361909267	47247416	0	0
T3	33100	590	0	0
T4	4218	0	0	0
T9	4035	0	0	0
T10	6277	362	0	0
T11	0	429	0	0
T15	1455	0	0	0
T16	2031	219	0	0
T17	1869	365	0	0
T18	195519	2148	0	0
T20	137786	0	0	0
T26	94815	46	0	0
T37	0	6301	0	0
T67	0	19977	0	0
T76	0	642	0	0