Line Coverage for Module :
prim_lc_sync ( parameter NumCopies=1,AsyncOn=1,ResetValueIsOn=0,LcResetValue=10 )
Line Coverage for Module self-instances :
| Line No. | Total | Covered | Percent |
TOTAL | | 2 | 2 | 100.00 |
ALWAYS | 68 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
67 always_ff @(posedge clk_i) begin
68 1/1 lc_en_in_sva_q <= lc_en_i;
Tests: T1 T2 T3
69 end
70 `ASSERT(OutputDelay_A,
71 rst_ni |-> ##3 lc_en_o == {NumCopies{$past(lc_en_in_sva_q, 2)}} ||
72 ($past(lc_en_in_sva_q, 2) != $past(lc_en_in_sva_q, 1)))
73 `endif
74 end else begin : gen_no_flops
75 //VCS coverage off
76 // pragma coverage off
77
78 // This unused companion logic helps remove lint errors
79 // for modules where clock and reset are used for assertions only
80 // or nothing at all.
81 // This logic will be removed for sythesis since it is unloaded.
82 lc_ctrl_pkg::lc_tx_t unused_logic;
83 always_ff @(posedge clk_i or negedge rst_ni) begin
84 if (!rst_ni) begin
85 unused_logic <= lc_ctrl_pkg::Off;
86 end else begin
87 unused_logic <= lc_en_i;
88 end
89 end
90 //VCS coverage on
91 // pragma coverage on
92
93 assign lc_en = lc_en_i;
94
95 `ASSERT(OutputDelay_A, lc_en_o == {NumCopies{lc_en_i}})
96 end
97
98 for (genvar j = 0; j < NumCopies; j++) begin : gen_buffs
99 logic [lc_ctrl_pkg::TxWidth-1:0] lc_en_out;
100 for (genvar k = 0; k < lc_ctrl_pkg::TxWidth; k++) begin : gen_bits
101 prim_sec_anchor_buf u_prim_buf (
102 .in_i(lc_en[k]),
103 .out_o(lc_en_out[k])
104 );
105 end
106 1/1 assign lc_en_o[j] = lc_ctrl_pkg::lc_tx_t'(lc_en_out);
Tests: T1 T2 T3
Line Coverage for Module :
prim_lc_sync ( parameter NumCopies=3,AsyncOn=1,ResetValueIsOn=0,LcResetValue=10 )
Line Coverage for Module self-instances :
| Line No. | Total | Covered | Percent |
TOTAL | | 4 | 4 | 100.00 |
ALWAYS | 68 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
67 always_ff @(posedge clk_i) begin
68 1/1 lc_en_in_sva_q <= lc_en_i;
Tests: T1 T2 T3
69 end
70 `ASSERT(OutputDelay_A,
71 rst_ni |-> ##3 lc_en_o == {NumCopies{$past(lc_en_in_sva_q, 2)}} ||
72 ($past(lc_en_in_sva_q, 2) != $past(lc_en_in_sva_q, 1)))
73 `endif
74 end else begin : gen_no_flops
75 //VCS coverage off
76 // pragma coverage off
77
78 // This unused companion logic helps remove lint errors
79 // for modules where clock and reset are used for assertions only
80 // or nothing at all.
81 // This logic will be removed for sythesis since it is unloaded.
82 lc_ctrl_pkg::lc_tx_t unused_logic;
83 always_ff @(posedge clk_i or negedge rst_ni) begin
84 if (!rst_ni) begin
85 unused_logic <= lc_ctrl_pkg::Off;
86 end else begin
87 unused_logic <= lc_en_i;
88 end
89 end
90 //VCS coverage on
91 // pragma coverage on
92
93 assign lc_en = lc_en_i;
94
95 `ASSERT(OutputDelay_A, lc_en_o == {NumCopies{lc_en_i}})
96 end
97
98 for (genvar j = 0; j < NumCopies; j++) begin : gen_buffs
99 logic [lc_ctrl_pkg::TxWidth-1:0] lc_en_out;
100 for (genvar k = 0; k < lc_ctrl_pkg::TxWidth; k++) begin : gen_bits
101 prim_sec_anchor_buf u_prim_buf (
102 .in_i(lc_en[k]),
103 .out_o(lc_en_out[k])
104 );
105 end
106 3/3 assign lc_en_o[j] = lc_ctrl_pkg::lc_tx_t'(lc_en_out);
Tests: T1 T2 T3 | T1 T2 T3 | T1 T2 T3
Line Coverage for Module :
prim_lc_sync ( parameter NumCopies=2,AsyncOn=0,ResetValueIsOn=0,LcResetValue=10 )
Line Coverage for Module self-instances :
| Line No. | Total | Covered | Percent |
TOTAL | | 3 | 3 | 100.00 |
ALWAYS | 84 | 0 | 0 | |
CONT_ASSIGN | 93 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
83 always_ff @(posedge clk_i or negedge rst_ni) begin
84 unreachable if (!rst_ni) begin
85 unreachable unused_logic <= lc_ctrl_pkg::Off;
86 end else begin
87 unreachable unused_logic <= lc_en_i;
88 end
89 end
90 //VCS coverage on
91 // pragma coverage on
92
93 1/1 assign lc_en = lc_en_i;
Tests: T1 T2 T3
94
95 `ASSERT(OutputDelay_A, lc_en_o == {NumCopies{lc_en_i}})
96 end
97
98 for (genvar j = 0; j < NumCopies; j++) begin : gen_buffs
99 logic [lc_ctrl_pkg::TxWidth-1:0] lc_en_out;
100 for (genvar k = 0; k < lc_ctrl_pkg::TxWidth; k++) begin : gen_bits
101 prim_sec_anchor_buf u_prim_buf (
102 .in_i(lc_en[k]),
103 .out_o(lc_en_out[k])
104 );
105 end
106 2/2 assign lc_en_o[j] = lc_ctrl_pkg::lc_tx_t'(lc_en_out);
Tests: T1 T2 T3 | T1 T2 T3
Line Coverage for Module :
prim_lc_sync ( parameter NumCopies=5,AsyncOn=1,ResetValueIsOn=0,LcResetValue=10 )
Line Coverage for Module self-instances :
| Line No. | Total | Covered | Percent |
TOTAL | | 6 | 6 | 100.00 |
ALWAYS | 68 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
67 always_ff @(posedge clk_i) begin
68 1/1 lc_en_in_sva_q <= lc_en_i;
Tests: T1 T2 T3
69 end
70 `ASSERT(OutputDelay_A,
71 rst_ni |-> ##3 lc_en_o == {NumCopies{$past(lc_en_in_sva_q, 2)}} ||
72 ($past(lc_en_in_sva_q, 2) != $past(lc_en_in_sva_q, 1)))
73 `endif
74 end else begin : gen_no_flops
75 //VCS coverage off
76 // pragma coverage off
77
78 // This unused companion logic helps remove lint errors
79 // for modules where clock and reset are used for assertions only
80 // or nothing at all.
81 // This logic will be removed for sythesis since it is unloaded.
82 lc_ctrl_pkg::lc_tx_t unused_logic;
83 always_ff @(posedge clk_i or negedge rst_ni) begin
84 if (!rst_ni) begin
85 unused_logic <= lc_ctrl_pkg::Off;
86 end else begin
87 unused_logic <= lc_en_i;
88 end
89 end
90 //VCS coverage on
91 // pragma coverage on
92
93 assign lc_en = lc_en_i;
94
95 `ASSERT(OutputDelay_A, lc_en_o == {NumCopies{lc_en_i}})
96 end
97
98 for (genvar j = 0; j < NumCopies; j++) begin : gen_buffs
99 logic [lc_ctrl_pkg::TxWidth-1:0] lc_en_out;
100 for (genvar k = 0; k < lc_ctrl_pkg::TxWidth; k++) begin : gen_bits
101 prim_sec_anchor_buf u_prim_buf (
102 .in_i(lc_en[k]),
103 .out_o(lc_en_out[k])
104 );
105 end
106 5/5 assign lc_en_o[j] = lc_ctrl_pkg::lc_tx_t'(lc_en_out);
Tests: T1 T2 T3 | T1 T2 T3 | T1 T2 T3 | T1 T2 T3 | T1 T2 T3
Assert Coverage for Module :
prim_lc_sync
Assertion Details
NumCopiesMustBeGreaterZero_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
10580 |
10580 |
0 |
0 |
T1 |
10 |
10 |
0 |
0 |
T2 |
10 |
10 |
0 |
0 |
T3 |
10 |
10 |
0 |
0 |
T8 |
10 |
10 |
0 |
0 |
T13 |
10 |
10 |
0 |
0 |
T14 |
10 |
10 |
0 |
0 |
T15 |
10 |
10 |
0 |
0 |
T16 |
10 |
10 |
0 |
0 |
T17 |
10 |
10 |
0 |
0 |
T18 |
10 |
10 |
0 |
0 |
OutputsKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
2147483647 |
2147483647 |
0 |
0 |
T1 |
11790 |
10820 |
0 |
0 |
T2 |
18630 |
17670 |
0 |
0 |
T3 |
124230 |
123350 |
0 |
0 |
T8 |
19360 |
18590 |
0 |
0 |
T13 |
36470 |
35520 |
0 |
0 |
T14 |
22090 |
21320 |
0 |
0 |
T15 |
15100 |
14550 |
0 |
0 |
T16 |
23710 |
22980 |
0 |
0 |
T17 |
1970290 |
1969390 |
0 |
0 |
T18 |
14690 |
13840 |
0 |
0 |
gen_flops.OutputDelay_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
2147483647 |
2147483647 |
0 |
22002 |
T1 |
9432 |
8632 |
0 |
24 |
T2 |
14904 |
14112 |
0 |
24 |
T3 |
99384 |
98656 |
0 |
24 |
T8 |
15488 |
14848 |
0 |
24 |
T13 |
29176 |
28392 |
0 |
24 |
T14 |
17672 |
17032 |
0 |
24 |
T15 |
12080 |
11616 |
0 |
24 |
T16 |
18968 |
18360 |
0 |
24 |
T17 |
1576232 |
1575488 |
0 |
24 |
T18 |
11752 |
11048 |
0 |
24 |
gen_no_flops.OutputDelay_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
755482910 |
753800892 |
0 |
0 |
T1 |
2358 |
2164 |
0 |
0 |
T2 |
3726 |
3534 |
0 |
0 |
T3 |
24846 |
24670 |
0 |
0 |
T8 |
3872 |
3718 |
0 |
0 |
T13 |
7294 |
7104 |
0 |
0 |
T14 |
4418 |
4264 |
0 |
0 |
T15 |
3020 |
2910 |
0 |
0 |
T16 |
4742 |
4596 |
0 |
0 |
T17 |
394058 |
393878 |
0 |
0 |
T18 |
2938 |
2768 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_region_cfg.u_lc_creator_seed_sw_rw_en_sync
| Line No. | Total | Covered | Percent |
TOTAL | | 2 | 2 | 100.00 |
ALWAYS | 68 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
67 always_ff @(posedge clk_i) begin
68 1/1 lc_en_in_sva_q <= lc_en_i;
Tests: T1 T2 T3
69 end
70 `ASSERT(OutputDelay_A,
71 rst_ni |-> ##3 lc_en_o == {NumCopies{$past(lc_en_in_sva_q, 2)}} ||
72 ($past(lc_en_in_sva_q, 2) != $past(lc_en_in_sva_q, 1)))
73 `endif
74 end else begin : gen_no_flops
75 //VCS coverage off
76 // pragma coverage off
77
78 // This unused companion logic helps remove lint errors
79 // for modules where clock and reset are used for assertions only
80 // or nothing at all.
81 // This logic will be removed for sythesis since it is unloaded.
82 lc_ctrl_pkg::lc_tx_t unused_logic;
83 always_ff @(posedge clk_i or negedge rst_ni) begin
84 if (!rst_ni) begin
85 unused_logic <= lc_ctrl_pkg::Off;
86 end else begin
87 unused_logic <= lc_en_i;
88 end
89 end
90 //VCS coverage on
91 // pragma coverage on
92
93 assign lc_en = lc_en_i;
94
95 `ASSERT(OutputDelay_A, lc_en_o == {NumCopies{lc_en_i}})
96 end
97
98 for (genvar j = 0; j < NumCopies; j++) begin : gen_buffs
99 logic [lc_ctrl_pkg::TxWidth-1:0] lc_en_out;
100 for (genvar k = 0; k < lc_ctrl_pkg::TxWidth; k++) begin : gen_bits
101 prim_sec_anchor_buf u_prim_buf (
102 .in_i(lc_en[k]),
103 .out_o(lc_en_out[k])
104 );
105 end
106 1/1 assign lc_en_o[j] = lc_ctrl_pkg::lc_tx_t'(lc_en_out);
Tests: T1 T2 T3
Assert Coverage for Instance : tb.dut.u_region_cfg.u_lc_creator_seed_sw_rw_en_sync
Assertion Details
NumCopiesMustBeGreaterZero_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
1058 |
1058 |
0 |
0 |
T1 |
1 |
1 |
0 |
0 |
T2 |
1 |
1 |
0 |
0 |
T3 |
1 |
1 |
0 |
0 |
T8 |
1 |
1 |
0 |
0 |
T13 |
1 |
1 |
0 |
0 |
T14 |
1 |
1 |
0 |
0 |
T15 |
1 |
1 |
0 |
0 |
T16 |
1 |
1 |
0 |
0 |
T17 |
1 |
1 |
0 |
0 |
T18 |
1 |
1 |
0 |
0 |
OutputsKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
377741524 |
376900515 |
0 |
0 |
T1 |
1179 |
1082 |
0 |
0 |
T2 |
1863 |
1767 |
0 |
0 |
T3 |
12423 |
12335 |
0 |
0 |
T8 |
1936 |
1859 |
0 |
0 |
T13 |
3647 |
3552 |
0 |
0 |
T14 |
2209 |
2132 |
0 |
0 |
T15 |
1510 |
1455 |
0 |
0 |
T16 |
2371 |
2298 |
0 |
0 |
T17 |
197029 |
196939 |
0 |
0 |
T18 |
1469 |
1384 |
0 |
0 |
gen_flops.OutputDelay_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
377741524 |
376867518 |
0 |
2769 |
T1 |
1179 |
1079 |
0 |
3 |
T2 |
1863 |
1764 |
0 |
3 |
T3 |
12423 |
12332 |
0 |
3 |
T8 |
1936 |
1856 |
0 |
3 |
T13 |
3647 |
3549 |
0 |
3 |
T14 |
2209 |
2129 |
0 |
3 |
T15 |
1510 |
1452 |
0 |
3 |
T16 |
2371 |
2295 |
0 |
3 |
T17 |
197029 |
196936 |
0 |
3 |
T18 |
1469 |
1381 |
0 |
3 |
Line Coverage for Instance : tb.dut.u_region_cfg.u_lc_owner_seed_sw_rw_en_sync
| Line No. | Total | Covered | Percent |
TOTAL | | 2 | 2 | 100.00 |
ALWAYS | 68 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
67 always_ff @(posedge clk_i) begin
68 1/1 lc_en_in_sva_q <= lc_en_i;
Tests: T1 T2 T3
69 end
70 `ASSERT(OutputDelay_A,
71 rst_ni |-> ##3 lc_en_o == {NumCopies{$past(lc_en_in_sva_q, 2)}} ||
72 ($past(lc_en_in_sva_q, 2) != $past(lc_en_in_sva_q, 1)))
73 `endif
74 end else begin : gen_no_flops
75 //VCS coverage off
76 // pragma coverage off
77
78 // This unused companion logic helps remove lint errors
79 // for modules where clock and reset are used for assertions only
80 // or nothing at all.
81 // This logic will be removed for sythesis since it is unloaded.
82 lc_ctrl_pkg::lc_tx_t unused_logic;
83 always_ff @(posedge clk_i or negedge rst_ni) begin
84 if (!rst_ni) begin
85 unused_logic <= lc_ctrl_pkg::Off;
86 end else begin
87 unused_logic <= lc_en_i;
88 end
89 end
90 //VCS coverage on
91 // pragma coverage on
92
93 assign lc_en = lc_en_i;
94
95 `ASSERT(OutputDelay_A, lc_en_o == {NumCopies{lc_en_i}})
96 end
97
98 for (genvar j = 0; j < NumCopies; j++) begin : gen_buffs
99 logic [lc_ctrl_pkg::TxWidth-1:0] lc_en_out;
100 for (genvar k = 0; k < lc_ctrl_pkg::TxWidth; k++) begin : gen_bits
101 prim_sec_anchor_buf u_prim_buf (
102 .in_i(lc_en[k]),
103 .out_o(lc_en_out[k])
104 );
105 end
106 1/1 assign lc_en_o[j] = lc_ctrl_pkg::lc_tx_t'(lc_en_out);
Tests: T1 T2 T3
Assert Coverage for Instance : tb.dut.u_region_cfg.u_lc_owner_seed_sw_rw_en_sync
Assertion Details
NumCopiesMustBeGreaterZero_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
1058 |
1058 |
0 |
0 |
T1 |
1 |
1 |
0 |
0 |
T2 |
1 |
1 |
0 |
0 |
T3 |
1 |
1 |
0 |
0 |
T8 |
1 |
1 |
0 |
0 |
T13 |
1 |
1 |
0 |
0 |
T14 |
1 |
1 |
0 |
0 |
T15 |
1 |
1 |
0 |
0 |
T16 |
1 |
1 |
0 |
0 |
T17 |
1 |
1 |
0 |
0 |
T18 |
1 |
1 |
0 |
0 |
OutputsKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
377741524 |
376900515 |
0 |
0 |
T1 |
1179 |
1082 |
0 |
0 |
T2 |
1863 |
1767 |
0 |
0 |
T3 |
12423 |
12335 |
0 |
0 |
T8 |
1936 |
1859 |
0 |
0 |
T13 |
3647 |
3552 |
0 |
0 |
T14 |
2209 |
2132 |
0 |
0 |
T15 |
1510 |
1455 |
0 |
0 |
T16 |
2371 |
2298 |
0 |
0 |
T17 |
197029 |
196939 |
0 |
0 |
T18 |
1469 |
1384 |
0 |
0 |
gen_flops.OutputDelay_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
377741524 |
376867518 |
0 |
2769 |
T1 |
1179 |
1079 |
0 |
3 |
T2 |
1863 |
1764 |
0 |
3 |
T3 |
12423 |
12332 |
0 |
3 |
T8 |
1936 |
1856 |
0 |
3 |
T13 |
3647 |
3549 |
0 |
3 |
T14 |
2209 |
2129 |
0 |
3 |
T15 |
1510 |
1452 |
0 |
3 |
T16 |
2371 |
2295 |
0 |
3 |
T17 |
197029 |
196936 |
0 |
3 |
T18 |
1469 |
1381 |
0 |
3 |
Line Coverage for Instance : tb.dut.u_region_cfg.u_lc_iso_part_sw_rd_en_sync
| Line No. | Total | Covered | Percent |
TOTAL | | 2 | 2 | 100.00 |
ALWAYS | 68 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
67 always_ff @(posedge clk_i) begin
68 1/1 lc_en_in_sva_q <= lc_en_i;
Tests: T1 T2 T3
69 end
70 `ASSERT(OutputDelay_A,
71 rst_ni |-> ##3 lc_en_o == {NumCopies{$past(lc_en_in_sva_q, 2)}} ||
72 ($past(lc_en_in_sva_q, 2) != $past(lc_en_in_sva_q, 1)))
73 `endif
74 end else begin : gen_no_flops
75 //VCS coverage off
76 // pragma coverage off
77
78 // This unused companion logic helps remove lint errors
79 // for modules where clock and reset are used for assertions only
80 // or nothing at all.
81 // This logic will be removed for sythesis since it is unloaded.
82 lc_ctrl_pkg::lc_tx_t unused_logic;
83 always_ff @(posedge clk_i or negedge rst_ni) begin
84 if (!rst_ni) begin
85 unused_logic <= lc_ctrl_pkg::Off;
86 end else begin
87 unused_logic <= lc_en_i;
88 end
89 end
90 //VCS coverage on
91 // pragma coverage on
92
93 assign lc_en = lc_en_i;
94
95 `ASSERT(OutputDelay_A, lc_en_o == {NumCopies{lc_en_i}})
96 end
97
98 for (genvar j = 0; j < NumCopies; j++) begin : gen_buffs
99 logic [lc_ctrl_pkg::TxWidth-1:0] lc_en_out;
100 for (genvar k = 0; k < lc_ctrl_pkg::TxWidth; k++) begin : gen_bits
101 prim_sec_anchor_buf u_prim_buf (
102 .in_i(lc_en[k]),
103 .out_o(lc_en_out[k])
104 );
105 end
106 1/1 assign lc_en_o[j] = lc_ctrl_pkg::lc_tx_t'(lc_en_out);
Tests: T1 T2 T3
Assert Coverage for Instance : tb.dut.u_region_cfg.u_lc_iso_part_sw_rd_en_sync
Assertion Details
NumCopiesMustBeGreaterZero_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
1058 |
1058 |
0 |
0 |
T1 |
1 |
1 |
0 |
0 |
T2 |
1 |
1 |
0 |
0 |
T3 |
1 |
1 |
0 |
0 |
T8 |
1 |
1 |
0 |
0 |
T13 |
1 |
1 |
0 |
0 |
T14 |
1 |
1 |
0 |
0 |
T15 |
1 |
1 |
0 |
0 |
T16 |
1 |
1 |
0 |
0 |
T17 |
1 |
1 |
0 |
0 |
T18 |
1 |
1 |
0 |
0 |
OutputsKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
377741524 |
376900515 |
0 |
0 |
T1 |
1179 |
1082 |
0 |
0 |
T2 |
1863 |
1767 |
0 |
0 |
T3 |
12423 |
12335 |
0 |
0 |
T8 |
1936 |
1859 |
0 |
0 |
T13 |
3647 |
3552 |
0 |
0 |
T14 |
2209 |
2132 |
0 |
0 |
T15 |
1510 |
1455 |
0 |
0 |
T16 |
2371 |
2298 |
0 |
0 |
T17 |
197029 |
196939 |
0 |
0 |
T18 |
1469 |
1384 |
0 |
0 |
gen_flops.OutputDelay_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
377741524 |
376867518 |
0 |
2769 |
T1 |
1179 |
1079 |
0 |
3 |
T2 |
1863 |
1764 |
0 |
3 |
T3 |
12423 |
12332 |
0 |
3 |
T8 |
1936 |
1856 |
0 |
3 |
T13 |
3647 |
3549 |
0 |
3 |
T14 |
2209 |
2129 |
0 |
3 |
T15 |
1510 |
1452 |
0 |
3 |
T16 |
2371 |
2295 |
0 |
3 |
T17 |
197029 |
196936 |
0 |
3 |
T18 |
1469 |
1381 |
0 |
3 |
Line Coverage for Instance : tb.dut.u_region_cfg.u_lc_iso_part_sw_wr_en_sync
| Line No. | Total | Covered | Percent |
TOTAL | | 2 | 2 | 100.00 |
ALWAYS | 68 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
67 always_ff @(posedge clk_i) begin
68 1/1 lc_en_in_sva_q <= lc_en_i;
Tests: T1 T2 T3
69 end
70 `ASSERT(OutputDelay_A,
71 rst_ni |-> ##3 lc_en_o == {NumCopies{$past(lc_en_in_sva_q, 2)}} ||
72 ($past(lc_en_in_sva_q, 2) != $past(lc_en_in_sva_q, 1)))
73 `endif
74 end else begin : gen_no_flops
75 //VCS coverage off
76 // pragma coverage off
77
78 // This unused companion logic helps remove lint errors
79 // for modules where clock and reset are used for assertions only
80 // or nothing at all.
81 // This logic will be removed for sythesis since it is unloaded.
82 lc_ctrl_pkg::lc_tx_t unused_logic;
83 always_ff @(posedge clk_i or negedge rst_ni) begin
84 if (!rst_ni) begin
85 unused_logic <= lc_ctrl_pkg::Off;
86 end else begin
87 unused_logic <= lc_en_i;
88 end
89 end
90 //VCS coverage on
91 // pragma coverage on
92
93 assign lc_en = lc_en_i;
94
95 `ASSERT(OutputDelay_A, lc_en_o == {NumCopies{lc_en_i}})
96 end
97
98 for (genvar j = 0; j < NumCopies; j++) begin : gen_buffs
99 logic [lc_ctrl_pkg::TxWidth-1:0] lc_en_out;
100 for (genvar k = 0; k < lc_ctrl_pkg::TxWidth; k++) begin : gen_bits
101 prim_sec_anchor_buf u_prim_buf (
102 .in_i(lc_en[k]),
103 .out_o(lc_en_out[k])
104 );
105 end
106 1/1 assign lc_en_o[j] = lc_ctrl_pkg::lc_tx_t'(lc_en_out);
Tests: T1 T2 T3
Assert Coverage for Instance : tb.dut.u_region_cfg.u_lc_iso_part_sw_wr_en_sync
Assertion Details
NumCopiesMustBeGreaterZero_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
1058 |
1058 |
0 |
0 |
T1 |
1 |
1 |
0 |
0 |
T2 |
1 |
1 |
0 |
0 |
T3 |
1 |
1 |
0 |
0 |
T8 |
1 |
1 |
0 |
0 |
T13 |
1 |
1 |
0 |
0 |
T14 |
1 |
1 |
0 |
0 |
T15 |
1 |
1 |
0 |
0 |
T16 |
1 |
1 |
0 |
0 |
T17 |
1 |
1 |
0 |
0 |
T18 |
1 |
1 |
0 |
0 |
OutputsKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
377741524 |
376900515 |
0 |
0 |
T1 |
1179 |
1082 |
0 |
0 |
T2 |
1863 |
1767 |
0 |
0 |
T3 |
12423 |
12335 |
0 |
0 |
T8 |
1936 |
1859 |
0 |
0 |
T13 |
3647 |
3552 |
0 |
0 |
T14 |
2209 |
2132 |
0 |
0 |
T15 |
1510 |
1455 |
0 |
0 |
T16 |
2371 |
2298 |
0 |
0 |
T17 |
197029 |
196939 |
0 |
0 |
T18 |
1469 |
1384 |
0 |
0 |
gen_flops.OutputDelay_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
377741524 |
376867518 |
0 |
2769 |
T1 |
1179 |
1079 |
0 |
3 |
T2 |
1863 |
1764 |
0 |
3 |
T3 |
12423 |
12332 |
0 |
3 |
T8 |
1936 |
1856 |
0 |
3 |
T13 |
3647 |
3549 |
0 |
3 |
T14 |
2209 |
2129 |
0 |
3 |
T15 |
1510 |
1452 |
0 |
3 |
T16 |
2371 |
2295 |
0 |
3 |
T17 |
197029 |
196936 |
0 |
3 |
T18 |
1469 |
1381 |
0 |
3 |
Line Coverage for Instance : tb.dut.u_lc_seed_hw_rd_en_sync
| Line No. | Total | Covered | Percent |
TOTAL | | 2 | 2 | 100.00 |
ALWAYS | 68 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
67 always_ff @(posedge clk_i) begin
68 1/1 lc_en_in_sva_q <= lc_en_i;
Tests: T1 T2 T3
69 end
70 `ASSERT(OutputDelay_A,
71 rst_ni |-> ##3 lc_en_o == {NumCopies{$past(lc_en_in_sva_q, 2)}} ||
72 ($past(lc_en_in_sva_q, 2) != $past(lc_en_in_sva_q, 1)))
73 `endif
74 end else begin : gen_no_flops
75 //VCS coverage off
76 // pragma coverage off
77
78 // This unused companion logic helps remove lint errors
79 // for modules where clock and reset are used for assertions only
80 // or nothing at all.
81 // This logic will be removed for sythesis since it is unloaded.
82 lc_ctrl_pkg::lc_tx_t unused_logic;
83 always_ff @(posedge clk_i or negedge rst_ni) begin
84 if (!rst_ni) begin
85 unused_logic <= lc_ctrl_pkg::Off;
86 end else begin
87 unused_logic <= lc_en_i;
88 end
89 end
90 //VCS coverage on
91 // pragma coverage on
92
93 assign lc_en = lc_en_i;
94
95 `ASSERT(OutputDelay_A, lc_en_o == {NumCopies{lc_en_i}})
96 end
97
98 for (genvar j = 0; j < NumCopies; j++) begin : gen_buffs
99 logic [lc_ctrl_pkg::TxWidth-1:0] lc_en_out;
100 for (genvar k = 0; k < lc_ctrl_pkg::TxWidth; k++) begin : gen_bits
101 prim_sec_anchor_buf u_prim_buf (
102 .in_i(lc_en[k]),
103 .out_o(lc_en_out[k])
104 );
105 end
106 1/1 assign lc_en_o[j] = lc_ctrl_pkg::lc_tx_t'(lc_en_out);
Tests: T1 T2 T3
Assert Coverage for Instance : tb.dut.u_lc_seed_hw_rd_en_sync
Assertion Details
NumCopiesMustBeGreaterZero_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
1058 |
1058 |
0 |
0 |
T1 |
1 |
1 |
0 |
0 |
T2 |
1 |
1 |
0 |
0 |
T3 |
1 |
1 |
0 |
0 |
T8 |
1 |
1 |
0 |
0 |
T13 |
1 |
1 |
0 |
0 |
T14 |
1 |
1 |
0 |
0 |
T15 |
1 |
1 |
0 |
0 |
T16 |
1 |
1 |
0 |
0 |
T17 |
1 |
1 |
0 |
0 |
T18 |
1 |
1 |
0 |
0 |
OutputsKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
377741524 |
376900515 |
0 |
0 |
T1 |
1179 |
1082 |
0 |
0 |
T2 |
1863 |
1767 |
0 |
0 |
T3 |
12423 |
12335 |
0 |
0 |
T8 |
1936 |
1859 |
0 |
0 |
T13 |
3647 |
3552 |
0 |
0 |
T14 |
2209 |
2132 |
0 |
0 |
T15 |
1510 |
1455 |
0 |
0 |
T16 |
2371 |
2298 |
0 |
0 |
T17 |
197029 |
196939 |
0 |
0 |
T18 |
1469 |
1384 |
0 |
0 |
gen_flops.OutputDelay_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
377741524 |
376867518 |
0 |
2769 |
T1 |
1179 |
1079 |
0 |
3 |
T2 |
1863 |
1764 |
0 |
3 |
T3 |
12423 |
12332 |
0 |
3 |
T8 |
1936 |
1856 |
0 |
3 |
T13 |
3647 |
3549 |
0 |
3 |
T14 |
2209 |
2129 |
0 |
3 |
T15 |
1510 |
1452 |
0 |
3 |
T16 |
2371 |
2295 |
0 |
3 |
T17 |
197029 |
196936 |
0 |
3 |
T18 |
1469 |
1381 |
0 |
3 |
Line Coverage for Instance : tb.dut.u_flash_hw_if.u_sync_rma_req
| Line No. | Total | Covered | Percent |
TOTAL | | 4 | 4 | 100.00 |
ALWAYS | 68 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
67 always_ff @(posedge clk_i) begin
68 1/1 lc_en_in_sva_q <= lc_en_i;
Tests: T1 T2 T3
69 end
70 `ASSERT(OutputDelay_A,
71 rst_ni |-> ##3 lc_en_o == {NumCopies{$past(lc_en_in_sva_q, 2)}} ||
72 ($past(lc_en_in_sva_q, 2) != $past(lc_en_in_sva_q, 1)))
73 `endif
74 end else begin : gen_no_flops
75 //VCS coverage off
76 // pragma coverage off
77
78 // This unused companion logic helps remove lint errors
79 // for modules where clock and reset are used for assertions only
80 // or nothing at all.
81 // This logic will be removed for sythesis since it is unloaded.
82 lc_ctrl_pkg::lc_tx_t unused_logic;
83 always_ff @(posedge clk_i or negedge rst_ni) begin
84 if (!rst_ni) begin
85 unused_logic <= lc_ctrl_pkg::Off;
86 end else begin
87 unused_logic <= lc_en_i;
88 end
89 end
90 //VCS coverage on
91 // pragma coverage on
92
93 assign lc_en = lc_en_i;
94
95 `ASSERT(OutputDelay_A, lc_en_o == {NumCopies{lc_en_i}})
96 end
97
98 for (genvar j = 0; j < NumCopies; j++) begin : gen_buffs
99 logic [lc_ctrl_pkg::TxWidth-1:0] lc_en_out;
100 for (genvar k = 0; k < lc_ctrl_pkg::TxWidth; k++) begin : gen_bits
101 prim_sec_anchor_buf u_prim_buf (
102 .in_i(lc_en[k]),
103 .out_o(lc_en_out[k])
104 );
105 end
106 3/3 assign lc_en_o[j] = lc_ctrl_pkg::lc_tx_t'(lc_en_out);
Tests: T1 T2 T3 | T1 T2 T3 | T1 T2 T3
Assert Coverage for Instance : tb.dut.u_flash_hw_if.u_sync_rma_req
Assertion Details
NumCopiesMustBeGreaterZero_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
1058 |
1058 |
0 |
0 |
T1 |
1 |
1 |
0 |
0 |
T2 |
1 |
1 |
0 |
0 |
T3 |
1 |
1 |
0 |
0 |
T8 |
1 |
1 |
0 |
0 |
T13 |
1 |
1 |
0 |
0 |
T14 |
1 |
1 |
0 |
0 |
T15 |
1 |
1 |
0 |
0 |
T16 |
1 |
1 |
0 |
0 |
T17 |
1 |
1 |
0 |
0 |
T18 |
1 |
1 |
0 |
0 |
OutputsKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
377741524 |
376900515 |
0 |
0 |
T1 |
1179 |
1082 |
0 |
0 |
T2 |
1863 |
1767 |
0 |
0 |
T3 |
12423 |
12335 |
0 |
0 |
T8 |
1936 |
1859 |
0 |
0 |
T13 |
3647 |
3552 |
0 |
0 |
T14 |
2209 |
2132 |
0 |
0 |
T15 |
1510 |
1455 |
0 |
0 |
T16 |
2371 |
2298 |
0 |
0 |
T17 |
197029 |
196939 |
0 |
0 |
T18 |
1469 |
1384 |
0 |
0 |
gen_flops.OutputDelay_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
377741524 |
376867518 |
0 |
2769 |
T1 |
1179 |
1079 |
0 |
3 |
T2 |
1863 |
1764 |
0 |
3 |
T3 |
12423 |
12332 |
0 |
3 |
T8 |
1936 |
1856 |
0 |
3 |
T13 |
3647 |
3549 |
0 |
3 |
T14 |
2209 |
2129 |
0 |
3 |
T15 |
1510 |
1452 |
0 |
3 |
T16 |
2371 |
2295 |
0 |
3 |
T17 |
197029 |
196936 |
0 |
3 |
T18 |
1469 |
1381 |
0 |
3 |
Line Coverage for Instance : tb.dut.u_prog_tl_gate.u_err_en_sync
| Line No. | Total | Covered | Percent |
TOTAL | | 3 | 3 | 100.00 |
ALWAYS | 84 | 0 | 0 | |
CONT_ASSIGN | 93 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
83 always_ff @(posedge clk_i or negedge rst_ni) begin
84 unreachable if (!rst_ni) begin
85 unreachable unused_logic <= lc_ctrl_pkg::Off;
86 end else begin
87 unreachable unused_logic <= lc_en_i;
88 end
89 end
90 //VCS coverage on
91 // pragma coverage on
92
93 1/1 assign lc_en = lc_en_i;
Tests: T1 T2 T3
94
95 `ASSERT(OutputDelay_A, lc_en_o == {NumCopies{lc_en_i}})
96 end
97
98 for (genvar j = 0; j < NumCopies; j++) begin : gen_buffs
99 logic [lc_ctrl_pkg::TxWidth-1:0] lc_en_out;
100 for (genvar k = 0; k < lc_ctrl_pkg::TxWidth; k++) begin : gen_bits
101 prim_sec_anchor_buf u_prim_buf (
102 .in_i(lc_en[k]),
103 .out_o(lc_en_out[k])
104 );
105 end
106 2/2 assign lc_en_o[j] = lc_ctrl_pkg::lc_tx_t'(lc_en_out);
Tests: T1 T2 T3 | T1 T2 T3
Assert Coverage for Instance : tb.dut.u_prog_tl_gate.u_err_en_sync
Assertion Details
NumCopiesMustBeGreaterZero_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
1058 |
1058 |
0 |
0 |
T1 |
1 |
1 |
0 |
0 |
T2 |
1 |
1 |
0 |
0 |
T3 |
1 |
1 |
0 |
0 |
T8 |
1 |
1 |
0 |
0 |
T13 |
1 |
1 |
0 |
0 |
T14 |
1 |
1 |
0 |
0 |
T15 |
1 |
1 |
0 |
0 |
T16 |
1 |
1 |
0 |
0 |
T17 |
1 |
1 |
0 |
0 |
T18 |
1 |
1 |
0 |
0 |
OutputsKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
377741455 |
376900446 |
0 |
0 |
T1 |
1179 |
1082 |
0 |
0 |
T2 |
1863 |
1767 |
0 |
0 |
T3 |
12423 |
12335 |
0 |
0 |
T8 |
1936 |
1859 |
0 |
0 |
T13 |
3647 |
3552 |
0 |
0 |
T14 |
2209 |
2132 |
0 |
0 |
T15 |
1510 |
1455 |
0 |
0 |
T16 |
2371 |
2298 |
0 |
0 |
T17 |
197029 |
196939 |
0 |
0 |
T18 |
1469 |
1384 |
0 |
0 |
gen_no_flops.OutputDelay_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
377741455 |
376900446 |
0 |
0 |
T1 |
1179 |
1082 |
0 |
0 |
T2 |
1863 |
1767 |
0 |
0 |
T3 |
12423 |
12335 |
0 |
0 |
T8 |
1936 |
1859 |
0 |
0 |
T13 |
3647 |
3552 |
0 |
0 |
T14 |
2209 |
2132 |
0 |
0 |
T15 |
1510 |
1455 |
0 |
0 |
T16 |
2371 |
2298 |
0 |
0 |
T17 |
197029 |
196939 |
0 |
0 |
T18 |
1469 |
1384 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_lc_escalation_en_sync
| Line No. | Total | Covered | Percent |
TOTAL | | 2 | 2 | 100.00 |
ALWAYS | 68 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
67 always_ff @(posedge clk_i) begin
68 1/1 lc_en_in_sva_q <= lc_en_i;
Tests: T1 T2 T3
69 end
70 `ASSERT(OutputDelay_A,
71 rst_ni |-> ##3 lc_en_o == {NumCopies{$past(lc_en_in_sva_q, 2)}} ||
72 ($past(lc_en_in_sva_q, 2) != $past(lc_en_in_sva_q, 1)))
73 `endif
74 end else begin : gen_no_flops
75 //VCS coverage off
76 // pragma coverage off
77
78 // This unused companion logic helps remove lint errors
79 // for modules where clock and reset are used for assertions only
80 // or nothing at all.
81 // This logic will be removed for sythesis since it is unloaded.
82 lc_ctrl_pkg::lc_tx_t unused_logic;
83 always_ff @(posedge clk_i or negedge rst_ni) begin
84 if (!rst_ni) begin
85 unused_logic <= lc_ctrl_pkg::Off;
86 end else begin
87 unused_logic <= lc_en_i;
88 end
89 end
90 //VCS coverage on
91 // pragma coverage on
92
93 assign lc_en = lc_en_i;
94
95 `ASSERT(OutputDelay_A, lc_en_o == {NumCopies{lc_en_i}})
96 end
97
98 for (genvar j = 0; j < NumCopies; j++) begin : gen_buffs
99 logic [lc_ctrl_pkg::TxWidth-1:0] lc_en_out;
100 for (genvar k = 0; k < lc_ctrl_pkg::TxWidth; k++) begin : gen_bits
101 prim_sec_anchor_buf u_prim_buf (
102 .in_i(lc_en[k]),
103 .out_o(lc_en_out[k])
104 );
105 end
106 1/1 assign lc_en_o[j] = lc_ctrl_pkg::lc_tx_t'(lc_en_out);
Tests: T1 T2 T3
Assert Coverage for Instance : tb.dut.u_lc_escalation_en_sync
Assertion Details
NumCopiesMustBeGreaterZero_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
1058 |
1058 |
0 |
0 |
T1 |
1 |
1 |
0 |
0 |
T2 |
1 |
1 |
0 |
0 |
T3 |
1 |
1 |
0 |
0 |
T8 |
1 |
1 |
0 |
0 |
T13 |
1 |
1 |
0 |
0 |
T14 |
1 |
1 |
0 |
0 |
T15 |
1 |
1 |
0 |
0 |
T16 |
1 |
1 |
0 |
0 |
T17 |
1 |
1 |
0 |
0 |
T18 |
1 |
1 |
0 |
0 |
OutputsKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
377718875 |
376877866 |
0 |
0 |
T1 |
1179 |
1082 |
0 |
0 |
T2 |
1863 |
1767 |
0 |
0 |
T3 |
12423 |
12335 |
0 |
0 |
T8 |
1936 |
1859 |
0 |
0 |
T13 |
3647 |
3552 |
0 |
0 |
T14 |
2209 |
2132 |
0 |
0 |
T15 |
1510 |
1455 |
0 |
0 |
T16 |
2371 |
2298 |
0 |
0 |
T17 |
197029 |
196939 |
0 |
0 |
T18 |
1469 |
1384 |
0 |
0 |
gen_flops.OutputDelay_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
377718875 |
376845019 |
0 |
2619 |
T1 |
1179 |
1079 |
0 |
3 |
T2 |
1863 |
1764 |
0 |
3 |
T3 |
12423 |
12332 |
0 |
3 |
T8 |
1936 |
1856 |
0 |
3 |
T13 |
3647 |
3549 |
0 |
3 |
T14 |
2209 |
2129 |
0 |
3 |
T15 |
1510 |
1452 |
0 |
3 |
T16 |
2371 |
2295 |
0 |
3 |
T17 |
197029 |
196936 |
0 |
3 |
T18 |
1469 |
1381 |
0 |
3 |
Line Coverage for Instance : tb.dut.u_tl_gate.u_err_en_sync
| Line No. | Total | Covered | Percent |
TOTAL | | 3 | 3 | 100.00 |
ALWAYS | 84 | 0 | 0 | |
CONT_ASSIGN | 93 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
83 always_ff @(posedge clk_i or negedge rst_ni) begin
84 unreachable if (!rst_ni) begin
85 unreachable unused_logic <= lc_ctrl_pkg::Off;
86 end else begin
87 unreachable unused_logic <= lc_en_i;
88 end
89 end
90 //VCS coverage on
91 // pragma coverage on
92
93 1/1 assign lc_en = lc_en_i;
Tests: T1 T2 T3
94
95 `ASSERT(OutputDelay_A, lc_en_o == {NumCopies{lc_en_i}})
96 end
97
98 for (genvar j = 0; j < NumCopies; j++) begin : gen_buffs
99 logic [lc_ctrl_pkg::TxWidth-1:0] lc_en_out;
100 for (genvar k = 0; k < lc_ctrl_pkg::TxWidth; k++) begin : gen_bits
101 prim_sec_anchor_buf u_prim_buf (
102 .in_i(lc_en[k]),
103 .out_o(lc_en_out[k])
104 );
105 end
106 2/2 assign lc_en_o[j] = lc_ctrl_pkg::lc_tx_t'(lc_en_out);
Tests: T1 T2 T3 | T1 T2 T3
Assert Coverage for Instance : tb.dut.u_tl_gate.u_err_en_sync
Assertion Details
NumCopiesMustBeGreaterZero_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
1058 |
1058 |
0 |
0 |
T1 |
1 |
1 |
0 |
0 |
T2 |
1 |
1 |
0 |
0 |
T3 |
1 |
1 |
0 |
0 |
T8 |
1 |
1 |
0 |
0 |
T13 |
1 |
1 |
0 |
0 |
T14 |
1 |
1 |
0 |
0 |
T15 |
1 |
1 |
0 |
0 |
T16 |
1 |
1 |
0 |
0 |
T17 |
1 |
1 |
0 |
0 |
T18 |
1 |
1 |
0 |
0 |
OutputsKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
377741455 |
376900446 |
0 |
0 |
T1 |
1179 |
1082 |
0 |
0 |
T2 |
1863 |
1767 |
0 |
0 |
T3 |
12423 |
12335 |
0 |
0 |
T8 |
1936 |
1859 |
0 |
0 |
T13 |
3647 |
3552 |
0 |
0 |
T14 |
2209 |
2132 |
0 |
0 |
T15 |
1510 |
1455 |
0 |
0 |
T16 |
2371 |
2298 |
0 |
0 |
T17 |
197029 |
196939 |
0 |
0 |
T18 |
1469 |
1384 |
0 |
0 |
gen_no_flops.OutputDelay_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
377741455 |
376900446 |
0 |
0 |
T1 |
1179 |
1082 |
0 |
0 |
T2 |
1863 |
1767 |
0 |
0 |
T3 |
12423 |
12335 |
0 |
0 |
T8 |
1936 |
1859 |
0 |
0 |
T13 |
3647 |
3552 |
0 |
0 |
T14 |
2209 |
2132 |
0 |
0 |
T15 |
1510 |
1455 |
0 |
0 |
T16 |
2371 |
2298 |
0 |
0 |
T17 |
197029 |
196939 |
0 |
0 |
T18 |
1469 |
1384 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_eflash.u_lc_nvm_debug_en_sync
| Line No. | Total | Covered | Percent |
TOTAL | | 6 | 6 | 100.00 |
ALWAYS | 68 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
67 always_ff @(posedge clk_i) begin
68 1/1 lc_en_in_sva_q <= lc_en_i;
Tests: T1 T2 T3
69 end
70 `ASSERT(OutputDelay_A,
71 rst_ni |-> ##3 lc_en_o == {NumCopies{$past(lc_en_in_sva_q, 2)}} ||
72 ($past(lc_en_in_sva_q, 2) != $past(lc_en_in_sva_q, 1)))
73 `endif
74 end else begin : gen_no_flops
75 //VCS coverage off
76 // pragma coverage off
77
78 // This unused companion logic helps remove lint errors
79 // for modules where clock and reset are used for assertions only
80 // or nothing at all.
81 // This logic will be removed for sythesis since it is unloaded.
82 lc_ctrl_pkg::lc_tx_t unused_logic;
83 always_ff @(posedge clk_i or negedge rst_ni) begin
84 if (!rst_ni) begin
85 unused_logic <= lc_ctrl_pkg::Off;
86 end else begin
87 unused_logic <= lc_en_i;
88 end
89 end
90 //VCS coverage on
91 // pragma coverage on
92
93 assign lc_en = lc_en_i;
94
95 `ASSERT(OutputDelay_A, lc_en_o == {NumCopies{lc_en_i}})
96 end
97
98 for (genvar j = 0; j < NumCopies; j++) begin : gen_buffs
99 logic [lc_ctrl_pkg::TxWidth-1:0] lc_en_out;
100 for (genvar k = 0; k < lc_ctrl_pkg::TxWidth; k++) begin : gen_bits
101 prim_sec_anchor_buf u_prim_buf (
102 .in_i(lc_en[k]),
103 .out_o(lc_en_out[k])
104 );
105 end
106 5/5 assign lc_en_o[j] = lc_ctrl_pkg::lc_tx_t'(lc_en_out);
Tests: T1 T2 T3 | T1 T2 T3 | T1 T2 T3 | T1 T2 T3 | T1 T2 T3
Assert Coverage for Instance : tb.dut.u_eflash.u_lc_nvm_debug_en_sync
Assertion Details
NumCopiesMustBeGreaterZero_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
1058 |
1058 |
0 |
0 |
T1 |
1 |
1 |
0 |
0 |
T2 |
1 |
1 |
0 |
0 |
T3 |
1 |
1 |
0 |
0 |
T8 |
1 |
1 |
0 |
0 |
T13 |
1 |
1 |
0 |
0 |
T14 |
1 |
1 |
0 |
0 |
T15 |
1 |
1 |
0 |
0 |
T16 |
1 |
1 |
0 |
0 |
T17 |
1 |
1 |
0 |
0 |
T18 |
1 |
1 |
0 |
0 |
OutputsKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
377741455 |
376900446 |
0 |
0 |
T1 |
1179 |
1082 |
0 |
0 |
T2 |
1863 |
1767 |
0 |
0 |
T3 |
12423 |
12335 |
0 |
0 |
T8 |
1936 |
1859 |
0 |
0 |
T13 |
3647 |
3552 |
0 |
0 |
T14 |
2209 |
2132 |
0 |
0 |
T15 |
1510 |
1455 |
0 |
0 |
T16 |
2371 |
2298 |
0 |
0 |
T17 |
197029 |
196939 |
0 |
0 |
T18 |
1469 |
1384 |
0 |
0 |
gen_flops.OutputDelay_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
377741455 |
376867464 |
0 |
2769 |
T1 |
1179 |
1079 |
0 |
3 |
T2 |
1863 |
1764 |
0 |
3 |
T3 |
12423 |
12332 |
0 |
3 |
T8 |
1936 |
1856 |
0 |
3 |
T13 |
3647 |
3549 |
0 |
3 |
T14 |
2209 |
2129 |
0 |
3 |
T15 |
1510 |
1452 |
0 |
3 |
T16 |
2371 |
2295 |
0 |
3 |
T17 |
197029 |
196936 |
0 |
3 |
T18 |
1469 |
1381 |
0 |
3 |