Unified Coverage Report :: Module :: prim_count

Module : prim_count

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.09			99.09

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_prim_count_0/rtl/prim_count.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_otp_ctrl_lfsr_timer.u_prim_count_integ	93.60			93.60
tb.dut.u_otp_ctrl_lfsr_timer.u_prim_count_cnsty	93.60			93.60
tb.dut.u_otp_ctrl_scrmbl.u_prim_count	100.00			100.00
tb.dut.u_otp_ctrl_dai.u_prim_count	100.00			100.00
tb.dut.u_otp_ctrl_lci.u_prim_count	100.00			100.00
tb.dut.u_otp_ctrl_kdi.u_prim_count_seed	100.00			100.00
tb.dut.u_otp_ctrl_kdi.u_prim_count_entropy	100.00			100.00
tb.dut.gen_partitions[3].gen_buffered.u_part_buf.u_prim_count	100.00			100.00
tb.dut.gen_partitions[4].gen_buffered.u_part_buf.u_prim_count	100.00			100.00
tb.dut.gen_partitions[5].gen_buffered.u_part_buf.u_prim_count	100.00			100.00
tb.dut.gen_partitions[6].gen_buffered.u_part_buf.u_prim_count	100.00			100.00
tb.dut.gen_partitions[7].gen_lifecycle.u_part_buf.u_prim_count	100.00			100.00

---

Module Instance : tb.dut.u_otp_ctrl_lfsr_timer.u_prim_count_integ

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.60			93.60

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.60			93.60

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
95.93	100.00	88.46		100.00	91.18	100.00	u_otp_ctrl_lfsr_timer

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_otp_ctrl_lfsr_timer.u_prim_count_cnsty

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.60			93.60

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.60			93.60

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
95.93	100.00	88.46		100.00	91.18	100.00	u_otp_ctrl_lfsr_timer

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_otp_ctrl_scrmbl.u_prim_count

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
97.95	91.67	100.00		100.00	98.08	100.00	u_otp_ctrl_scrmbl

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_otp_ctrl_dai.u_prim_count

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
91.25	94.47	88.75		85.96	87.06	100.00	u_otp_ctrl_dai

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_otp_ctrl_lci.u_prim_count

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00		100.00	100.00	100.00	u_otp_ctrl_lci

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_otp_ctrl_kdi.u_prim_count_seed

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
94.62	98.59	94.44		90.91	89.13	100.00	u_otp_ctrl_kdi

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_otp_ctrl_kdi.u_prim_count_entropy

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
94.62	98.59	94.44		90.91	89.13	100.00	u_otp_ctrl_kdi

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.gen_partitions[3].gen_buffered.u_part_buf.u_prim_count

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
84.62	82.50	90.00		89.66	78.57	82.35	gen_partitions[3].gen_buffered.u_part_buf

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.gen_partitions[4].gen_buffered.u_part_buf.u_prim_count

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
90.61	91.88	87.50		94.44	84.93	94.29	gen_partitions[4].gen_buffered.u_part_buf

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.gen_partitions[5].gen_buffered.u_part_buf.u_prim_count

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
90.61	91.88	87.50		94.44	84.93	94.29	gen_partitions[5].gen_buffered.u_part_buf

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.gen_partitions[6].gen_buffered.u_part_buf.u_prim_count

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
90.05	91.88	87.50		91.67	84.93	94.29	gen_partitions[6].gen_buffered.u_part_buf

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.gen_partitions[7].gen_lifecycle.u_part_buf.u_prim_count

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
79.92	71.76	78.57		95.24	72.22	81.82	gen_partitions[7].gen_lifecycle.u_part_buf

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Toggle Coverage for Module : prim_count ( parameter Width=8,ResetValue=0,EnableAlertTriggerSVA=1,NumCnt=2 )
Toggle Coverage for Module self-instances :

SCORE	TOGGLE
100.00	100.00

tb.dut.u_otp_ctrl_dai.u_prim_count

	Total	Covered	Percent
Totals	7	7	100.00
Total Bits	42	42	100.00
Total Bits 0->1	21	21	100.00
Total Bits 1->0	21	21	100.00

Ports	7	7	100.00
Port Bits	42	42	100.00
Port Bits 0->1	21	21	100.00
Port Bits 1->0	21	21	100.00

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
clk_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
rst_ni	Yes	Yes	T1,T2,T4	Yes	T1,T2,T3	INPUT
clr_i	Yes	Yes	T1,T2,T4	Yes	T1,T2,T4	INPUT
set_i	Unreachable	Unreachable		Unreachable		INPUT
set_cnt_i[7:0]	Unreachable	Unreachable		Unreachable		INPUT
incr_en_i	Yes	Yes	T1,T4,T5	Yes	T1,T4,T5	INPUT
decr_en_i	Unreachable	Unreachable		Unreachable		INPUT
step_i[7:0]	Unreachable	Unreachable		Unreachable		INPUT
cnt_o[7:0]	Yes	Yes	T1,T4,T5	Yes	T1,T4,T5	OUTPUT
cnt_next_o[7:0]	Yes	Yes	T1,T4,T5	Yes	T1,T4,T5	OUTPUT
err_o	Yes	Yes	T16,T17,T18	Yes	T16,T17,T18	OUTPUT

---

Toggle Coverage for Module : prim_count ( parameter Width=4,ResetValue=0,EnableAlertTriggerSVA=1,NumCnt=2 )
Toggle Coverage for Module self-instances :

SCORE	TOGGLE
100.00	100.00

tb.dut.gen_partitions[3].gen_buffered.u_part_buf.u_prim_count

SCORE	TOGGLE
100.00	100.00

tb.dut.gen_partitions[5].gen_buffered.u_part_buf.u_prim_count

SCORE	TOGGLE
100.00	100.00

tb.dut.gen_partitions[6].gen_buffered.u_part_buf.u_prim_count

SCORE	TOGGLE
100.00	100.00

tb.dut.gen_partitions[7].gen_lifecycle.u_part_buf.u_prim_count

	Total	Covered	Percent
Totals	7	7	100.00
Total Bits	26	26	100.00
Total Bits 0->1	13	13	100.00
Total Bits 1->0	13	13	100.00

Ports	7	7	100.00
Port Bits	26	26	100.00
Port Bits 0->1	13	13	100.00
Port Bits 1->0	13	13	100.00

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
clk_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
rst_ni	Yes	Yes	T1,T2,T4	Yes	T1,T2,T3	INPUT
clr_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
set_i	Unreachable	Unreachable		Unreachable		INPUT
set_cnt_i[3:0]	Unreachable	Unreachable		Unreachable		INPUT
incr_en_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
decr_en_i	Unreachable	Unreachable		Unreachable		INPUT
step_i[3:0]	Unreachable	Unreachable		Unreachable		INPUT
cnt_o[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
cnt_next_o[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
err_o	Yes	Yes	T16,T17,T18	Yes	T16,T17,T18	OUTPUT

---

Toggle Coverage for Module : prim_count ( parameter Width=40,ResetValue=0,EnableAlertTriggerSVA=1,NumCnt=2 )
Toggle Coverage for Module self-instances :

SCORE	TOGGLE
93.60	93.60

tb.dut.u_otp_ctrl_lfsr_timer.u_prim_count_integ

SCORE	TOGGLE
93.60	93.60

tb.dut.u_otp_ctrl_lfsr_timer.u_prim_count_cnsty

	Total	Covered	Percent
Totals	8	7	87.50
Total Bits	250	234	93.60
Total Bits 0->1	125	117	93.60
Total Bits 1->0	125	117	93.60

Ports	8	7	87.50
Port Bits	250	234	93.60
Port Bits 0->1	125	117	93.60
Port Bits 1->0	125	117	93.60

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
clk_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
rst_ni	Yes	Yes	T1,T2,T4	Yes	T1,T2,T3	INPUT
clr_i	Unreachable	Unreachable		Unreachable		INPUT
set_i	Yes	Yes	T1,T4,T5	Yes	T1,T4,T5	INPUT
set_cnt_i[31:0]	Yes	Yes	T1,T4,*T5	Yes	T1,T4,T5	INPUT
set_cnt_i[39:32]	No	No		No		INPUT
incr_en_i	Unreachable	Unreachable		Unreachable		INPUT
decr_en_i	Yes	Yes	T1,T4,T5	Yes	T1,T4,T5	INPUT
step_i[39:0]	Unreachable	Unreachable		Unreachable		INPUT
cnt_o[39:0]	Yes	Yes	T1,T4,T5	Yes	T1,T4,T5	OUTPUT
cnt_next_o[39:0]	Yes	Yes	T1,T4,T5	Yes	T1,T4,T5	OUTPUT
err_o	Yes	Yes	T16,T17,T18	Yes	T16,T17,T18	OUTPUT

*Tests covering at least one bit in the range

---

Toggle Coverage for Module : prim_count ( parameter Width=2,ResetValue=0,EnableAlertTriggerSVA=1,NumCnt=2 )
Toggle Coverage for Module self-instances :

SCORE	TOGGLE
100.00	100.00

tb.dut.u_otp_ctrl_kdi.u_prim_count_seed

SCORE	TOGGLE
100.00	100.00

tb.dut.u_otp_ctrl_kdi.u_prim_count_entropy

	Total	Covered	Percent
Totals	7	7	100.00
Total Bits	18	18	100.00
Total Bits 0->1	9	9	100.00
Total Bits 1->0	9	9	100.00

Ports	7	7	100.00
Port Bits	18	18	100.00
Port Bits 0->1	9	9	100.00
Port Bits 1->0	9	9	100.00

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
clk_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
rst_ni	Yes	Yes	T1,T2,T4	Yes	T1,T2,T3	INPUT
clr_i	Yes	Yes	T1,T4,T5	Yes	T1,T4,T5	INPUT
set_i	Unreachable	Unreachable		Unreachable		INPUT
set_cnt_i[1:0]	Unreachable	Unreachable		Unreachable		INPUT
incr_en_i	Yes	Yes	T1,T4,T5	Yes	T1,T4,T5	INPUT
decr_en_i	Unreachable	Unreachable		Unreachable		INPUT
step_i[1:0]	Unreachable	Unreachable		Unreachable		INPUT
cnt_o[1:0]	Yes	Yes	T1,T4,T5	Yes	T1,T4,T5	OUTPUT
cnt_next_o[1:0]	Yes	Yes	T1,T4,T5	Yes	T1,T4,T5	OUTPUT
err_o	Yes	Yes	T16,T17,T18	Yes	T16,T17,T18	OUTPUT

---

Toggle Coverage for Module : prim_count ( parameter Width=6,ResetValue=0,EnableAlertTriggerSVA=1,NumCnt=2 )
Toggle Coverage for Module self-instances :

SCORE	TOGGLE
100.00	100.00

tb.dut.u_otp_ctrl_lci.u_prim_count

	Total	Covered	Percent
Totals	7	7	100.00
Total Bits	34	34	100.00
Total Bits 0->1	17	17	100.00
Total Bits 1->0	17	17	100.00

Ports	7	7	100.00
Port Bits	34	34	100.00
Port Bits 0->1	17	17	100.00
Port Bits 1->0	17	17	100.00

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
clk_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
rst_ni	Yes	Yes	T1,T2,T4	Yes	T1,T2,T3	INPUT
clr_i	Yes	Yes	T1,T4,T5	Yes	T1,T4,T5	INPUT
set_i	Unreachable	Unreachable		Unreachable		INPUT
set_cnt_i[5:0]	Unreachable	Unreachable		Unreachable		INPUT
incr_en_i	Yes	Yes	T1,T4,T5	Yes	T1,T4,T5	INPUT
decr_en_i	Unreachable	Unreachable		Unreachable		INPUT
step_i[5:0]	Unreachable	Unreachable		Unreachable		INPUT
cnt_o[5:0]	Yes	Yes	T1,T4,T5	Yes	T1,T4,T5	OUTPUT
cnt_next_o[5:0]	Yes	Yes	T1,T4,T5	Yes	T1,T4,T5	OUTPUT
err_o	Yes	Yes	T16,T17,T18	Yes	T16,T17,T18	OUTPUT

---

Toggle Coverage for Module : prim_count ( parameter Width=3,ResetValue=0,EnableAlertTriggerSVA=1,NumCnt=2 )
Toggle Coverage for Module self-instances :

SCORE	TOGGLE
100.00	100.00

tb.dut.gen_partitions[4].gen_buffered.u_part_buf.u_prim_count

	Total	Covered	Percent
Totals	7	7	100.00
Total Bits	22	22	100.00
Total Bits 0->1	11	11	100.00
Total Bits 1->0	11	11	100.00

Ports	7	7	100.00
Port Bits	22	22	100.00
Port Bits 0->1	11	11	100.00
Port Bits 1->0	11	11	100.00

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
clk_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
rst_ni	Yes	Yes	T1,T2,T4	Yes	T1,T2,T3	INPUT
clr_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
set_i	Unreachable	Unreachable		Unreachable		INPUT
set_cnt_i[2:0]	Unreachable	Unreachable		Unreachable		INPUT
incr_en_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
decr_en_i	Unreachable	Unreachable		Unreachable		INPUT
step_i[2:0]	Unreachable	Unreachable		Unreachable		INPUT
cnt_o[2:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
cnt_next_o[2:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
err_o	Yes	Yes	T16,T17,T18	Yes	T16,T17,T18	OUTPUT

---

Toggle Coverage for Module : prim_count ( parameter Width=5,ResetValue=0,EnableAlertTriggerSVA=1,NumCnt=2 )
Toggle Coverage for Module self-instances :

SCORE	TOGGLE
100.00	100.00

tb.dut.u_otp_ctrl_scrmbl.u_prim_count

	Total	Covered	Percent
Totals	7	7	100.00
Total Bits	30	30	100.00
Total Bits 0->1	15	15	100.00
Total Bits 1->0	15	15	100.00

Ports	7	7	100.00
Port Bits	30	30	100.00
Port Bits 0->1	15	15	100.00
Port Bits 1->0	15	15	100.00

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
clk_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
rst_ni	Yes	Yes	T1,T2,T4	Yes	T1,T2,T3	INPUT
clr_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
set_i	Unreachable	Unreachable		Unreachable		INPUT
set_cnt_i[4:0]	Unreachable	Unreachable		Unreachable		INPUT
incr_en_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
decr_en_i	Unreachable	Unreachable		Unreachable		INPUT
step_i[4:0]	Unreachable	Unreachable		Unreachable		INPUT
cnt_o[4:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
cnt_next_o[4:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
err_o	Yes	Yes	T16,T17,T18	Yes	T16,T17,T18	OUTPUT

Toggle Coverage for Instance : tb.dut.u_otp_ctrl_lfsr_timer.u_prim_count_integ

	Total	Covered	Percent
Totals	8	7	87.50
Total Bits	250	234	93.60
Total Bits 0->1	125	117	93.60
Total Bits 1->0	125	117	93.60

Ports	8	7	87.50
Port Bits	250	234	93.60
Port Bits 0->1	125	117	93.60
Port Bits 1->0	125	117	93.60

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
clk_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
rst_ni	Yes	Yes	T1,T2,T4	Yes	T1,T2,T3	INPUT
clr_i	Unreachable	Unreachable		Unreachable		INPUT
set_i	Yes	Yes	T1,T4,T8	Yes	T1,T4,T8	INPUT
set_cnt_i[31:0]	Yes	Yes	T1,T4,*T5	Yes	T1,T4,T5	INPUT
set_cnt_i[39:32]	No	No		No		INPUT
incr_en_i	Unreachable	Unreachable		Unreachable		INPUT
decr_en_i	Yes	Yes	T1,T4,T8	Yes	T1,T4,T8	INPUT
step_i[39:0]	Unreachable	Unreachable		Unreachable		INPUT
cnt_o[39:0]	Yes	Yes	T1,T4,T8	Yes	T1,T4,T8	OUTPUT
cnt_next_o[39:0]	Yes	Yes	T1,T4,T8	Yes	T1,T4,T8	OUTPUT
err_o	Yes	Yes	T16,T17,T18	Yes	T16,T17,T18	OUTPUT

*Tests covering at least one bit in the range

Toggle Coverage for Instance : tb.dut.u_otp_ctrl_lfsr_timer.u_prim_count_cnsty

	Total	Covered	Percent
Totals	8	7	87.50
Total Bits	250	234	93.60
Total Bits 0->1	125	117	93.60
Total Bits 1->0	125	117	93.60

Ports	8	7	87.50
Port Bits	250	234	93.60
Port Bits 0->1	125	117	93.60
Port Bits 1->0	125	117	93.60

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
clk_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
rst_ni	Yes	Yes	T1,T2,T4	Yes	T1,T2,T3	INPUT
clr_i	Unreachable	Unreachable		Unreachable		INPUT
set_i	Yes	Yes	T1,T4,T5	Yes	T1,T4,T5	INPUT
set_cnt_i[31:0]	Yes	Yes	T1,T4,*T5	Yes	T1,T4,T5	INPUT
set_cnt_i[39:32]	No	No		No		INPUT
incr_en_i	Unreachable	Unreachable		Unreachable		INPUT
decr_en_i	Yes	Yes	T1,T4,T5	Yes	T1,T4,T5	INPUT
step_i[39:0]	Unreachable	Unreachable		Unreachable		INPUT
cnt_o[39:0]	Yes	Yes	T1,T4,T5	Yes	T1,T4,T5	OUTPUT
cnt_next_o[39:0]	Yes	Yes	T1,T4,T5	Yes	T1,T4,T5	OUTPUT
err_o	Yes	Yes	T16,T17,T18	Yes	T16,T17,T18	OUTPUT

*Tests covering at least one bit in the range

Toggle Coverage for Instance : tb.dut.u_otp_ctrl_scrmbl.u_prim_count

	Total	Covered	Percent
Totals	7	7	100.00
Total Bits	30	30	100.00
Total Bits 0->1	15	15	100.00
Total Bits 1->0	15	15	100.00

Ports	7	7	100.00
Port Bits	30	30	100.00
Port Bits 0->1	15	15	100.00
Port Bits 1->0	15	15	100.00

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
clk_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
rst_ni	Yes	Yes	T1,T2,T4	Yes	T1,T2,T3	INPUT
clr_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
set_i	Unreachable	Unreachable		Unreachable		INPUT
set_cnt_i[4:0]	Unreachable	Unreachable		Unreachable		INPUT
incr_en_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
decr_en_i	Unreachable	Unreachable		Unreachable		INPUT
step_i[4:0]	Unreachable	Unreachable		Unreachable		INPUT
cnt_o[4:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
cnt_next_o[4:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
err_o	Yes	Yes	T16,T17,T18	Yes	T16,T17,T18	OUTPUT

Toggle Coverage for Instance : tb.dut.u_otp_ctrl_dai.u_prim_count

	Total	Covered	Percent
Totals	7	7	100.00
Total Bits	42	42	100.00
Total Bits 0->1	21	21	100.00
Total Bits 1->0	21	21	100.00

Ports	7	7	100.00
Port Bits	42	42	100.00
Port Bits 0->1	21	21	100.00
Port Bits 1->0	21	21	100.00

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
clk_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
rst_ni	Yes	Yes	T1,T2,T4	Yes	T1,T2,T3	INPUT
clr_i	Yes	Yes	T1,T2,T4	Yes	T1,T2,T4	INPUT
set_i	Unreachable	Unreachable		Unreachable		INPUT
set_cnt_i[7:0]	Unreachable	Unreachable		Unreachable		INPUT
incr_en_i	Yes	Yes	T1,T4,T5	Yes	T1,T4,T5	INPUT
decr_en_i	Unreachable	Unreachable		Unreachable		INPUT
step_i[7:0]	Unreachable	Unreachable		Unreachable		INPUT
cnt_o[7:0]	Yes	Yes	T1,T4,T5	Yes	T1,T4,T5	OUTPUT
cnt_next_o[7:0]	Yes	Yes	T1,T4,T5	Yes	T1,T4,T5	OUTPUT
err_o	Yes	Yes	T16,T17,T18	Yes	T16,T17,T18	OUTPUT

Toggle Coverage for Instance : tb.dut.u_otp_ctrl_lci.u_prim_count

	Total	Covered	Percent
Totals	7	7	100.00
Total Bits	34	34	100.00
Total Bits 0->1	17	17	100.00
Total Bits 1->0	17	17	100.00

Ports	7	7	100.00
Port Bits	34	34	100.00
Port Bits 0->1	17	17	100.00
Port Bits 1->0	17	17	100.00

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
clk_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
rst_ni	Yes	Yes	T1,T2,T4	Yes	T1,T2,T3	INPUT
clr_i	Yes	Yes	T1,T4,T5	Yes	T1,T4,T5	INPUT
set_i	Unreachable	Unreachable		Unreachable		INPUT
set_cnt_i[5:0]	Unreachable	Unreachable		Unreachable		INPUT
incr_en_i	Yes	Yes	T1,T4,T5	Yes	T1,T4,T5	INPUT
decr_en_i	Unreachable	Unreachable		Unreachable		INPUT
step_i[5:0]	Unreachable	Unreachable		Unreachable		INPUT
cnt_o[5:0]	Yes	Yes	T1,T4,T5	Yes	T1,T4,T5	OUTPUT
cnt_next_o[5:0]	Yes	Yes	T1,T4,T5	Yes	T1,T4,T5	OUTPUT
err_o	Yes	Yes	T16,T17,T18	Yes	T16,T17,T18	OUTPUT

Toggle Coverage for Instance : tb.dut.u_otp_ctrl_kdi.u_prim_count_seed

	Total	Covered	Percent
Totals	7	7	100.00
Total Bits	18	18	100.00
Total Bits 0->1	9	9	100.00
Total Bits 1->0	9	9	100.00

Ports	7	7	100.00
Port Bits	18	18	100.00
Port Bits 0->1	9	9	100.00
Port Bits 1->0	9	9	100.00

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
clk_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
rst_ni	Yes	Yes	T1,T2,T4	Yes	T1,T2,T3	INPUT
clr_i	Yes	Yes	T1,T4,T5	Yes	T1,T4,T5	INPUT
set_i	Unreachable	Unreachable		Unreachable		INPUT
set_cnt_i[1:0]	Unreachable	Unreachable		Unreachable		INPUT
incr_en_i	Yes	Yes	T1,T4,T5	Yes	T1,T4,T5	INPUT
decr_en_i	Unreachable	Unreachable		Unreachable		INPUT
step_i[1:0]	Unreachable	Unreachable		Unreachable		INPUT
cnt_o[1:0]	Yes	Yes	T1,T4,T5	Yes	T1,T4,T5	OUTPUT
cnt_next_o[1:0]	Yes	Yes	T1,T4,T5	Yes	T1,T4,T5	OUTPUT
err_o	Yes	Yes	T16,T17,T18	Yes	T16,T17,T18	OUTPUT

Toggle Coverage for Instance : tb.dut.u_otp_ctrl_kdi.u_prim_count_entropy

	Total	Covered	Percent
Totals	7	7	100.00
Total Bits	18	18	100.00
Total Bits 0->1	9	9	100.00
Total Bits 1->0	9	9	100.00

Ports	7	7	100.00
Port Bits	18	18	100.00
Port Bits 0->1	9	9	100.00
Port Bits 1->0	9	9	100.00

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
clk_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
rst_ni	Yes	Yes	T1,T2,T4	Yes	T1,T2,T3	INPUT
clr_i	Yes	Yes	T1,T4,T5	Yes	T1,T4,T5	INPUT
set_i	Unreachable	Unreachable		Unreachable		INPUT
set_cnt_i[1:0]	Unreachable	Unreachable		Unreachable		INPUT
incr_en_i	Yes	Yes	T1,T4,T5	Yes	T1,T4,T5	INPUT
decr_en_i	Unreachable	Unreachable		Unreachable		INPUT
step_i[1:0]	Unreachable	Unreachable		Unreachable		INPUT
cnt_o[1:0]	Yes	Yes	T1,T4,T5	Yes	T1,T4,T5	OUTPUT
cnt_next_o[1:0]	Yes	Yes	T1,T4,T5	Yes	T1,T4,T5	OUTPUT
err_o	Yes	Yes	T16,T17,T18	Yes	T16,T17,T18	OUTPUT

Toggle Coverage for Instance : tb.dut.gen_partitions[3].gen_buffered.u_part_buf.u_prim_count

	Total	Covered	Percent
Totals	7	7	100.00
Total Bits	26	26	100.00
Total Bits 0->1	13	13	100.00
Total Bits 1->0	13	13	100.00

Ports	7	7	100.00
Port Bits	26	26	100.00
Port Bits 0->1	13	13	100.00
Port Bits 1->0	13	13	100.00

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
clk_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
rst_ni	Yes	Yes	T1,T2,T4	Yes	T1,T2,T3	INPUT
clr_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
set_i	Unreachable	Unreachable		Unreachable		INPUT
set_cnt_i[3:0]	Unreachable	Unreachable		Unreachable		INPUT
incr_en_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
decr_en_i	Unreachable	Unreachable		Unreachable		INPUT
step_i[3:0]	Unreachable	Unreachable		Unreachable		INPUT
cnt_o[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
cnt_next_o[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
err_o	Yes	Yes	T16,T17,T18	Yes	T16,T17,T18	OUTPUT

Toggle Coverage for Instance : tb.dut.gen_partitions[4].gen_buffered.u_part_buf.u_prim_count

	Total	Covered	Percent
Totals	7	7	100.00
Total Bits	22	22	100.00
Total Bits 0->1	11	11	100.00
Total Bits 1->0	11	11	100.00

Ports	7	7	100.00
Port Bits	22	22	100.00
Port Bits 0->1	11	11	100.00
Port Bits 1->0	11	11	100.00

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
clk_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
rst_ni	Yes	Yes	T1,T2,T4	Yes	T1,T2,T3	INPUT
clr_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
set_i	Unreachable	Unreachable		Unreachable		INPUT
set_cnt_i[2:0]	Unreachable	Unreachable		Unreachable		INPUT
incr_en_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
decr_en_i	Unreachable	Unreachable		Unreachable		INPUT
step_i[2:0]	Unreachable	Unreachable		Unreachable		INPUT
cnt_o[2:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
cnt_next_o[2:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
err_o	Yes	Yes	T16,T17,T18	Yes	T16,T17,T18	OUTPUT

Toggle Coverage for Instance : tb.dut.gen_partitions[5].gen_buffered.u_part_buf.u_prim_count

	Total	Covered	Percent
Totals	7	7	100.00
Total Bits	26	26	100.00
Total Bits 0->1	13	13	100.00
Total Bits 1->0	13	13	100.00

Ports	7	7	100.00
Port Bits	26	26	100.00
Port Bits 0->1	13	13	100.00
Port Bits 1->0	13	13	100.00

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
clk_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
rst_ni	Yes	Yes	T1,T2,T4	Yes	T1,T2,T3	INPUT
clr_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
set_i	Unreachable	Unreachable		Unreachable		INPUT
set_cnt_i[3:0]	Unreachable	Unreachable		Unreachable		INPUT
incr_en_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
decr_en_i	Unreachable	Unreachable		Unreachable		INPUT
step_i[3:0]	Unreachable	Unreachable		Unreachable		INPUT
cnt_o[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
cnt_next_o[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
err_o	Yes	Yes	T16,T17,T18	Yes	T16,T17,T18	OUTPUT

Toggle Coverage for Instance : tb.dut.gen_partitions[6].gen_buffered.u_part_buf.u_prim_count

	Total	Covered	Percent
Totals	7	7	100.00
Total Bits	26	26	100.00
Total Bits 0->1	13	13	100.00
Total Bits 1->0	13	13	100.00

Ports	7	7	100.00
Port Bits	26	26	100.00
Port Bits 0->1	13	13	100.00
Port Bits 1->0	13	13	100.00

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
clk_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
rst_ni	Yes	Yes	T1,T2,T4	Yes	T1,T2,T3	INPUT
clr_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
set_i	Unreachable	Unreachable		Unreachable		INPUT
set_cnt_i[3:0]	Unreachable	Unreachable		Unreachable		INPUT
incr_en_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
decr_en_i	Unreachable	Unreachable		Unreachable		INPUT
step_i[3:0]	Unreachable	Unreachable		Unreachable		INPUT
cnt_o[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
cnt_next_o[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
err_o	Yes	Yes	T16,T17,T18	Yes	T16,T17,T18	OUTPUT

Toggle Coverage for Instance : tb.dut.gen_partitions[7].gen_lifecycle.u_part_buf.u_prim_count

	Total	Covered	Percent
Totals	7	7	100.00
Total Bits	26	26	100.00
Total Bits 0->1	13	13	100.00
Total Bits 1->0	13	13	100.00

Ports	7	7	100.00
Port Bits	26	26	100.00
Port Bits 0->1	13	13	100.00
Port Bits 1->0	13	13	100.00

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
clk_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
rst_ni	Yes	Yes	T1,T2,T4	Yes	T1,T2,T3	INPUT
clr_i	Yes	Yes	T1,T4,T5	Yes	T1,T4,T5	INPUT
set_i	Unreachable	Unreachable		Unreachable		INPUT
set_cnt_i[3:0]	Unreachable	Unreachable		Unreachable		INPUT
incr_en_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
decr_en_i	Unreachable	Unreachable		Unreachable		INPUT
step_i[3:0]	Unreachable	Unreachable		Unreachable		INPUT
cnt_o[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
cnt_next_o[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
err_o	Yes	Yes	T16,T17,T18	Yes	T16,T17,T18	OUTPUT