Unified Coverage Report :: Module :: otp_ctrl_scrmbl

Module : otp_ctrl_scrmbl

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.95	91.67	100.00		100.00	98.08	100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_ip_otp_ctrl_1.0/rtl/otp_ctrl_scrmbl.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_otp_ctrl_scrmbl	97.95	91.67	100.00		100.00	98.08	100.00

---

Module Instance : tb.dut.u_otp_ctrl_scrmbl

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.95	91.67	100.00		100.00	98.08	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.62	81.50	100.00	100.00	100.00	98.21	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.04	97.89	88.57	96.78		96.97	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_anchor_digests[0].u_const_anchor_buf	0.00	0.00
gen_anchor_digests[0].u_iv_anchor_buf	0.00	0.00
gen_anchor_digests[1].u_const_anchor_buf	0.00	0.00
gen_anchor_digests[1].u_iv_anchor_buf	0.00	0.00
gen_anchor_digests[2].u_const_anchor_buf	0.00	0.00
gen_anchor_digests[2].u_iv_anchor_buf	0.00	0.00
gen_anchor_digests[3].u_const_anchor_buf	0.00	0.00
gen_anchor_digests[3].u_iv_anchor_buf	0.00	0.00
gen_anchor_keys[0].u_key_anchor_buf	0.00	0.00
gen_anchor_keys[1].u_key_anchor_buf	0.00	0.00
gen_anchor_keys[2].u_key_anchor_buf	0.00	0.00
u_prim_count	100.00			100.00
u_prim_present_dec	100.00	100.00	100.00			100.00	100.00
u_prim_present_enc	100.00	100.00	100.00			100.00	100.00
u_state_regs	100.00	100.00				100.00	100.00

---

Since this is the module's only instance, the coverage report is the same as for the module.

Line Coverage for Module : otp_ctrl_scrmbl

	Line No.	Total	Covered	Percent
TOTAL		120	110	91.67
ALWAYS	141	10	0	0.00
CONT_ASSIGN	198	1	1	100.00
CONT_ASSIGN	199	1	1	100.00
CONT_ASSIGN	200	1	1	100.00
CONT_ASSIGN	201	1	1	100.00
CONT_ASSIGN	208	1	1	100.00
CONT_ASSIGN	214	1	1	100.00
CONT_ASSIGN	223	1	1	100.00
CONT_ASSIGN	229	1	1	100.00
CONT_ASSIGN	230	1	1	100.00
CONT_ASSIGN	233	1	1	100.00
CONT_ASSIGN	280	1	1	100.00
ALWAYS	300	75	75	100.00
ALWAYS	474	3	3	100.00
ALWAYS	477	21	21	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_otp_ctrl_1.0/rtl/otp_ctrl_scrmbl.sv' or '../src/lowrisc_ip_otp_ctrl_1.0/rtl/otp_ctrl_scrmbl.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
141	0	1
142	0	1
143	0	1
144	0	1
146	0	1
147	0	1
150	0	1
154	0	1
155	0	1
156	0	1
198	1	1
199	1	1
200	1	1
201	1	1
208	1	1
214	1	1
223	1	1
229	1	1
230	1	1
233	1	1
280	1	1
300	1	1
301	1	1
302	1	1
303	1	1
304	1	1
305	1	1
306	1	1
307	1	1
308	1	1
309	1	1
310	1	1
311	1	1
312	1	1
313	1	1
314	1	1
316	1	1
321	1	1
322	1	1
324	1	1
325	1	1
327	1	1
328	1	1
329	1	1
330	1	1
333	1	1
334	1	1
335	1	1
336	1	1
339	1	1
340	1	1
342	1	1
346	1	1
347	1	1
348	1	1
349	1	1
350	1	1
353	1	1
354	1	1
355	1	1
358	1	1
359	1	1
360	1	1
361	1	1
362	1	1
363	1	1
			MISSING_ELSE
372	1	1
373	1	1
374	1	1
375	1	1
376	1	1
377	1	1
378	1	1
379	1	1
			MISSING_ELSE
385	1	1
386	1	1
387	1	1
388	1	1
389	1	1
390	1	1
391	1	1
392	1	1
			MISSING_ELSE
399	1	1
400	1	1
401	1	1
402	1	1
403	1	1
404	1	1
405	1	1
406	1	1
408	1	1
412	1	1
			MISSING_ELSE
418	1	1
432	1	1
433	1	1
434	1	1
			MISSING_ELSE
474	3	3
477	1	1
478	1	1
479	1	1
480	1	1
481	1	1
482	1	1
483	1	1
484	1	1
486	1	1
487	1	1
490	1	1
491	1	1
492	1	1
			MISSING_ELSE
494	1	1
495	1	1
			MISSING_ELSE
497	1	1
498	1	1
499	1	1
500	1	1
			MISSING_ELSE
502	1	1
503	1	1
			MISSING_ELSE

---

Cond Coverage for Module : otp_ctrl_scrmbl

	Total	Covered	Percent
Conditions	68	68	100.00
Logical	68	68	100.00
Non-Logical	0	0
Event	0	0

 LINE       208
 EXPRESSION 
 Number  Term
      1  (data_state_sel == SelEncDataOut) ? enc_data_out : ((data_state_sel == SelDecDataOut) ? dec_data_out : ((data_state_sel == SelDigestState) ? digest_state_q : ((data_state_sel == SelEncDataOutXor) ? enc_data_out_xor : data_i))))

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       208
 SUB-EXPRESSION (data_state_sel == SelEncDataOut)
                ----------------1----------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       208
 SUB-EXPRESSION 
 Number  Term
      1  (data_state_sel == SelDecDataOut) ? dec_data_out : ((data_state_sel == SelDigestState) ? digest_state_q : ((data_state_sel == SelEncDataOutXor) ? enc_data_out_xor : data_i)))

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       208
 SUB-EXPRESSION (data_state_sel == SelDecDataOut)
                ----------------1----------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       208
 SUB-EXPRESSION ((data_state_sel == SelDigestState) ? digest_state_q : ((data_state_sel == SelEncDataOutXor) ? enc_data_out_xor : data_i))
                 -----------------1----------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       208
 SUB-EXPRESSION (data_state_sel == SelDigestState)
                -----------------1----------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       208
 SUB-EXPRESSION ((data_state_sel == SelEncDataOutXor) ? enc_data_out_xor : data_i)
                 ------------------1-----------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       208
 SUB-EXPRESSION (data_state_sel == SelEncDataOutXor)
                ------------------1-----------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       214
 EXPRESSION 
 Number  Term
      1  (key_state_sel == SelDecKeyOut) ? dec_key_out : ((key_state_sel == SelEncKeyOut) ? enc_key_out : ((key_state_sel == SelDecKeyInit) ? otp_dec_key_mux : ((key_state_sel == SelEncKeyInit) ? otp_enc_key_mux : ((key_state_sel == SelDigestConst) ? otp_digest_const_mux : ((key_state_sel == SelDigestChained) ? ({data_state_q, data_shadow_q}) : ({data_i, data_shadow_q})))))))

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       214
 SUB-EXPRESSION (key_state_sel == SelDecKeyOut)
                ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       214
 SUB-EXPRESSION 
 Number  Term
      1  (key_state_sel == SelEncKeyOut) ? enc_key_out : ((key_state_sel == SelDecKeyInit) ? otp_dec_key_mux : ((key_state_sel == SelEncKeyInit) ? otp_enc_key_mux : ((key_state_sel == SelDigestConst) ? otp_digest_const_mux : ((key_state_sel == SelDigestChained) ? ({data_state_q, data_shadow_q}) : ({data_i, data_shadow_q}))))))

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       214
 SUB-EXPRESSION (key_state_sel == SelEncKeyOut)
                ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       214
 SUB-EXPRESSION 
 Number  Term
      1  (key_state_sel == SelDecKeyInit) ? otp_dec_key_mux : ((key_state_sel == SelEncKeyInit) ? otp_enc_key_mux : ((key_state_sel == SelDigestConst) ? otp_digest_const_mux : ((key_state_sel == SelDigestChained) ? ({data_state_q, data_shadow_q}) : ({data_i, data_shadow_q})))))

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       214
 SUB-EXPRESSION (key_state_sel == SelDecKeyInit)
                ----------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       214
 SUB-EXPRESSION 
 Number  Term
      1  (key_state_sel == SelEncKeyInit) ? otp_enc_key_mux : ((key_state_sel == SelDigestConst) ? otp_digest_const_mux : ((key_state_sel == SelDigestChained) ? ({data_state_q, data_shadow_q}) : ({data_i, data_shadow_q}))))

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       214
 SUB-EXPRESSION (key_state_sel == SelEncKeyInit)
                ----------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       214
 SUB-EXPRESSION 
 Number  Term
      1  (key_state_sel == SelDigestConst) ? otp_digest_const_mux : ((key_state_sel == SelDigestChained) ? ({data_state_q, data_shadow_q}) : ({data_i, data_shadow_q})))

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       214
 SUB-EXPRESSION (key_state_sel == SelDigestConst)
                ----------------1----------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       214
 SUB-EXPRESSION ((key_state_sel == SelDigestChained) ? ({data_state_q, data_shadow_q}) : ({data_i, data_shadow_q}))
                 -----------------1-----------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       214
 SUB-EXPRESSION (key_state_sel == SelDigestChained)
                -----------------1-----------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       223
 EXPRESSION 
 Number  Term
      1  (key_state_sel == SelDecKeyOut) ? dec_idx_out : ((key_state_sel == SelEncKeyOut) ? enc_idx_out : ((key_state_sel == SelDecKeyInit) ? ((unsigned'(5'(otp_ctrl_pkg::NumPresentRounds)))) : 5'b1)))

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       223
 SUB-EXPRESSION (key_state_sel == SelDecKeyOut)
                ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       223
 SUB-EXPRESSION ((key_state_sel == SelEncKeyOut) ? enc_idx_out : ((key_state_sel == SelDecKeyInit) ? ((unsigned'(5'(otp_ctrl_pkg::NumPresentRounds)))) : 5'b1))
                 ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       223
 SUB-EXPRESSION (key_state_sel == SelEncKeyOut)
                ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       223
 SUB-EXPRESSION ((key_state_sel == SelDecKeyInit) ? ((unsigned'(5'(otp_ctrl_pkg::NumPresentRounds)))) : 5'b1)
                 ----------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       223
 SUB-EXPRESSION (key_state_sel == SelDecKeyInit)
                ----------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       230
 EXPRESSION (digest_init ? otp_digest_iv_mux : enc_data_out_xor)
             -----1-----

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       233
 EXPRESSION (valid_q ? data_state_q : 0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       339
 EXPRESSION (digest_mode_q == ChainedMode)
            ---------------1--------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       348
 EXPRESSION ((digest_mode_q == ChainedMode) ? SelDigestChained : SelDigestInput)
             ---------------1--------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       348
 SUB-EXPRESSION (digest_mode_q == ChainedMode)
                ---------------1--------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       377
 EXPRESSION (cnt == LastPresentRound)
            ------------1------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       390
 EXPRESSION (cnt == LastPresentRound)
            ------------1------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       404
 EXPRESSION (cnt == LastPresentRound)
            ------------1------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

---

FSM Coverage for Module : otp_ctrl_scrmbl

Summary for FSM :: state_q

	Total	Covered	Percent
States	5	5	100.00	(Not included in score)
Transitions	10	10	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DecryptSt	327	Covered	T13
DigestSt	346	Covered	T13
EncryptSt	333	Covered	T13
ErrorSt	433	Covered	T13
IdleSt	378	Covered	T13

transitions	Line No.	Covered	Tests
DecryptSt->ErrorSt	433	Covered	T13
DecryptSt->IdleSt	378	Covered	T13
DigestSt->ErrorSt	433	Covered	T13
DigestSt->IdleSt	405	Covered	T13
EncryptSt->ErrorSt	433	Covered	T13
EncryptSt->IdleSt	391	Covered	T13
IdleSt->DecryptSt	327	Covered	T13
IdleSt->DigestSt	346	Covered	T13
IdleSt->EncryptSt	333	Covered	T13
IdleSt->ErrorSt	433	Covered	T13

---

Branch Coverage for Module : otp_ctrl_scrmbl

	Line No.	Total	Covered	Percent
Branches		52	51	98.08
TERNARY	208	5	5	100.00
TERNARY	214	7	7	100.00
TERNARY	223	4	4	100.00
TERNARY	230	2	2	100.00
TERNARY	233	2	2	100.00
CASE	316	18	17	94.44
IF	432	2	2	100.00
IF	474	2	2	100.00
IF	477	10	10	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_otp_ctrl_1.0/rtl/otp_ctrl_scrmbl.sv' or '../src/lowrisc_ip_otp_ctrl_1.0/rtl/otp_ctrl_scrmbl.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	208	((data_state_sel == SelEncDataOut)) ? 
-2-:	208	((data_state_sel == SelDecDataOut)) ? 
-3-:	208	((data_state_sel == SelDigestState)) ? 
-4-:	208	((data_state_sel == SelEncDataOutXor)) ? 

Branches:

-1-	-2-	-3-	-4-	Status	Tests
1	-	-	-	Covered	T1,T2,T3
0	1	-	-	Covered	T1,T2,T3
0	0	1	-	Covered	T1,T2,T3
0	0	0	1	Covered	T1,T2,T3
0	0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	214	((key_state_sel == SelDecKeyOut)) ? 
-2-:	214	((key_state_sel == SelEncKeyOut)) ? 
-3-:	214	((key_state_sel == SelDecKeyInit)) ? 
-4-:	214	((key_state_sel == SelEncKeyInit)) ? 
-5-:	214	((key_state_sel == SelDigestConst)) ? 
-6-:	214	((key_state_sel == SelDigestChained)) ? 

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	Status	Tests
1	-	-	-	-	-	Covered	T1,T2,T3
0	1	-	-	-	-	Covered	T1,T2,T3
0	0	1	-	-	-	Covered	T1,T2,T3
0	0	0	1	-	-	Covered	T1,T2,T3
0	0	0	0	1	-	Covered	T1,T2,T3
0	0	0	0	0	1	Covered	T1,T2,T3
0	0	0	0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	223	((key_state_sel == SelDecKeyOut)) ? 
-2-:	223	((key_state_sel == SelEncKeyOut)) ? 
-3-:	223	((key_state_sel == SelDecKeyInit)) ? 

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T3
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	230	(digest_init) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	233	(valid_q) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	316	case (state_q)
-2-:	324	if (valid_i)
-3-:	325	case (cmd_i)
-4-:	339	if ((digest_mode_q == ChainedMode))
-5-:	348	((digest_mode_q == ChainedMode)) ? 
-6-:	377	if ((cnt == LastPresentRound))
-7-:	390	if ((cnt == LastPresentRound))
-8-:	404	if ((cnt == LastPresentRound))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests
IdleSt	1	Decrypt	-	-	-	-	-	Covered	T1,T2,T3
IdleSt	1	Encrypt	-	-	-	-	-	Covered	T1,T2,T3
IdleSt	1	LoadShadow	1	-	-	-	-	Covered	T1,T2,T3
IdleSt	1	LoadShadow	0	-	-	-	-	Covered	T1,T2,T3
IdleSt	1	Digest	-	1	-	-	-	Covered	T1,T2,T3
IdleSt	1	Digest	-	0	-	-	-	Covered	T1,T2,T3
IdleSt	1	DigestInit	-	-	-	-	-	Covered	T1,T2,T3
IdleSt	1	DigestFinalize	-	-	-	-	-	Covered	T1,T2,T3
IdleSt	1	default	-	-	-	-	-	Not Covered
IdleSt	0	-	-	-	-	-	-	Covered	T1,T2,T3
DecryptSt	-	-	-	-	1	-	-	Covered	T1,T2,T3
DecryptSt	-	-	-	-	0	-	-	Covered	T1,T2,T3
EncryptSt	-	-	-	-	-	1	-	Covered	T1,T2,T3
EncryptSt	-	-	-	-	-	0	-	Covered	T1,T2,T3
DigestSt	-	-	-	-	-	-	1	Covered	T1,T2,T3
DigestSt	-	-	-	-	-	-	0	Covered	T1,T2,T3
ErrorSt	-	-	-	-	-	-	-	Covered	T1,T8,T11
default	-	-	-	-	-	-	-	Covered	T16,T17,T18

	LineNo.	Expression
-1-:	432	if ((lc_ctrl_pkg::lc_tx_test_true_loose(escalate_en_i) || cnt_err))

Branches:

-1-	Status	Tests
1	Covered	T1,T8,T11
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	474	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	477	if ((!rst_ni))
-2-:	490	if (key_state_en)
-3-:	494	if (data_state_en)
-4-:	497	if (data_shadow_copy)
-5-:	499	if (data_shadow_load)
-6-:	502	if (digest_state_en)

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	Status	Tests
1	-	-	-	-	-	Covered	T1,T2,T3
0	1	-	-	-	-	Covered	T1,T2,T3
0	0	-	-	-	-	Covered	T1,T2,T3
0	-	1	-	-	-	Covered	T1,T2,T3
0	-	0	-	-	-	Covered	T1,T2,T3
0	-	-	1	-	-	Covered	T1,T2,T3
0	-	-	0	1	-	Covered	T1,T2,T3
0	-	-	0	0	-	Covered	T1,T2,T3
0	-	-	-	-	1	Covered	T1,T2,T3
0	-	-	-	-	0	Covered	T1,T2,T3

---

Assert Coverage for Module : otp_ctrl_scrmbl

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	9	9	100.00	9	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	9	9	100.00	9	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckNumDecKeys_A	2098301949	248015	0	0
CheckNumDigest1_A	2098301949	109915	0	0
CheckNumEncKeys_A	2098301949	262933	0	0
DecKeyLutKnown_A	2098301949	2097475901	0	0
DigestConstLutKnown_A	2098301949	2097475901	0	0
DigestIvLutKnown_A	2098301949	2097475901	0	0
EncKeyLutKnown_A	2098301949	2097475901	0	0
NumMaxPresentRounds_A	1160	1160	0	0
u_state_regs_A	2098301949	2097475901	0	0

CheckNumDecKeys_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2098301949	248015	0	0
T1	219091	392	0	0
T2	13075	48	0	0
T3	5043	24	0	0
T4	504764	339	0	0
T5	19562	122	0	0
T6	27806	149	0	0
T7	13630	52	0	0
T8	10804	70	0	0
T9	15640	58	0	0
T10	10210	62	0	0

CheckNumDigest1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2098301949	109915	0	0
T1	219091	221	0	0
T2	13075	4	0	0
T3	5043	4	0	0
T4	504764	604	0	0
T5	19562	46	0	0
T6	27806	62	0	0
T7	13630	20	0	0
T8	10804	14	0	0
T9	15640	9	0	0
T10	10210	5	0	0

CheckNumEncKeys_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2098301949	262933	0	0
T1	219091	374	0	0
T2	13075	33	0	0
T3	5043	24	0	0
T4	504764	690	0	0
T5	19562	101	0	0
T6	27806	146	0	0
T7	13630	53	0	0
T8	10804	76	0	0
T9	15640	43	0	0
T10	10210	39	0	0

DecKeyLutKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2098301949	2097475901	0	0
T1	219091	219090	0	0
T2	13075	12830	0	0
T3	5043	4984	0	0
T4	504764	504762	0	0
T5	19562	19038	0	0
T6	27806	27322	0	0
T7	13630	13522	0	0
T8	10804	10490	0	0
T9	15640	15362	0	0
T10	10210	9938	0	0

DigestConstLutKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2098301949	2097475901	0	0
T1	219091	219090	0	0
T2	13075	12830	0	0
T3	5043	4984	0	0
T4	504764	504762	0	0
T5	19562	19038	0	0
T6	27806	27322	0	0
T7	13630	13522	0	0
T8	10804	10490	0	0
T9	15640	15362	0	0
T10	10210	9938	0	0

DigestIvLutKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2098301949	2097475901	0	0
T1	219091	219090	0	0
T2	13075	12830	0	0
T3	5043	4984	0	0
T4	504764	504762	0	0
T5	19562	19038	0	0
T6	27806	27322	0	0
T7	13630	13522	0	0
T8	10804	10490	0	0
T9	15640	15362	0	0
T10	10210	9938	0	0

EncKeyLutKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2098301949	2097475901	0	0
T1	219091	219090	0	0
T2	13075	12830	0	0
T3	5043	4984	0	0
T4	504764	504762	0	0
T5	19562	19038	0	0
T6	27806	27322	0	0
T7	13630	13522	0	0
T8	10804	10490	0	0
T9	15640	15362	0	0
T10	10210	9938	0	0

NumMaxPresentRounds_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1160	1160	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

u_state_regs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2098301949	2097475901	0	0
T1	219091	219090	0	0
T2	13075	12830	0	0
T3	5043	4984	0	0
T4	504764	504762	0	0
T5	19562	19038	0	0
T6	27806	27322	0	0
T7	13630	13522	0	0
T8	10804	10490	0	0
T9	15640	15362	0	0
T10	10210	9938	0	0