Unified Coverage Report :: Module :: otp_ctrl_core_csr_assert_fpv

Module : otp_ctrl_core_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_otp_ctrl_csr_assert_0/otp_ctrl_core_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.otp_ctrl_core_csr_assert	100.00						100.00

---

Module Instance : tb.dut.otp_ctrl_core_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
95.99	97.89	88.57	96.52		96.97	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : otp_ctrl_core_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	13	13	100.00	13	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	13	13	100.00	13	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	2147483647	22514322	0	0
check_regwen_rd_A	2147483647	4338	0	0
check_timeout_rd_A	2147483647	4221	0	0
check_trigger_regwen_rd_A	2147483647	4633	0	0
consistency_check_period_rd_A	2147483647	5031	0	0
creator_sw_cfg_read_lock_rd_A	2147483647	4518	0	0
direct_access_address_rd_A	2147483647	4291	0	0
direct_access_wdata_0_rd_A	2147483647	3278	0	0
direct_access_wdata_1_rd_A	2147483647	3829	0	0
integrity_check_period_rd_A	2147483647	4326	0	0
intr_enable_rd_A	2147483647	5720	0	0
owner_sw_cfg_read_lock_rd_A	2147483647	4218	0	0
vendor_test_read_lock_rd_A	2147483647	4191	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	22514322	0	0
T110	6803	94	0	0
T111	3691	0	0	0
T112	3722	0	0	0
T113	4025	0	0	0
T114	4145	0	0	0
T115	59527	5	0	0
T181	3152	0	0	0
T182	3704	0	0	0
T183	5844	0	0	0
T185	0	107	0	0
T186	0	53	0	0
T187	0	176	0	0
T188	0	200	0	0
T193	3516	0	0	0
T211	0	3	0	0
T217	0	6	0	0
T241	0	2	0	0
T245	0	3	0	0

check_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	4338	0	0
T115	59527	27	0	0
T184	5729	6	0	0
T185	9067	0	0	0
T186	0	9	0	0
T189	0	9	0	0
T193	3516	0	0	0
T210	11770	0	0	0
T247	5529	11	0	0
T248	4329	0	0	0
T249	4624	0	0	0
T254	0	2	0	0
T258	0	77	0	0
T280	0	2	0	0
T281	0	2	0	0
T282	0	41	0	0
T283	3311	0	0	0
T284	3531	0	0	0

check_timeout_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	4221	0	0
T7	0	62	0	0
T116	6069	0	0	0
T184	5729	1	0	0
T185	9067	0	0	0
T186	6903	1	0	0
T187	9327	0	0	0
T189	0	6	0	0
T247	5529	13	0	0
T248	4329	0	0	0
T249	4624	0	0	0
T258	0	63	0	0
T280	0	9	0	0
T281	0	9	0	0
T284	3531	0	0	0
T285	0	3	0	0
T286	0	7	0	0
T287	3095	0	0	0

check_trigger_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	4633	0	0
T115	59527	30	0	0
T184	5729	5	0	0
T185	9067	0	0	0
T186	0	1	0	0
T189	0	10	0	0
T193	3516	0	0	0
T210	11770	0	0	0
T247	5529	31	0	0
T248	4329	0	0	0
T249	4624	0	0	0
T254	0	8	0	0
T257	0	1	0	0
T258	0	61	0	0
T280	0	29	0	0
T281	0	7	0	0
T283	3311	0	0	0
T284	3531	0	0	0

consistency_check_period_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	5031	0	0
T115	59527	14	0	0
T184	5729	0	0	0
T185	9067	0	0	0
T186	0	5	0	0
T189	0	5	0	0
T193	3516	0	0	0
T210	11770	0	0	0
T247	5529	32	0	0
T248	4329	0	0	0
T249	4624	0	0	0
T254	0	1	0	0
T257	0	7	0	0
T258	0	85	0	0
T280	0	16	0	0
T282	0	46	0	0
T283	3311	0	0	0
T284	3531	0	0	0
T288	0	75	0	0

creator_sw_cfg_read_lock_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	4518	0	0
T7	0	82	0	0
T15	0	238	0	0
T116	6069	0	0	0
T184	5729	7	0	0
T185	9067	0	0	0
T186	6903	5	0	0
T187	9327	0	0	0
T247	5529	6	0	0
T248	4329	0	0	0
T249	4624	0	0	0
T258	0	81	0	0
T280	0	34	0	0
T284	3531	0	0	0
T285	0	5	0	0
T286	0	12	0	0
T287	3095	0	0	0
T289	0	7	0	0

direct_access_address_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	4291	0	0
T7	0	58	0	0
T15	0	242	0	0
T184	5729	9	0	0
T185	9067	0	0	0
T194	0	107	0	0
T247	5529	0	0	0
T248	4329	0	0	0
T249	4624	0	0	0
T251	13216	0	0	0
T269	0	92	0	0
T281	6211	5	0	0
T284	3531	0	0	0
T285	0	4	0	0
T286	0	5	0	0
T289	0	12	0	0
T290	0	17	0	0
T291	3110	0	0	0
T292	3984	0	0	0

direct_access_wdata_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	3278	0	0
T7	111091	37	0	0
T8	8171	0	0	0
T9	19415	0	0	0
T10	10832	0	0	0
T11	12755	0	0	0
T15	0	187	0	0
T37	12955	0	0	0
T48	11194	0	0	0
T93	43989	0	0	0
T106	9868	0	0	0
T107	14899	0	0	0
T194	0	131	0	0
T216	0	344	0	0
T269	0	51	0	0
T290	0	30	0	0
T293	0	51	0	0
T294	0	93	0	0
T295	0	63	0	0
T296	0	302	0	0

direct_access_wdata_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	3829	0	0
T7	111091	83	0	0
T8	8171	0	0	0
T9	19415	0	0	0
T10	10832	0	0	0
T11	12755	0	0	0
T15	0	238	0	0
T37	12955	0	0	0
T48	11194	0	0	0
T93	43989	0	0	0
T106	9868	0	0	0
T107	14899	0	0	0
T194	0	140	0	0
T216	0	272	0	0
T269	0	71	0	0
T290	0	50	0	0
T293	0	77	0	0
T294	0	137	0	0
T295	0	56	0	0
T296	0	295	0	0

integrity_check_period_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	4326	0	0
T115	59527	14	0	0
T184	5729	1	0	0
T185	9067	0	0	0
T186	0	1	0	0
T189	0	11	0	0
T193	3516	0	0	0
T210	11770	0	0	0
T247	5529	2	0	0
T248	4329	0	0	0
T249	4624	0	0	0
T257	0	2	0	0
T258	0	83	0	0
T280	0	45	0	0
T281	0	6	0	0
T282	0	35	0	0
T283	3311	0	0	0
T284	3531	0	0	0

intr_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	5720	0	0
T111	3691	9	0	0
T112	3722	20	0	0
T113	4025	20	0	0
T115	59527	47	0	0
T181	3152	0	0	0
T182	3704	0	0	0
T183	5844	0	0	0
T184	0	3	0	0
T186	0	2	0	0
T193	3516	0	0	0
T210	11770	0	0	0
T247	0	5	0	0
T254	0	5	0	0
T283	3311	0	0	0
T284	0	6	0	0
T297	0	13	0	0

owner_sw_cfg_read_lock_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	4218	0	0
T7	0	43	0	0
T15	0	201	0	0
T116	6069	0	0	0
T184	5729	2	0	0
T185	9067	0	0	0
T186	6903	6	0	0
T187	9327	0	0	0
T189	0	4	0	0
T247	5529	14	0	0
T248	4329	0	0	0
T249	4624	0	0	0
T258	0	106	0	0
T280	0	49	0	0
T284	3531	0	0	0
T286	0	12	0	0
T287	3095	0	0	0
T289	0	6	0	0

vendor_test_read_lock_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	4191	0	0
T7	0	52	0	0
T15	0	214	0	0
T184	5729	6	0	0
T185	9067	0	0	0
T189	9929	2	0	0
T190	5241	0	0	0
T194	0	150	0	0
T247	5529	24	0	0
T248	4329	0	0	0
T249	4624	0	0	0
T258	7874	42	0	0
T275	3490	0	0	0
T280	0	31	0	0
T284	3531	0	0	0
T286	0	15	0	0
T289	0	1	0	0