Unified Coverage Report :: Module :: otp_ctrl

Module : otp_ctrl

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
95.82	97.89	88.57	95.67		96.97	100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_ip_otp_ctrl_1.0/rtl/otp_ctrl.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut	95.99	97.89	88.57	96.52		96.97	100.00

---

Module Instance : tb.dut

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
95.99	97.89	88.57	96.52		96.97	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.12	92.63	91.48	92.48	92.11	93.49	96.53

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							tb

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
core_tlul_assert_device	100.00	100.00				100.00	100.00
gen_alert_tx[0].u_prim_alert_sender	100.00			100.00
gen_alert_tx[1].u_prim_alert_sender	100.00			100.00
gen_alert_tx[2].u_prim_alert_sender	100.00			100.00
gen_alert_tx[3].u_prim_alert_sender	100.00			100.00
gen_alert_tx[4].u_prim_alert_sender	77.78			77.78
gen_bufs[0].u_prim_mubi8_sender_read_lock	100.00	100.00				100.00	100.00
gen_bufs[0].u_prim_mubi8_sender_write_lock	79.17	37.50				100.00	100.00
gen_bufs[1].u_prim_mubi8_sender_read_lock	100.00	100.00				100.00	100.00
gen_bufs[1].u_prim_mubi8_sender_write_lock	79.17	37.50				100.00	100.00
gen_bufs[2].u_prim_mubi8_sender_read_lock	100.00	100.00				100.00	100.00
gen_bufs[2].u_prim_mubi8_sender_write_lock	79.17	37.50				100.00	100.00
gen_bufs[3].u_prim_mubi8_sender_read_lock	79.17	37.50				100.00	100.00
gen_bufs[3].u_prim_mubi8_sender_write_lock	79.17	37.50				100.00	100.00
gen_bufs[4].u_prim_mubi8_sender_read_lock	79.17	37.50				100.00	100.00
gen_bufs[4].u_prim_mubi8_sender_write_lock	79.17	37.50				100.00	100.00
gen_bufs[5].u_prim_mubi8_sender_read_lock	79.17	37.50				100.00	100.00
gen_bufs[5].u_prim_mubi8_sender_write_lock	79.17	37.50				100.00	100.00
gen_bufs[6].u_prim_mubi8_sender_read_lock	100.00	100.00				100.00	100.00
gen_bufs[6].u_prim_mubi8_sender_write_lock	100.00	100.00				100.00	100.00
gen_bufs[7].u_prim_mubi8_sender_read_lock	79.17	37.50				100.00	100.00
gen_bufs[7].u_prim_mubi8_sender_write_lock	79.17	37.50				100.00	100.00
gen_partitions[0].gen_unbuffered.u_part_unbuf	94.53	98.44	95.74	97.87	83.33	94.64	97.14
gen_partitions[1].gen_unbuffered.u_part_unbuf	98.26	100.00	100.00	97.87	91.67	100.00	100.00
gen_partitions[2].gen_unbuffered.u_part_unbuf	98.26	100.00	100.00	97.87	91.67	100.00	100.00
gen_partitions[3].gen_buffered.u_part_buf	88.27	86.27	88.68	93.78	93.10	81.71	86.05
gen_partitions[4].gen_buffered.u_part_buf	92.46	93.87	86.44	94.30	97.22	87.36	95.56
gen_partitions[5].gen_buffered.u_part_buf	91.44	93.87	86.44	93.73	91.67	87.36	95.56
gen_partitions[6].gen_buffered.u_part_buf	91.44	93.87	86.44	93.73	91.67	87.36	95.56
gen_partitions[7].gen_lifecycle.u_part_buf	80.10	71.86	77.42	74.13	95.24	76.56	85.37
otp_ctrl_core_csr_assert	100.00						100.00
prim_tlul_assert_device	100.00	100.00				100.00	100.00
u_edn_arb	92.49	92.31	84.31			100.00	93.33
u_edn_req	92.19	100.00	93.75			100.00	75.00
u_intr_error	100.00	100.00	100.00			100.00	100.00
u_intr_operation_done	100.00	100.00	100.00			100.00	100.00
u_keygmr_key_valid	100.00	100.00				100.00
u_otp	96.20	91.72	94.75	100.00	100.00	90.71	100.00
u_otp_arb	94.18	93.01	89.98			100.00	93.75
u_otp_ctrl_dai	91.38	90.73	93.06	100.00	87.72	90.43	86.36
u_otp_ctrl_kdi	96.34	98.43	96.90	100.00	90.91	94.44	97.37
u_otp_ctrl_lci	100.00	100.00	100.00	100.00	100.00	100.00	100.00
u_otp_ctrl_lfsr_timer	96.89	100.00	96.25	85.10	100.00	100.00	100.00
u_otp_ctrl_scrmbl	96.62	81.50	100.00	100.00	100.00	98.21	100.00
u_otp_init_sync	100.00	100.00				100.00
u_otp_rsp_fifo	94.70	100.00	78.79			100.00	100.00
u_part_sel_idx	82.27	76.81	98.44			100.00	53.85
u_prim_lc_sender_rma_token_valid	100.00	100.00				100.00
u_prim_lc_sender_secrets_valid	100.00	100.00				100.00
u_prim_lc_sender_test_tokens_valid	100.00	100.00				100.00
u_prim_lc_sync_check_byp_en	100.00	100.00				100.00	100.00
u_prim_lc_sync_creator_seed_sw_rw_en	100.00	100.00				100.00	100.00
u_prim_lc_sync_dft_en	100.00	100.00				100.00	100.00
u_prim_lc_sync_escalate_en	100.00	100.00				100.00	100.00
u_prim_lc_sync_seed_hw_rd_en	100.00	100.00				100.00	100.00
u_reg_core	99.28	99.59	96.83	100.00		100.00	100.00
u_scrmbl_mtx	76.66	83.33	79.54			100.00	43.75
u_tlul_adapter_sram	91.72	89.54	84.55			92.77	100.00
u_tlul_lc_gate	93.35	99.24	100.00		85.71	94.29	87.50

Line Coverage for Module : otp_ctrl

	Line No.	Total	Covered	Percent
TOTAL		142	139	97.89
CONT_ASSIGN	234	1	1	100.00
CONT_ASSIGN	234	1	1	100.00
CONT_ASSIGN	234	1	1	100.00
CONT_ASSIGN	234	1	1	100.00
CONT_ASSIGN	234	1	1	100.00
CONT_ASSIGN	234	1	1	100.00
CONT_ASSIGN	234	1	1	100.00
CONT_ASSIGN	234	1	1	100.00
ALWAYS	264	14	13	92.86
ALWAYS	288	3	3	100.00
CONT_ASSIGN	301	1	1	100.00
CONT_ASSIGN	302	1	1	100.00
CONT_ASSIGN	303	1	1	100.00
CONT_ASSIGN	304	1	1	100.00
CONT_ASSIGN	305	1	1	100.00
CONT_ASSIGN	306	1	1	100.00
CONT_ASSIGN	307	1	1	100.00
CONT_ASSIGN	309	1	1	100.00
ALWAYS	319	11	11	100.00
CONT_ASSIGN	374	1	1	100.00
CONT_ASSIGN	378	1	1	100.00
CONT_ASSIGN	382	1	1	100.00
CONT_ASSIGN	383	1	1	100.00
CONT_ASSIGN	384	1	1	100.00
CONT_ASSIGN	386	1	1	100.00
CONT_ASSIGN	394	1	1	100.00
CONT_ASSIGN	395	1	1	100.00
ALWAYS	398	3	3	100.00
ALWAYS	420	20	20	100.00
CONT_ASSIGN	474	1	1	100.00
CONT_ASSIGN	487	1	1	100.00
CONT_ASSIGN	495	1	1	100.00
ALWAYS	498	9	9	100.00
CONT_ASSIGN	549	1	1	100.00
CONT_ASSIGN	557	1	1	100.00
CONT_ASSIGN	604	1	1	100.00
CONT_ASSIGN	606	1	1	100.00
CONT_ASSIGN	729	1	1	100.00
CONT_ASSIGN	730	1	1	100.00
CONT_ASSIGN	731	1	1	100.00
CONT_ASSIGN	761	1	1	100.00
CONT_ASSIGN	763	1	1	100.00
ALWAYS	840	2	2	100.00
ALWAYS	898	2	2	100.00
ALWAYS	925	4	4	100.00
CONT_ASSIGN	952	1	1	100.00
ALWAYS	955	3	3	100.00
CONT_ASSIGN	1007	1	1	100.00
CONT_ASSIGN	1009	1	1	100.00
CONT_ASSIGN	1043	1	1	100.00
CONT_ASSIGN	1094	1	0	0.00
CONT_ASSIGN	1149	1	1	100.00
CONT_ASSIGN	1149	1	1	100.00
CONT_ASSIGN	1149	1	1	100.00
CONT_ASSIGN	1204	1	1	100.00
CONT_ASSIGN	1204	1	1	100.00
CONT_ASSIGN	1204	1	0	0.00
CONT_ASSIGN	1204	1	1	100.00
CONT_ASSIGN	1264	1	1	100.00
CONT_ASSIGN	1276	1	1	100.00
CONT_ASSIGN	1299	1	1	100.00
CONT_ASSIGN	1300	1	1	100.00
CONT_ASSIGN	1303	1	1	100.00
CONT_ASSIGN	1304	1	1	100.00
CONT_ASSIGN	1305	1	1	100.00
CONT_ASSIGN	1310	1	1	100.00
CONT_ASSIGN	1333	1	1	100.00
CONT_ASSIGN	1334	1	1	100.00
CONT_ASSIGN	1336	1	1	100.00
CONT_ASSIGN	1338	1	1	100.00
CONT_ASSIGN	1342	1	1	100.00
CONT_ASSIGN	1344	1	1	100.00
CONT_ASSIGN	1346	1	1	100.00
CONT_ASSIGN	1351	1	1	100.00
CONT_ASSIGN	1353	1	1	100.00
CONT_ASSIGN	1355	1	1	100.00
CONT_ASSIGN	1387	1	1	100.00
CONT_ASSIGN	1389	1	1	100.00
CONT_ASSIGN	1393	1	1	100.00
CONT_ASSIGN	1397	1	1	100.00
CONT_ASSIGN	1401	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_otp_ctrl_1.0/rtl/otp_ctrl.sv' or '../src/lowrisc_ip_otp_ctrl_1.0/rtl/otp_ctrl.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
234	8	8
264	1	1
265	1	1
266	1	1
267	1	1
268	1	1
269	1	1
272	0	1
			MISSING_ELSE
277	1	1
278	1	1
279	1	1
280	1	1
281	1	1
282	1	1
283	1	1
288	1	1
289	1	1
291	1	1
301	1	1
302	1	1
303	1	1
304	1	1
305	1	1
306	1	1
307	1	1
309	1	1
319	1	1
323	1	1
324	1	1
328	1	1
329	1	1
			MISSING_ELSE
331	1	1
332	1	1
			MISSING_ELSE
334	1	1
335	1	1
			MISSING_ELSE
338	1	1
339	1	1
			MISSING_ELSE
374	1	1
378	1	1
382	1	1
383	1	1
384	1	1
386	1	1
394	1	1
395	1	1
398	1	1
399	1	1
401	1	1
420	1	1
423	1	1
424	1	1
425	1	1
427	1	1
429	1	1
432	1	1
434	1	1
437	1	1
438	1	1
			MISSING_ELSE
442	1	1
444	1	1
448	1	1
451	1	1
453	1	1
458	1	1
459	1	1
			MISSING_ELSE
461	1	1
462	1	1
			MISSING_ELSE
467	1	1
474	1	1
487	1	1
495	1	1
498	1	1
499	1	1
500	1	1
501	1	1
502	1	1
504	1	1
505	1	1
506	1	1
507	1	1
549	1	1
557	1	1
604	1	1
606	1	1
729	1	1
730	1	1
731	1	1
761	1	1
763	1	1
840	1	1
841	1	1
898	1	1
899	1	1
925	1	1
926	1	1
927	1	1
928	1	1
952	1	1
955	1	1
956	1	1
958	1	1
1007	1	1
1009	1	1
1043	1	1
1094	0	1
1149	3	3
1204	3	4
1264	1	1
1276	1	1
1299	1	1
1300	1	1
1303	1	1
1304	1	1
1305	1	1
1310	1	1
1333	1	1
1334	1	1
1336	1	1
1338	1	1
1342	1	1
1344	1	1
1346	1	1
1351	1	1
1353	1	1
1355	1	1
1387	1	1
1389	1	1
1393	1	1
1397	1	1
1401	1	1

---

Cond Coverage for Module : otp_ctrl

	Total	Covered	Percent
Conditions	105	93	88.57
Logical	105	93	88.57
Non-Logical	0	0
Event	0	0

 LINE       234
 EXPRESSION (({tlul_addr, 2'b0} >= 11'b0) & ({1'b0, {tlul_addr, 2'b0}} < gen_part_sel[0].PartEnd))
             --------------1-------------   --------------------------2--------------------------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       234
 EXPRESSION (({tlul_addr, 2'b0} >= 11'b00001000000) & ({1'b0, {tlul_addr, 2'b0}} < gen_part_sel[1].PartEnd))
             -------------------1------------------   --------------------------2--------------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T3,T6

 LINE       234
 EXPRESSION (({tlul_addr, 2'b0} >= 11'b01101100000) & ({1'b0, {tlul_addr, 2'b0}} < gen_part_sel[2].PartEnd))
             -------------------1------------------   --------------------------2--------------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T7,T12,T13
1	1	Covered	T1,T2,T3

 LINE       234
 EXPRESSION (({tlul_addr, 2'b0} >= 11'b11010000000) & ({1'b0, {tlul_addr, 2'b0}} < gen_part_sel[3].PartEnd))
             -------------------1------------------   --------------------------2--------------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T7,T12,T13
1	1	Covered	T7,T12,T13

 LINE       234
 EXPRESSION (({tlul_addr, 2'b0} >= 11'b11011010000) & ({1'b0, {tlul_addr, 2'b0}} < gen_part_sel[4].PartEnd))
             -------------------1------------------   --------------------------2--------------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T7,T12,T13
1	1	Covered	T7,T12,T13

 LINE       234
 EXPRESSION (({tlul_addr, 2'b0} >= 11'b11011111000) & ({1'b0, {tlul_addr, 2'b0}} < gen_part_sel[5].PartEnd))
             -------------------1------------------   --------------------------2--------------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T7,T12,T13
1	1	Covered	T7,T12,T13

 LINE       234
 EXPRESSION (({tlul_addr, 2'b0} >= 11'b11101010000) & ({1'b0, {tlul_addr, 2'b0}} < gen_part_sel[6].PartEnd))
             -------------------1------------------   --------------------------2--------------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T7,T12,T13
1	1	Covered	T7,T12,T13

 LINE       234
 EXPRESSION (({tlul_addr, 2'b0} >= 11'b11110101000) & ({1'b0, {tlul_addr, 2'b0}} < gen_part_sel[7].PartEnd))
             -------------------1------------------   --------------------------2--------------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T7,T12,T13

 LINE       268
 EXPRESSION (tlul_part_sel_oh != '0)
            ------------1-----------

-1-	Status	Tests
0	Not Covered
1	Covered	T1,T2,T3

 LINE       277
 EXPRESSION (((|part_tlul_gnt)) | tlul_oob_err_q)
             ---------1--------   -------2------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Not Covered
1	0	Covered	T1,T2,T3

 LINE       278
 EXPRESSION (((|part_tlul_rvalid)) | tlul_oob_err_q)
             ----------1----------   -------2------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Not Covered
1	0	Covered	T1,T2,T3

 LINE       374
 EXPRESSION (reg2hw.direct_access_cmd.digest.qe | reg2hw.direct_access_cmd.wr.qe | reg2hw.direct_access_cmd.rd.qe)
             -----------------1----------------   ---------------2--------------   ---------------3--------------

-1-	-2-	-3-	Status	Tests
0	0	0	Covered	T1,T2,T3
0	0	1	Not Covered
0	1	0	Not Covered
1	0	0	Not Covered

 LINE       394
 EXPRESSION (lci_prog_idle & dai_prog_idle)
             ------1------   ------2------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       425
 EXPRESSION (fatal_bus_integ_error_q | ((|intg_error)))
             -----------1-----------   -------2-------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T20,T21,T22
1	0	Not Covered

 LINE       434
 EXPRESSION (part_error[k] == MacroError)
            --------------1--------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Not Covered

 LINE       438
 EXPRESSION (part_error[k] == MacroEccUncorrError)
            -------------------1------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T37,T48,T58

 LINE       458
 EXPRESSION (fatal_macro_error_q || fatal_check_error_q)
             ---------1---------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T7,T107,T26
1	0	Covered	T9,T37,T48

 LINE       467
 EXPRESSION (chk_timeout | lfsr_fsm_err | scrmbl_fsm_err | ((|part_fsm_err)))
             -----1-----   ------2-----   -------3------   --------4--------

-1-	-2-	-3-	-4-	Status	Tests
0	0	0	0	Covered	T1,T2,T3
0	0	0	1	Covered	T9,T37,T48
0	0	1	0	Covered	T20,T21,T22
0	1	0	0	Covered	T20,T21,T22
1	0	0	0	Covered	T29,T95,T97

 LINE       557
 SUB-EXPRESSION (reg2hw.alert_test.recov_prim_otp_alert.q & reg2hw.alert_test.recov_prim_otp_alert.qe)
                 --------------------1-------------------   --------------------2--------------------

-1-	-2-	Status	Tests
0	1	Covered	T8,T209,T172
1	0	Covered	T1,T2,T3
1	1	Covered	T8,T209,T172

 LINE       557
 SUB-EXPRESSION (reg2hw.alert_test.fatal_prim_otp_alert.q & reg2hw.alert_test.fatal_prim_otp_alert.qe)
                 --------------------1-------------------   --------------------2--------------------

-1-	-2-	Status	Tests
0	1	Covered	T8,T209,T172
1	0	Covered	T1,T2,T3
1	1	Covered	T8,T209,T172

 LINE       557
 SUB-EXPRESSION (reg2hw.alert_test.fatal_bus_integ_error.q & reg2hw.alert_test.fatal_bus_integ_error.qe)
                 --------------------1--------------------   ---------------------2--------------------

-1-	-2-	Status	Tests
0	1	Covered	T8,T209,T172
1	0	Covered	T1,T2,T3
1	1	Covered	T8,T209,T172

 LINE       557
 SUB-EXPRESSION (reg2hw.alert_test.fatal_check_error.q & reg2hw.alert_test.fatal_check_error.qe)
                 ------------------1------------------   -------------------2------------------

-1-	-2-	Status	Tests
0	1	Covered	T8,T209,T172
1	0	Covered	T1,T2,T3
1	1	Covered	T8,T209,T172

 LINE       557
 SUB-EXPRESSION (reg2hw.alert_test.fatal_macro_error.q & reg2hw.alert_test.fatal_macro_error.qe)
                 ------------------1------------------   -------------------2------------------

-1-	-2-	Status	Tests
0	1	Covered	T8,T209,T172
1	0	Covered	T1,T2,T3
1	1	Covered	T8,T209,T172

 LINE       604
 EXPRESSION (reg2hw.check_trigger.integrity.q & reg2hw.check_trigger.integrity.qe)
             ----------------1---------------   ----------------2----------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       606
 EXPRESSION (reg2hw.check_trigger.consistency.q & reg2hw.check_trigger.consistency.qe)
             -----------------1----------------   -----------------2-----------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       729
 EXPRESSION (otp_prim_ready & otp_rsp_fifo_ready)
             -------1------   ---------2--------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       730
 EXPRESSION (otp_arb_valid & otp_rsp_fifo_ready)
             ------1------   ---------2--------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T3

 LINE       731
 EXPRESSION (otp_prim_ready & otp_prim_valid)
             -------1------   -------2------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       841
 EXPRESSION (otp_rvalid & otp_fifo_valid)
             -----1----   -------2------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T3

 LINE       1299
 EXPRESSION (part_init_done[HwCfgIdx] ? On : Off)
             ------------1-----------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       1303
 EXPRESSION (part_digest[Secret2Idx] != '0)
            ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T3,T6

 LINE       1333
 EXPRESSION (part_digest[Secret1Idx] != '0)
            ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       1351
 EXPRESSION ((part_digest[Secret0Idx] != '0) ? On : Off)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       1351
 SUB-EXPRESSION (part_digest[Secret0Idx] != '0)
                ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       1353
 EXPRESSION ((part_digest[Secret2Idx] != '0) ? On : Off)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T3,T6

 LINE       1353
 SUB-EXPRESSION (part_digest[Secret2Idx] != '0)
                ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T3,T6

 LINE       1355
 EXPRESSION ((part_digest[Secret2Idx] != '0) ? On : Off)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T3,T6

 LINE       1355
 SUB-EXPRESSION (part_digest[Secret2Idx] != '0)
                ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T3,T6

---

Toggle Coverage for Module : otp_ctrl

	Total	Covered	Percent
Totals	145	135	93.10
Total Bits	9412	9004	95.67
Total Bits 0->1	4706	4502	95.67
Total Bits 1->0	4706	4502	95.67

Ports	145	135	93.10
Port Bits	9412	9004	95.67
Port Bits 0->1	4706	4502	95.67
Port Bits 1->0	4706	4502	95.67

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
clk_i	Yes	Yes	T16,T109,T110	Yes	T16,T109,T110	INPUT
rst_ni	Yes	Yes	T110,T115,T184	Yes	T16,T109,T110	INPUT
clk_edn_i	Yes	Yes	T16,T109,T110	Yes	T16,T109,T110	INPUT
rst_edn_ni	Yes	Yes	T110,T115,T184	Yes	T16,T109,T110	INPUT
edn_o.edn_req	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
edn_i.edn_bus[31:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
edn_i.edn_fips	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
edn_i.edn_ack	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
core_tl_i.d_ready	Yes	Yes	T109,T110,T114	Yes	T16,T109,T110	INPUT
core_tl_i.a_user.data_intg[6:0]	Yes	Yes	T16,T109,T110	Yes	T16,T109,T110	INPUT
core_tl_i.a_user.cmd_intg[6:0]	Yes	Yes	T16,T109,T110	Yes	T16,T109,T110	INPUT
core_tl_i.a_user.instr_type[3:0]	Yes	Yes	T110,T114,T111	Yes	T110,T114,T111	INPUT
core_tl_i.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		INPUT
core_tl_i.a_data[31:0]	Yes	Yes	T16,T109,T110	Yes	T16,T109,T110	INPUT
core_tl_i.a_mask[3:0]	Yes	Yes	T16,T109,T110	Yes	T110,T114,T111	INPUT
core_tl_i.a_address[31:0]	Yes	Yes	T110,T114,T111	Yes	T110,T114,T111	INPUT
core_tl_i.a_source[7:0]	Yes	Yes	T16,T109,T110	Yes	T16,T109,T110	INPUT
core_tl_i.a_size[1:0]	Yes	Yes	T110,T114,T111	Yes	T110,T114,T111	INPUT
core_tl_i.a_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
core_tl_i.a_opcode[2:0]	Yes	Yes	T16,T109,T110	Yes	T16,T109,T110	INPUT
core_tl_i.a_valid	Yes	Yes	T16,T109,T110	Yes	T16,T109,T110	INPUT
core_tl_o.a_ready	Yes	Yes	T16,T109,T110	Yes	T16,T109,T110	OUTPUT
core_tl_o.d_error	Yes	Yes	T110,T115,T184	Yes	T110,T115,T184	OUTPUT
core_tl_o.d_user.data_intg[6:0]	Yes	Yes	T16,T109,T110	Yes	T16,T109,T110	OUTPUT
core_tl_o.d_user.rsp_intg[5:0]	Yes	Yes	*T16,*T109,T110	Yes	T16,T109,T110	OUTPUT
core_tl_o.d_user.rsp_intg[6]	Unreachable	Unreachable		Unreachable		OUTPUT
core_tl_o.d_data[31:0]	Yes	Yes	T16,T109,T110	Yes	T16,T109,T110	OUTPUT
core_tl_o.d_sink	Unreachable	Unreachable		Unreachable		OUTPUT
core_tl_o.d_source[7:0]	Yes	Yes	T16,T109,T110	Yes	T16,T109,T110	OUTPUT
core_tl_o.d_size[1:0]	Yes	Yes	T110,T114,T111	Yes	T110,T114,T111	OUTPUT
core_tl_o.d_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
core_tl_o.d_opcode[0]	Yes	Yes	*T16,*T109,*T110	Yes	T16,T109,T110	OUTPUT
core_tl_o.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		OUTPUT
core_tl_o.d_valid	Yes	Yes	T16,T109,T110	Yes	T16,T109,T110	OUTPUT
prim_tl_i.d_ready	Yes	Yes	T109,T110,T114	Yes	T16,T109,T110	INPUT
prim_tl_i.a_user.data_intg[6:0]	Yes	Yes	T16,T109,T110	Yes	T16,T109,T110	INPUT
prim_tl_i.a_user.cmd_intg[6:0]	Yes	Yes	T16,T109,T110	Yes	T16,T109,T110	INPUT
prim_tl_i.a_user.instr_type[3:0]	Yes	Yes	T110,T112,T210	Yes	T110,T111,T182	INPUT
prim_tl_i.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		INPUT
prim_tl_i.a_data[31:0]	Yes	Yes	T16,T109,T110	Yes	T16,T109,T110	INPUT
prim_tl_i.a_mask[3:0]	Yes	Yes	T110,T114,T111	Yes	T110,T114,T182	INPUT
prim_tl_i.a_address[31:0]	Yes	Yes	T110,T114,T111	Yes	T110,T114,T115	INPUT
prim_tl_i.a_source[7:0]	Yes	Yes	T16,T109,T110	Yes	T16,T109,T110	INPUT
prim_tl_i.a_size[1:0]	Yes	Yes	T110,T114,T115	Yes	T110,T114,T115	INPUT
prim_tl_i.a_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
prim_tl_i.a_opcode[2:0]	Yes	Yes	T16,T109,T110	Yes	T16,T109,T110	INPUT
prim_tl_i.a_valid	Yes	Yes	T16,T109,T110	Yes	T16,T109,T110	INPUT
prim_tl_o.a_ready	Yes	Yes	T16,T109,T110	Yes	T16,T109,T110	OUTPUT
prim_tl_o.d_error	Yes	Yes	T16,T109,T110	Yes	T110,T115,T184	OUTPUT
prim_tl_o.d_user.data_intg[6:0]	Yes	Yes	T16,T109,T110	Yes	T16,T109,T110	OUTPUT
prim_tl_o.d_user.rsp_intg[5:0]	Yes	Yes	*T16,*T109,T110	Yes	T16,T109,T110	OUTPUT
prim_tl_o.d_user.rsp_intg[6]	Unreachable	Unreachable		Unreachable		OUTPUT
prim_tl_o.d_data[31:0]	Yes	Yes	T16,T109,T110	Yes	T16,T109,T110	OUTPUT
prim_tl_o.d_sink	Unreachable	Unreachable		Unreachable		OUTPUT
prim_tl_o.d_source[7:0]	Yes	Yes	T16,T109,T110	Yes	T16,T109,T110	OUTPUT
prim_tl_o.d_size[1:0]	Yes	Yes	T110,T114,T115	Yes	T110,T114,T115	OUTPUT
prim_tl_o.d_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
prim_tl_o.d_opcode[0]	Yes	Yes	*T16,*T109,*T110	Yes	T16,T109,T110	OUTPUT
prim_tl_o.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		OUTPUT
prim_tl_o.d_valid	Yes	Yes	T16,T109,T110	Yes	T16,T109,T110	OUTPUT
intr_otp_operation_done_o	Yes	Yes	T111,T112,T113	Yes	T111,T112,T113	OUTPUT
intr_otp_error_o	Yes	Yes	T111,T112,T113	Yes	T111,T112,T113	OUTPUT
alert_rx_i[0].ack_n	Yes	Yes	T16,T109,T110	Yes	T16,T109,T110	INPUT
alert_rx_i[0].ack_p	Yes	Yes	T16,T109,T110	Yes	T16,T109,T110	INPUT
alert_rx_i[0].ping_n	Unreachable	Unreachable		Unreachable		INPUT
alert_rx_i[0].ping_p	Unreachable	Unreachable		Unreachable		INPUT
alert_rx_i[1].ack_n	Yes	Yes	T16,T109,T110	Yes	T16,T109,T110	INPUT
alert_rx_i[1].ack_p	Yes	Yes	T16,T109,T183	Yes	T16,T109,T183	INPUT
alert_rx_i[1].ping_n	Unreachable	Unreachable		Unreachable		INPUT
alert_rx_i[1].ping_p	Unreachable	Unreachable		Unreachable		INPUT
alert_rx_i[2].ack_n	Yes	Yes	T16,T109,T110	Yes	T16,T109,T110	INPUT
alert_rx_i[2].ack_p	Yes	Yes	T16,T109,T110	Yes	T16,T109,T110	INPUT
alert_rx_i[2].ping_n	Unreachable	Unreachable		Unreachable		INPUT
alert_rx_i[2].ping_p	Unreachable	Unreachable		Unreachable		INPUT
alert_rx_i[3].ack_n	Yes	Yes	T16,T109,T110	Yes	T16,T109,T110	INPUT
alert_rx_i[3].ack_p	Yes	Yes	T16,T109,T110	Yes	T16,T109,T110	INPUT
alert_rx_i[3].ping_n	Unreachable	Unreachable		Unreachable		INPUT
alert_rx_i[3].ping_p	Unreachable	Unreachable		Unreachable		INPUT
alert_rx_i[4].ack_n	Yes	Yes	T16,T109,T110	Yes	T16,T109,T110	INPUT
alert_rx_i[4].ack_p	Yes	Yes	T16,T109,T114	Yes	T16,T109,T114	INPUT
alert_rx_i[4].ping_n	Unreachable	Unreachable		Unreachable		INPUT
alert_rx_i[4].ping_p	Unreachable	Unreachable		Unreachable		INPUT
alert_tx_o[0].alert_n	Yes	Yes	T16,T109,T110	Yes	T16,T109,T110	OUTPUT
alert_tx_o[0].alert_p	Yes	Yes	T16,T109,T110	Yes	T16,T109,T110	OUTPUT
alert_tx_o[1].alert_n	Yes	Yes	T16,T109,T110	Yes	T16,T109,T110	OUTPUT
alert_tx_o[1].alert_p	Yes	Yes	T16,T109,T183	Yes	T16,T109,T183	OUTPUT
alert_tx_o[2].alert_n	Yes	Yes	T16,T109,T110	Yes	T16,T109,T110	OUTPUT
alert_tx_o[2].alert_p	Yes	Yes	T16,T109,T110	Yes	T16,T109,T110	OUTPUT
alert_tx_o[3].alert_n	Yes	Yes	T16,T109,T110	Yes	T16,T109,T110	OUTPUT
alert_tx_o[3].alert_p	Yes	Yes	T16,T109,T110	Yes	T16,T109,T110	OUTPUT
alert_tx_o[4].alert_n	Yes	Yes	T16,T109,T110	Yes	T16,T109,T110	OUTPUT
alert_tx_o[4].alert_p	Yes	Yes	T16,T109,T114	Yes	T16,T109,T114	OUTPUT
obs_ctrl_i.obmen[3:0]	No	No		No		INPUT
obs_ctrl_i.obmsl[3:0]	No	No		No		INPUT
obs_ctrl_i.obgsl[3:0]	No	No		No		INPUT
otp_obs_o[7:0]	Unreachable	Unreachable		Unreachable		OUTPUT
otp_ast_pwr_seq_o.pwr_seq[1:0]	No	No		No		OUTPUT
otp_ast_pwr_seq_h_i.pwr_seq_h[1:0]	Yes	Yes	T115,T185,T211	Yes	T115,T185,T211	INPUT
pwr_otp_i.otp_init	Yes	Yes	T16,T109,T110	Yes	T16,T109,T110	INPUT
pwr_otp_o.otp_idle	Yes	Yes	T110,T115,T184	Yes	T16,T109,T110	OUTPUT
pwr_otp_o.otp_done	Yes	Yes	T110,T115,T184	Yes	T16,T109,T110	OUTPUT
lc_otp_vendor_test_i.ctrl[31:0]	No	No		No		INPUT
lc_otp_vendor_test_o.status[31:0]	No	No		No		OUTPUT
lc_otp_program_i.count[383:0]	Yes	Yes	T102,T212,T213	Yes	T121,T102,T212	INPUT
lc_otp_program_i.state[319:0]	Yes	Yes	T102,T213,T214	Yes	T102,T215,T216	INPUT
lc_otp_program_i.req	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
lc_otp_program_o.ack	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
lc_otp_program_o.err	Yes	Yes	T95,T121,T102	Yes	T95,T121,T102	OUTPUT
lc_creator_seed_sw_rw_en_i[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
lc_seed_hw_rd_en_i[3:0]	Yes	Yes	T115,T211,T217	Yes	T115,T211,T217	INPUT
lc_dft_en_i[3:0]	Yes	Yes	T110,T115,T185	Yes	T16,T110,T114	INPUT
lc_escalate_en_i[3:0]	Yes	Yes	T7,T107,T95	Yes	T7,T107,T95	INPUT
lc_check_byp_en_i[3:0]	Yes	Yes	T16,T109,T110	Yes	T16,T109,T110	INPUT
otp_lc_data_o.rma_token[127:0]	Yes	Yes	T11,T93,T95	Yes	T93,T95,T96	OUTPUT
otp_lc_data_o.rma_token_valid[3:0]	Yes	Yes	T2,T3,T6	Yes	T2,T3,T6	OUTPUT
otp_lc_data_o.test_exit_token[127:0]	Yes	Yes	T110,T115,T184	Yes	T16,T109,T110	OUTPUT
otp_lc_data_o.test_unlock_token[127:0]	Yes	Yes	T110,T115,T184	Yes	T16,T109,T110	OUTPUT
otp_lc_data_o.test_tokens_valid[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
otp_lc_data_o.secrets_valid[3:0]	Yes	Yes	T2,T3,T6	Yes	T2,T3,T6	OUTPUT
otp_lc_data_o.count[3:0]	Yes	Yes	*T16,*T109,*T110	Yes	T110,T115,T184	OUTPUT
otp_lc_data_o.count[4]	No	No		No		OUTPUT
otp_lc_data_o.count[8:5]	Yes	Yes	*T16,*T109,*T110	Yes	T110,T115,T184	OUTPUT
otp_lc_data_o.count[9]	No	No		No		OUTPUT
otp_lc_data_o.count[10]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	OUTPUT
otp_lc_data_o.count[11]	No	No		No		OUTPUT
otp_lc_data_o.count[15:12]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	OUTPUT
otp_lc_data_o.count[16]	No	No		No		OUTPUT
otp_lc_data_o.count[29:17]	Yes	Yes	*T16,*T109,*T110	Yes	T110,T115,T184	OUTPUT
otp_lc_data_o.count[32:30]	No	No		No		OUTPUT
otp_lc_data_o.count[41:33]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	OUTPUT
otp_lc_data_o.count[42]	No	No		No		OUTPUT
otp_lc_data_o.count[46:43]	Yes	Yes	*T16,*T109,*T110	Yes	T110,T115,T184	OUTPUT
otp_lc_data_o.count[47]	No	No		No		OUTPUT
otp_lc_data_o.count[54:48]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	OUTPUT
otp_lc_data_o.count[55]	No	No		No		OUTPUT
otp_lc_data_o.count[62:56]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	OUTPUT
otp_lc_data_o.count[65:63]	No	No		No		OUTPUT
otp_lc_data_o.count[76:66]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	OUTPUT
otp_lc_data_o.count[77]	No	No		No		OUTPUT
otp_lc_data_o.count[78]	Yes	Yes	*T16,*T109,*T110	Yes	T110,T115,T184	OUTPUT
otp_lc_data_o.count[79]	No	No		No		OUTPUT
otp_lc_data_o.count[84:80]	Yes	Yes	*T16,*T109,*T110	Yes	T110,T115,T184	OUTPUT
otp_lc_data_o.count[85]	No	No		No		OUTPUT
otp_lc_data_o.count[88:86]	Yes	Yes	*T16,*T109,*T110	Yes	T110,T115,T184	OUTPUT
otp_lc_data_o.count[89]	No	No		No		OUTPUT
otp_lc_data_o.count[101:90]	Yes	Yes	*T16,*T109,*T110	Yes	T110,T115,T184	OUTPUT
otp_lc_data_o.count[102]	No	No		No		OUTPUT
otp_lc_data_o.count[105:103]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	OUTPUT
otp_lc_data_o.count[106]	No	No		No		OUTPUT
otp_lc_data_o.count[118:107]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	OUTPUT
otp_lc_data_o.count[119]	No	No		No		OUTPUT
otp_lc_data_o.count[121:120]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
otp_lc_data_o.count[122]	No	No		No		OUTPUT
otp_lc_data_o.count[124:123]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	OUTPUT
otp_lc_data_o.count[125]	No	No		No		OUTPUT
otp_lc_data_o.count[137:126]	Yes	Yes	*T16,*T109,*T110	Yes	T110,T115,T184	OUTPUT
otp_lc_data_o.count[138]	No	No		No		OUTPUT
otp_lc_data_o.count[142:139]	Yes	Yes	*T16,*T109,*T110	Yes	T110,T115,T184	OUTPUT
otp_lc_data_o.count[143]	No	No		No		OUTPUT
otp_lc_data_o.count[147:144]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
otp_lc_data_o.count[148]	No	No		No		OUTPUT
otp_lc_data_o.count[158:149]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	OUTPUT
otp_lc_data_o.count[159]	No	No		No		OUTPUT
otp_lc_data_o.count[164:160]	Yes	Yes	*T16,*T109,*T110	Yes	T110,T115,T184	OUTPUT
otp_lc_data_o.count[165]	No	No		No		OUTPUT
otp_lc_data_o.count[171:166]	Yes	Yes	*T16,*T109,*T110	Yes	T110,T115,T184	OUTPUT
otp_lc_data_o.count[172]	No	No		No		OUTPUT
otp_lc_data_o.count[180:173]	Yes	Yes	*T16,*T109,*T110	Yes	T110,T115,T184	OUTPUT
otp_lc_data_o.count[181]	No	No		No		OUTPUT
otp_lc_data_o.count[185:182]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	OUTPUT
otp_lc_data_o.count[187:186]	No	No		No		OUTPUT
otp_lc_data_o.count[191:188]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	OUTPUT
otp_lc_data_o.count[192]	No	No		No		OUTPUT
otp_lc_data_o.count[193]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	OUTPUT
otp_lc_data_o.count[195:194]	No	No		No		OUTPUT
otp_lc_data_o.count[202:196]	Yes	Yes	*T16,*T109,*T110	Yes	T110,T115,T184	OUTPUT
otp_lc_data_o.count[203]	No	No		No		OUTPUT
otp_lc_data_o.count[215:204]	Yes	Yes	*T16,*T109,*T110	Yes	T110,T115,T184	OUTPUT
otp_lc_data_o.count[216]	No	No		No		OUTPUT
otp_lc_data_o.count[217]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	OUTPUT
otp_lc_data_o.count[218]	No	No		No		OUTPUT
otp_lc_data_o.count[225:219]	Yes	Yes	*T16,*T109,*T110	Yes	T110,T115,T184	OUTPUT
otp_lc_data_o.count[227:226]	No	No		No		OUTPUT
otp_lc_data_o.count[228]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	OUTPUT
otp_lc_data_o.count[229]	No	No		No		OUTPUT
otp_lc_data_o.count[237:230]	Yes	Yes	*T16,*T109,*T110	Yes	T110,T115,T184	OUTPUT
otp_lc_data_o.count[238]	No	No		No		OUTPUT
otp_lc_data_o.count[240:239]	Yes	Yes	*T16,*T109,*T110	Yes	T110,T115,T184	OUTPUT
otp_lc_data_o.count[241]	No	No		No		OUTPUT
otp_lc_data_o.count[243:242]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	OUTPUT
otp_lc_data_o.count[245:244]	No	No		No		OUTPUT
otp_lc_data_o.count[269:246]	Yes	Yes	*T16,*T109,*T110	Yes	T110,T115,T184	OUTPUT
otp_lc_data_o.count[270]	No	No		No		OUTPUT
otp_lc_data_o.count[292:271]	Yes	Yes	*T16,*T109,*T110	Yes	T110,T115,T184	OUTPUT
otp_lc_data_o.count[293]	No	No		No		OUTPUT
otp_lc_data_o.count[303:294]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	OUTPUT
otp_lc_data_o.count[304]	No	No		No		OUTPUT
otp_lc_data_o.count[312:305]	Yes	Yes	*T16,*T109,*T110	Yes	T110,T115,T184	OUTPUT
otp_lc_data_o.count[313]	No	No		No		OUTPUT
otp_lc_data_o.count[324:314]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	OUTPUT
otp_lc_data_o.count[325]	No	No		No		OUTPUT
otp_lc_data_o.count[327:326]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	OUTPUT
otp_lc_data_o.count[328]	No	No		No		OUTPUT
otp_lc_data_o.count[330:329]	Yes	Yes	*T16,*T109,*T110	Yes	T110,T115,T184	OUTPUT
otp_lc_data_o.count[331]	No	No		No		OUTPUT
otp_lc_data_o.count[343:332]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	OUTPUT
otp_lc_data_o.count[344]	No	No		No		OUTPUT
otp_lc_data_o.count[345]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	OUTPUT
otp_lc_data_o.count[346]	No	No		No		OUTPUT
otp_lc_data_o.count[357:347]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	OUTPUT
otp_lc_data_o.count[358]	No	No		No		OUTPUT
otp_lc_data_o.count[364:359]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	OUTPUT
otp_lc_data_o.count[365]	No	No		No		OUTPUT
otp_lc_data_o.count[366]	Yes	Yes	*T16,*T109,*T110	Yes	T110,T115,T184	OUTPUT
otp_lc_data_o.count[367]	No	No		No		OUTPUT
otp_lc_data_o.count[383:368]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
otp_lc_data_o.state[5:0]	Yes	Yes	*T16,*T109,*T110	Yes	T110,T115,T184	OUTPUT
otp_lc_data_o.state[6]	No	No		No		OUTPUT
otp_lc_data_o.state[12:7]	Yes	Yes	*T16,*T109,*T110	Yes	T110,T115,T184	OUTPUT
otp_lc_data_o.state[13]	No	No		No		OUTPUT
otp_lc_data_o.state[14]	Yes	Yes	*T16,*T109,*T110	Yes	T110,T115,T184	OUTPUT
otp_lc_data_o.state[16:15]	No	No		No		OUTPUT
otp_lc_data_o.state[17]	Yes	Yes	*T16,*T109,*T110	Yes	T110,T115,T184	OUTPUT
otp_lc_data_o.state[20:18]	No	No		No		OUTPUT
otp_lc_data_o.state[21]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	OUTPUT
otp_lc_data_o.state[22]	No	No		No		OUTPUT
otp_lc_data_o.state[31:23]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	OUTPUT
otp_lc_data_o.state[32]	No	No		No		OUTPUT
otp_lc_data_o.state[34:33]	Yes	Yes	*T16,*T109,*T110	Yes	T110,T115,T184	OUTPUT
otp_lc_data_o.state[37:35]	No	No		No		OUTPUT
otp_lc_data_o.state[46:38]	Yes	Yes	*T16,*T109,*T110	Yes	T110,T115,T184	OUTPUT
otp_lc_data_o.state[47]	No	No		No		OUTPUT
otp_lc_data_o.state[50:48]	Yes	Yes	*T16,*T109,*T110	Yes	T110,T115,T184	OUTPUT
otp_lc_data_o.state[51]	No	No		No		OUTPUT
otp_lc_data_o.state[52]	Yes	Yes	*T16,*T109,*T110	Yes	T110,T115,T184	OUTPUT
otp_lc_data_o.state[53]	No	No		No		OUTPUT
otp_lc_data_o.state[59:54]	Yes	Yes	*T16,*T109,*T110	Yes	T110,T115,T184	OUTPUT
otp_lc_data_o.state[60]	No	No		No		OUTPUT
otp_lc_data_o.state[61]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	OUTPUT
otp_lc_data_o.state[62]	No	No		No		OUTPUT
otp_lc_data_o.state[73:63]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	OUTPUT
otp_lc_data_o.state[74]	No	No		No		OUTPUT
otp_lc_data_o.state[83:75]	Yes	Yes	*T16,*T109,*T110	Yes	T110,T115,T184	OUTPUT
otp_lc_data_o.state[84]	No	No		No		OUTPUT
otp_lc_data_o.state[87:85]	Yes	Yes	*T16,*T109,*T110	Yes	T110,T115,T184	OUTPUT
otp_lc_data_o.state[88]	No	No		No		OUTPUT
otp_lc_data_o.state[101:89]	Yes	Yes	*T16,*T109,*T110	Yes	T110,T115,T184	OUTPUT
otp_lc_data_o.state[102]	No	No		No		OUTPUT
otp_lc_data_o.state[103]	Yes	Yes	*T16,*T109,*T110	Yes	T110,T115,T184	OUTPUT
otp_lc_data_o.state[104]	No	No		No		OUTPUT
otp_lc_data_o.state[105]	Yes	Yes	*T16,*T109,*T110	Yes	T110,T115,T184	OUTPUT
otp_lc_data_o.state[107:106]	No	No		No		OUTPUT
otp_lc_data_o.state[113:108]	Yes	Yes	*T16,*T109,*T110	Yes	T110,T115,T184	OUTPUT
otp_lc_data_o.state[115:114]	No	No		No		OUTPUT
otp_lc_data_o.state[121:116]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	OUTPUT
otp_lc_data_o.state[122]	No	No		No		OUTPUT
otp_lc_data_o.state[126:123]	Yes	Yes	*T16,*T109,*T110	Yes	T110,T115,T184	OUTPUT
otp_lc_data_o.state[127]	No	No		No		OUTPUT
otp_lc_data_o.state[136:128]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	OUTPUT
otp_lc_data_o.state[137]	No	No		No		OUTPUT
otp_lc_data_o.state[145:138]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	OUTPUT
otp_lc_data_o.state[147:146]	No	No		No		OUTPUT
otp_lc_data_o.state[152:148]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	OUTPUT
otp_lc_data_o.state[154:153]	No	No		No		OUTPUT
otp_lc_data_o.state[156:155]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	OUTPUT
otp_lc_data_o.state[158:157]	No	No		No		OUTPUT
otp_lc_data_o.state[160:159]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
otp_lc_data_o.state[161]	No	No		No		OUTPUT
otp_lc_data_o.state[163:162]	Yes	Yes	*T16,*T109,*T110	Yes	T110,T115,T184	OUTPUT
otp_lc_data_o.state[165:164]	No	No		No		OUTPUT
otp_lc_data_o.state[177:166]	Yes	Yes	*T16,*T109,*T110	Yes	T110,T115,T184	OUTPUT
otp_lc_data_o.state[178]	No	No		No		OUTPUT
otp_lc_data_o.state[180:179]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
otp_lc_data_o.state[181]	No	No		No		OUTPUT
otp_lc_data_o.state[182]	Yes	Yes	*T16,*T109,*T110	Yes	T110,T115,T184	OUTPUT
otp_lc_data_o.state[183]	No	No		No		OUTPUT
otp_lc_data_o.state[198:184]	Yes	Yes	*T16,*T109,*T110	Yes	T110,T115,T184	OUTPUT
otp_lc_data_o.state[199]	No	No		No		OUTPUT
otp_lc_data_o.state[206:200]	Yes	Yes	*T16,*T109,*T110	Yes	T110,T115,T184	OUTPUT
otp_lc_data_o.state[207]	No	No		No		OUTPUT
otp_lc_data_o.state[210:208]	Yes	Yes	T16,T109,T110	Yes	T110,T115,T184	OUTPUT
otp_lc_data_o.state[211]	No	No		No		OUTPUT
otp_lc_data_o.state[214:212]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	OUTPUT
otp_lc_data_o.state[215]	No	No		No		OUTPUT
otp_lc_data_o.state[217:216]	Yes	Yes	*T16,*T109,*T110	Yes	T110,T115,T184	OUTPUT
otp_lc_data_o.state[218]	No	No		No		OUTPUT
otp_lc_data_o.state[219]	Yes	Yes	*T1,*T3,*T6	Yes	T1,T3,T6	OUTPUT
otp_lc_data_o.state[221:220]	No	No		No		OUTPUT
otp_lc_data_o.state[230:222]	Yes	Yes	*T16,*T109,*T110	Yes	T110,T115,T184	OUTPUT
otp_lc_data_o.state[231]	No	No		No		OUTPUT
otp_lc_data_o.state[234:232]	Yes	Yes	T1,T3,T6	Yes	T1,T3,T6	OUTPUT
otp_lc_data_o.state[235]	No	No		No		OUTPUT
otp_lc_data_o.state[239:236]	Yes	Yes	*T16,*T109,*T110	Yes	T110,T115,T184	OUTPUT
otp_lc_data_o.state[240]	No	No		No		OUTPUT
otp_lc_data_o.state[243:241]	Yes	Yes	T16,T109,T110	Yes	T110,T115,T184	OUTPUT
otp_lc_data_o.state[244]	No	No		No		OUTPUT
otp_lc_data_o.state[246:245]	Yes	Yes	T1,T3,T6	Yes	T1,T3,T6	OUTPUT
otp_lc_data_o.state[247]	No	No		No		OUTPUT
otp_lc_data_o.state[263:248]	Yes	Yes	*T1,*T3,*T6	Yes	T1,T3,T6	OUTPUT
otp_lc_data_o.state[264]	No	No		No		OUTPUT
otp_lc_data_o.state[268:265]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	OUTPUT
otp_lc_data_o.state[269]	No	No		No		OUTPUT
otp_lc_data_o.state[273:270]	Yes	Yes	*T1,*T3,*T6	Yes	T1,T3,T6	OUTPUT
otp_lc_data_o.state[274]	No	No		No		OUTPUT
otp_lc_data_o.state[278:275]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	OUTPUT
otp_lc_data_o.state[280:279]	No	No		No		OUTPUT
otp_lc_data_o.state[294:281]	Yes	Yes	*T1,*T3,*T6	Yes	T1,T3,T6	OUTPUT
otp_lc_data_o.state[295]	No	No		No		OUTPUT
otp_lc_data_o.state[301:296]	Yes	Yes	*T16,*T109,*T110	Yes	T110,T115,T184	OUTPUT
otp_lc_data_o.state[302]	No	No		No		OUTPUT
otp_lc_data_o.state[306:303]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
otp_lc_data_o.state[307]	No	No		No		OUTPUT
otp_lc_data_o.state[319:308]	Yes	Yes	T16,T109,T110	Yes	T110,T115,T184	OUTPUT
otp_lc_data_o.error	Yes	Yes	T7,T9,T37	Yes	T7,T9,T37	OUTPUT
otp_lc_data_o.valid	Yes	Yes	T110,T115,T184	Yes	T16,T109,T110	OUTPUT
otp_keymgr_key_o.key_share1[255:0]	Yes	Yes	T6,T95,T98	Yes	T6,T95,T98	OUTPUT
otp_keymgr_key_o.key_share0[255:0]	Yes	Yes	T115,T184,T211	Yes	T111,T181,T115	OUTPUT
otp_keymgr_key_o.valid	Yes	Yes	T2,T3,T6	Yes	T2,T3,T6	OUTPUT
flash_otp_key_i.addr_req	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
flash_otp_key_i.data_req	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
flash_otp_key_o.seed_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
flash_otp_key_o.rand_key[127:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
flash_otp_key_o.key[127:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
flash_otp_key_o.addr_ack	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
flash_otp_key_o.data_ack	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
sram_otp_key_i[0].req	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
sram_otp_key_i[1].req	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
sram_otp_key_i[2].req	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
sram_otp_key_o[0].seed_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
sram_otp_key_o[0].nonce[127:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
sram_otp_key_o[0].key[127:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
sram_otp_key_o[0].ack	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
sram_otp_key_o[1].seed_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
sram_otp_key_o[1].nonce[127:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
sram_otp_key_o[1].key[127:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
sram_otp_key_o[1].ack	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
sram_otp_key_o[2].seed_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
sram_otp_key_o[2].nonce[127:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
sram_otp_key_o[2].key[127:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
sram_otp_key_o[2].ack	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
otbn_otp_key_i.req	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
otbn_otp_key_o.seed_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
otbn_otp_key_o.nonce[63:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
otbn_otp_key_o.key[127:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
otbn_otp_key_o.ack	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
otp_hw_cfg_o.data.device_id[255:0]	Yes	Yes	T218,T101,T137	Yes	T108,T218,T101	OUTPUT
otp_hw_cfg_o.data.manuf_state[255:0]	Yes	Yes	T16,T109,T110	Yes	T110,T115,T184	OUTPUT
otp_hw_cfg_o.data.en_sram_ifetch[7:0]	Yes	Yes	T16,T109,T110	Yes	T110,T115,T184	OUTPUT
otp_hw_cfg_o.data.en_csrng_sw_app_read[7:0]	Yes	Yes	T16,T109,T110	Yes	T110,T115,T184	OUTPUT
otp_hw_cfg_o.data.en_entropy_src_fw_read[7:0]	Yes	Yes	T16,T109,T110	Yes	T110,T115,T184	OUTPUT
otp_hw_cfg_o.data.en_entropy_src_fw_over[7:0]	Yes	Yes	T16,T109,T110	Yes	T110,T115,T184	OUTPUT
otp_hw_cfg_o.data.unallocated[31:0]	Yes	Yes	T95,T98,T102	Yes	T108,T95,T98	OUTPUT
otp_hw_cfg_o.data.hw_cfg_digest[63:0]	Yes	Yes	T16,T109,T110	Yes	T110,T115,T184	OUTPUT
otp_hw_cfg_o.valid[3:0]	Yes	Yes	T110,T115,T184	Yes	T16,T109,T110	OUTPUT
otp_ext_voltage_h_io	No	No		No		INOUT
scan_en_i	Yes	Yes	T115,T211,T186	Yes	T110,T115,T185	INPUT
scan_rst_ni	Yes	Yes	T115,T185,T211	Yes	T110,T115,T184	INPUT
scanmode_i[3:0]	Yes	Yes	T115,T211,T117	Yes	T115,T184,T185	INPUT
cio_test_o[7:0]	No	No		No		OUTPUT
cio_test_en_o[7:0]	Yes	Yes	T110,T115,T184	Yes	T16,T109,T110	OUTPUT

*Tests covering at least one bit in the range

---

Branch Coverage for Module : otp_ctrl

	Line No.	Total	Covered	Percent
Branches		33	32	96.97
TERNARY	1299	2	2	100.00
TERNARY	1351	2	2	100.00
TERNARY	1353	2	2	100.00
TERNARY	1355	2	2	100.00
IF	267	3	2	66.67
IF	288	2	2	100.00
IF	328	2	2	100.00
IF	331	2	2	100.00
IF	334	2	2	100.00
IF	338	2	2	100.00
IF	398	2	2	100.00
IF	437	2	2	100.00
IF	458	2	2	100.00
IF	461	2	2	100.00
IF	498	2	2	100.00
IF	955	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_otp_ctrl_1.0/rtl/otp_ctrl.sv' or '../src/lowrisc_ip_otp_ctrl_1.0/rtl/otp_ctrl.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	1299	(part_init_done[HwCfgIdx]) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	1351	((part_digest[Secret0Idx] != '0)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	1353	((part_digest[Secret2Idx] != '0)) ? 

Branches:

-1-	Status	Tests
1	Covered	T2,T3,T6
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	1355	((part_digest[Secret2Idx] != '0)) ? 

Branches:

-1-	Status	Tests
1	Covered	T2,T3,T6
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	267	if (tlul_req)
-2-:	268	if ((tlul_part_sel_oh != '0))

Branches:

-1-	-2-	Status	Tests
1	1	Covered	T1,T2,T3
1	0	Not Covered
0	-	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	288	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	328	if ((!reg2hw.vendor_test_read_lock))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	331	if ((!reg2hw.creator_sw_cfg_read_lock))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	334	if ((!reg2hw.owner_sw_cfg_read_lock))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	338	if (lc_ctrl_pkg::lc_tx_test_false_loose(lc_creator_seed_sw_rw_en))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	398	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	437	if (otp_ctrl_part_pkg::PartInfo[k].ecc_fatal)

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	458	if ((fatal_macro_error_q || fatal_check_error_q))

Branches:

-1-	Status	Tests
1	Covered	T7,T9,T37
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	461	if (lc_ctrl_pkg::lc_tx_test_true_strict(lc_escalate_en[k]))

Branches:

-1-	Status	Tests
1	Covered	T7,T9,T37
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	498	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	955	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Module : otp_ctrl

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	64	64	100.00	64	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	64	64	100.00	64	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AlertTxKnown_A	2147483647	2147483647	0	0
CoreTlOutKnown_A	2147483647	2147483647	0	0
CreatorRootKeyShare0Size_A	1157	1157	0	0
CreatorRootKeyShare1Size_A	1157	1157	0	0
ErrorCodeWidth_A	1157	1157	0	0
FlashAddrKeySeedSize_A	1157	1157	0	0
FlashDataKeySeedSize_A	1157	1157	0	0
FlashOtpKeyRspKnown_A	2147483647	2147483647	0	0
FpvSecCmCntCnstyCheck_A	2147483647	50	0	0
FpvSecCmCntDaiCheck_A	2147483647	50	0	0
FpvSecCmCntIntegCheck_A	2147483647	50	0	0
FpvSecCmCntKdiEntropyCheck_A	2147483647	50	0	0
FpvSecCmCntKdiSeedCheck_A	2147483647	50	0	0
FpvSecCmCntLciCheck_A	2147483647	50	0	0
FpvSecCmCntScrmblCheck_A	2147483647	50	0	0
FpvSecCmCtrlDaiFsmCheck_A	2147483647	50	0	0
FpvSecCmCtrlKdiFsmCheck_A	2147483647	50	0	0
FpvSecCmCtrlLciFsmCheck_A	2147483647	50	0	0
FpvSecCmCtrlLfsrTimerFsmCheck_A	2147483647	50	0	0
FpvSecCmCtrlScrambleFsmCheck_A	2147483647	50	0	0
FpvSecCmDoubleLfsrCheck_A	2147483647	50	0	0
FpvSecCmRegWeOnehotCheck_A	2147483647	50	0	0
FpvSecCmTlLcGateFsm_A	2147483647	50	0	0
IntrOtpErrorKnown_A	2147483647	2147483647	0	0
IntrOtpOperationDoneKnown_A	2147483647	2147483647	0	0
LcOtpProgramRspKnown_A	2147483647	2147483647	0	0
LcSeedHwRdEnStable_A	2147483647	2276	0	0
LcStateSize_A	1157	1157	0	0
LcTransitionCntSize_A	1157	1157	0	0
OtpAstPwrSeqKnown_A	2147483647	2147483647	0	0
OtpErrorCode0_A	1157	1157	0	0
OtpErrorCode1_A	1157	1157	0	0
OtpErrorCode2_A	1157	1157	0	0
OtpErrorCode3_A	1157	1157	0	0
OtpErrorCode4_A	1157	1157	0	0
OtpHwCfgKnown_A	2147483647	2147483647	0	0
OtpIfWidth_A	1157	1157	0	0
OtpKeymgrKeyKnown_A	2147483647	2147483647	0	0
OtpLcDataKnown_A	2147483647	2147483647	0	0
OtpOtgnKeyKnown_A	2147483647	2147483647	0	0
OtpRespFifoUnderflow_A	2147483647	1341882	0	0
OtpSramKeyKnown_A	2147483647	2147483647	0	0
PartSelMustBeOnehot_A	2147483647	2147483647	0	0
PrimTlOutKnown_A	2147483647	2147483647	0	0
PwrOtpInitRspKnown_A	2147483647	2147483647	0	0
RmaTokenSize_A	1157	1157	0	0
SramDataKeySeedSize_A	1157	1157	0	0
TestExitTokenSize_A	1157	1157	0	0
TestUnlockTokenSize_A	1157	1157	0	0
gen_partitions[0].gen_unbuffered.FpvSecCmCtrlPartUnbufFsmCheck_A	2147483647	50	0	0
gen_partitions[1].gen_unbuffered.FpvSecCmCtrlPartUnbufFsmCheck_A	2147483647	50	0	0
gen_partitions[2].gen_unbuffered.FpvSecCmCtrlPartUnbufFsmCheck_A	2147483647	50	0	0
gen_partitions[3].gen_buffered.FpvSecCmCntPartBufCheck_A	2147483647	50	0	0
gen_partitions[3].gen_buffered.FpvSecCmCtrlPartBufFsmCheck_A	2147483647	50	0	0
gen_partitions[4].gen_buffered.FpvSecCmCntPartBufCheck_A	2147483647	50	0	0
gen_partitions[4].gen_buffered.FpvSecCmCtrlPartBufFsmCheck_A	2147483647	50	0	0
gen_partitions[5].gen_buffered.FpvSecCmCntPartBufCheck_A	2147483647	50	0	0
gen_partitions[5].gen_buffered.FpvSecCmCtrlPartBufFsmCheck_A	2147483647	50	0	0
gen_partitions[6].gen_buffered.FpvSecCmCntPartBufCheck_A	2147483647	50	0	0
gen_partitions[6].gen_buffered.FpvSecCmCtrlPartBufFsmCheck_A	2147483647	50	0	0
gen_partitions[7].gen_lifecycle.FpvSecCmCntPartLcCheck_A	2147483647	50	0	0
gen_partitions[7].gen_lifecycle.FpvSecCmCtrlPartLcFsmCheck_A	2147483647	50	0	0
gen_reg_we_assert_generic.FpvSecCmPrimFsmCheck_A	2147483647	50	0	0
gen_reg_we_assert_generic.FpvSecCmPrimRegWeOnehotCheck_A	2147483647	50	0	0

AlertTxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	73436	72051	0	0
T2	38018	37309	0	0
T3	110228	108967	0	0
T5	7499	6741	0	0
T6	50788	49798	0	0
T7	111091	111090	0	0
T8	8171	8083	0	0
T9	19415	19147	0	0
T10	10832	10630	0	0
T11	12755	12519	0	0

CoreTlOutKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	73436	72051	0	0
T2	38018	37309	0	0
T3	110228	108967	0	0
T5	7499	6741	0	0
T6	50788	49798	0	0
T7	111091	111090	0	0
T8	8171	8083	0	0
T9	19415	19147	0	0
T10	10832	10630	0	0
T11	12755	12519	0	0

CreatorRootKeyShare0Size_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1157	1157	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0

CreatorRootKeyShare1Size_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1157	1157	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0

ErrorCodeWidth_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1157	1157	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0

FlashAddrKeySeedSize_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1157	1157	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0

FlashDataKeySeedSize_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1157	1157	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0

FlashOtpKeyRspKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	73436	72051	0	0
T2	38018	37309	0	0
T3	110228	108967	0	0
T5	7499	6741	0	0
T6	50788	49798	0	0
T7	111091	111090	0	0
T8	8171	8083	0	0
T9	19415	19147	0	0
T10	10832	10630	0	0
T11	12755	12519	0	0

FpvSecCmCntCnstyCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	50	0	0
T20	850632	10	0	0
T21	866086	10	0	0
T22	849475	10	0	0
T51	15976	0	0	0
T171	15714	0	0	0
T219	0	10	0	0
T220	0	10	0	0
T221	13660	0	0	0
T222	15281	0	0	0
T223	18644	0	0	0
T224	16459	0	0	0
T225	18030	0	0	0

FpvSecCmCntDaiCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	50	0	0
T20	850632	10	0	0
T21	866086	10	0	0
T22	849475	10	0	0
T51	15976	0	0	0
T171	15714	0	0	0
T219	0	10	0	0
T220	0	10	0	0
T221	13660	0	0	0
T222	15281	0	0	0
T223	18644	0	0	0
T224	16459	0	0	0
T225	18030	0	0	0

FpvSecCmCntIntegCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	50	0	0
T20	850632	10	0	0
T21	866086	10	0	0
T22	849475	10	0	0
T51	15976	0	0	0
T171	15714	0	0	0
T219	0	10	0	0
T220	0	10	0	0
T221	13660	0	0	0
T222	15281	0	0	0
T223	18644	0	0	0
T224	16459	0	0	0
T225	18030	0	0	0

FpvSecCmCntKdiEntropyCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	50	0	0
T20	850632	10	0	0
T21	866086	10	0	0
T22	849475	10	0	0
T51	15976	0	0	0
T171	15714	0	0	0
T219	0	10	0	0
T220	0	10	0	0
T221	13660	0	0	0
T222	15281	0	0	0
T223	18644	0	0	0
T224	16459	0	0	0
T225	18030	0	0	0

FpvSecCmCntKdiSeedCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	50	0	0
T20	850632	10	0	0
T21	866086	10	0	0
T22	849475	10	0	0
T51	15976	0	0	0
T171	15714	0	0	0
T219	0	10	0	0
T220	0	10	0	0
T221	13660	0	0	0
T222	15281	0	0	0
T223	18644	0	0	0
T224	16459	0	0	0
T225	18030	0	0	0

FpvSecCmCntLciCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	50	0	0
T20	850632	10	0	0
T21	866086	10	0	0
T22	849475	10	0	0
T51	15976	0	0	0
T171	15714	0	0	0
T219	0	10	0	0
T220	0	10	0	0
T221	13660	0	0	0
T222	15281	0	0	0
T223	18644	0	0	0
T224	16459	0	0	0
T225	18030	0	0	0

FpvSecCmCntScrmblCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	50	0	0
T20	850632	10	0	0
T21	866086	10	0	0
T22	849475	10	0	0
T51	15976	0	0	0
T171	15714	0	0	0
T219	0	10	0	0
T220	0	10	0	0
T221	13660	0	0	0
T222	15281	0	0	0
T223	18644	0	0	0
T224	16459	0	0	0
T225	18030	0	0	0

FpvSecCmCtrlDaiFsmCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	50	0	0
T20	850632	10	0	0
T21	866086	10	0	0
T22	849475	10	0	0
T51	15976	0	0	0
T171	15714	0	0	0
T219	0	10	0	0
T220	0	10	0	0
T221	13660	0	0	0
T222	15281	0	0	0
T223	18644	0	0	0
T224	16459	0	0	0
T225	18030	0	0	0

FpvSecCmCtrlKdiFsmCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	50	0	0
T20	850632	10	0	0
T21	866086	10	0	0
T22	849475	10	0	0
T51	15976	0	0	0
T171	15714	0	0	0
T219	0	10	0	0
T220	0	10	0	0
T221	13660	0	0	0
T222	15281	0	0	0
T223	18644	0	0	0
T224	16459	0	0	0
T225	18030	0	0	0

FpvSecCmCtrlLciFsmCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	50	0	0
T20	850632	10	0	0
T21	866086	10	0	0
T22	849475	10	0	0
T51	15976	0	0	0
T171	15714	0	0	0
T219	0	10	0	0
T220	0	10	0	0
T221	13660	0	0	0
T222	15281	0	0	0
T223	18644	0	0	0
T224	16459	0	0	0
T225	18030	0	0	0

FpvSecCmCtrlLfsrTimerFsmCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	50	0	0
T20	850632	10	0	0
T21	866086	10	0	0
T22	849475	10	0	0
T51	15976	0	0	0
T171	15714	0	0	0
T219	0	10	0	0
T220	0	10	0	0
T221	13660	0	0	0
T222	15281	0	0	0
T223	18644	0	0	0
T224	16459	0	0	0
T225	18030	0	0	0

FpvSecCmCtrlScrambleFsmCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	50	0	0
T20	850632	10	0	0
T21	866086	10	0	0
T22	849475	10	0	0
T51	15976	0	0	0
T171	15714	0	0	0
T219	0	10	0	0
T220	0	10	0	0
T221	13660	0	0	0
T222	15281	0	0	0
T223	18644	0	0	0
T224	16459	0	0	0
T225	18030	0	0	0

FpvSecCmDoubleLfsrCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	50	0	0
T20	850632	10	0	0
T21	866086	10	0	0
T22	849475	10	0	0
T51	15976	0	0	0
T171	15714	0	0	0
T219	0	10	0	0
T220	0	10	0	0
T221	13660	0	0	0
T222	15281	0	0	0
T223	18644	0	0	0
T224	16459	0	0	0
T225	18030	0	0	0

FpvSecCmRegWeOnehotCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	50	0	0
T20	850632	10	0	0
T21	866086	10	0	0
T22	849475	10	0	0
T51	15976	0	0	0
T171	15714	0	0	0
T219	0	10	0	0
T220	0	10	0	0
T221	13660	0	0	0
T222	15281	0	0	0
T223	18644	0	0	0
T224	16459	0	0	0
T225	18030	0	0	0

FpvSecCmTlLcGateFsm_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	50	0	0
T20	850632	10	0	0
T21	866086	10	0	0
T22	849475	10	0	0
T51	15976	0	0	0
T171	15714	0	0	0
T219	0	10	0	0
T220	0	10	0	0
T221	13660	0	0	0
T222	15281	0	0	0
T223	18644	0	0	0
T224	16459	0	0	0
T225	18030	0	0	0

IntrOtpErrorKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	73436	72051	0	0
T2	38018	37309	0	0
T3	110228	108967	0	0
T5	7499	6741	0	0
T6	50788	49798	0	0
T7	111091	111090	0	0
T8	8171	8083	0	0
T9	19415	19147	0	0
T10	10832	10630	0	0
T11	12755	12519	0	0

IntrOtpOperationDoneKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	73436	72051	0	0
T2	38018	37309	0	0
T3	110228	108967	0	0
T5	7499	6741	0	0
T6	50788	49798	0	0
T7	111091	111090	0	0
T8	8171	8083	0	0
T9	19415	19147	0	0
T10	10832	10630	0	0
T11	12755	12519	0	0

LcOtpProgramRspKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	73436	72051	0	0
T2	38018	37309	0	0
T3	110228	108967	0	0
T5	7499	6741	0	0
T6	50788	49798	0	0
T7	111091	111090	0	0
T8	8171	8083	0	0
T9	19415	19147	0	0
T10	10832	10630	0	0
T11	12755	12519	0	0

LcSeedHwRdEnStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2276	0	0
T2	38018	6	0	0
T3	110228	6	0	0
T5	7499	0	0	0
T6	50788	7	0	0
T7	111091	0	0	0
T8	8171	0	0	0
T9	19415	0	0	0
T10	10832	1	0	0
T11	12755	0	0	0
T26	0	1	0	0
T29	0	5	0	0
T94	0	5	0	0
T95	0	40	0	0
T104	0	2	0	0
T106	9868	1	0	0

LcStateSize_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1157	1157	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0

LcTransitionCntSize_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1157	1157	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0

OtpAstPwrSeqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	73436	72051	0	0
T2	38018	37309	0	0
T3	110228	108967	0	0
T5	7499	6741	0	0
T6	50788	49798	0	0
T7	111091	111090	0	0
T8	8171	8083	0	0
T9	19415	19147	0	0
T10	10832	10630	0	0
T11	12755	12519	0	0

OtpErrorCode0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1157	1157	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0

OtpErrorCode1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1157	1157	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0

OtpErrorCode2_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1157	1157	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0

OtpErrorCode3_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1157	1157	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0

OtpErrorCode4_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1157	1157	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0

OtpHwCfgKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	73436	72051	0	0
T2	38018	37309	0	0
T3	110228	108967	0	0
T5	7499	6741	0	0
T6	50788	49798	0	0
T7	111091	111090	0	0
T8	8171	8083	0	0
T9	19415	19147	0	0
T10	10832	10630	0	0
T11	12755	12519	0	0

OtpIfWidth_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1157	1157	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0

OtpKeymgrKeyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	73436	72051	0	0
T2	38018	37309	0	0
T3	110228	108967	0	0
T5	7499	6741	0	0
T6	50788	49798	0	0
T7	111091	111090	0	0
T8	8171	8083	0	0
T9	19415	19147	0	0
T10	10832	10630	0	0
T11	12755	12519	0	0

OtpLcDataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	73436	72051	0	0
T2	38018	37309	0	0
T3	110228	108967	0	0
T5	7499	6741	0	0
T6	50788	49798	0	0
T7	111091	111090	0	0
T8	8171	8083	0	0
T9	19415	19147	0	0
T10	10832	10630	0	0
T11	12755	12519	0	0

OtpOtgnKeyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	73436	72051	0	0
T2	38018	37309	0	0
T3	110228	108967	0	0
T5	7499	6741	0	0
T6	50788	49798	0	0
T7	111091	111090	0	0
T8	8171	8083	0	0
T9	19415	19147	0	0
T10	10832	10630	0	0
T11	12755	12519	0	0

OtpRespFifoUnderflow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1341882	0	0
T1	73436	1479	0	0
T2	38018	841	0	0
T3	110228	1328	0	0
T5	7499	136	0	0
T6	50788	2598	0	0
T7	111091	1043	0	0
T8	8171	52	0	0
T9	19415	162	0	0
T10	10832	254	0	0
T11	12755	271	0	0

OtpSramKeyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	73436	72051	0	0
T2	38018	37309	0	0
T3	110228	108967	0	0
T5	7499	6741	0	0
T6	50788	49798	0	0
T7	111091	111090	0	0
T8	8171	8083	0	0
T9	19415	19147	0	0
T10	10832	10630	0	0
T11	12755	12519	0	0

PartSelMustBeOnehot_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	73436	72051	0	0
T2	38018	37309	0	0
T3	110228	108967	0	0
T5	7499	6741	0	0
T6	50788	49798	0	0
T7	111091	111090	0	0
T8	8171	8083	0	0
T9	19415	19147	0	0
T10	10832	10630	0	0
T11	12755	12519	0	0

PrimTlOutKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	73436	72051	0	0
T2	38018	37309	0	0
T3	110228	108967	0	0
T5	7499	6741	0	0
T6	50788	49798	0	0
T7	111091	111090	0	0
T8	8171	8083	0	0
T9	19415	19147	0	0
T10	10832	10630	0	0
T11	12755	12519	0	0

PwrOtpInitRspKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	73436	72051	0	0
T2	38018	37309	0	0
T3	110228	108967	0	0
T5	7499	6741	0	0
T6	50788	49798	0	0
T7	111091	111090	0	0
T8	8171	8083	0	0
T9	19415	19147	0	0
T10	10832	10630	0	0
T11	12755	12519	0	0

RmaTokenSize_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1157	1157	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0

SramDataKeySeedSize_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1157	1157	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0

TestExitTokenSize_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1157	1157	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0

TestUnlockTokenSize_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1157	1157	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0

gen_partitions[0].gen_unbuffered.FpvSecCmCtrlPartUnbufFsmCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	50	0	0
T20	850632	10	0	0
T21	866086	10	0	0
T22	849475	10	0	0
T51	15976	0	0	0
T171	15714	0	0	0
T219	0	10	0	0
T220	0	10	0	0
T221	13660	0	0	0
T222	15281	0	0	0
T223	18644	0	0	0
T224	16459	0	0	0
T225	18030	0	0	0

gen_partitions[1].gen_unbuffered.FpvSecCmCtrlPartUnbufFsmCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	50	0	0
T20	850632	10	0	0
T21	866086	10	0	0
T22	849475	10	0	0
T51	15976	0	0	0
T171	15714	0	0	0
T219	0	10	0	0
T220	0	10	0	0
T221	13660	0	0	0
T222	15281	0	0	0
T223	18644	0	0	0
T224	16459	0	0	0
T225	18030	0	0	0

gen_partitions[2].gen_unbuffered.FpvSecCmCtrlPartUnbufFsmCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	50	0	0
T20	850632	10	0	0
T21	866086	10	0	0
T22	849475	10	0	0
T51	15976	0	0	0
T171	15714	0	0	0
T219	0	10	0	0
T220	0	10	0	0
T221	13660	0	0	0
T222	15281	0	0	0
T223	18644	0	0	0
T224	16459	0	0	0
T225	18030	0	0	0

gen_partitions[3].gen_buffered.FpvSecCmCntPartBufCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	50	0	0
T20	850632	10	0	0
T21	866086	10	0	0
T22	849475	10	0	0
T51	15976	0	0	0
T171	15714	0	0	0
T219	0	10	0	0
T220	0	10	0	0
T221	13660	0	0	0
T222	15281	0	0	0
T223	18644	0	0	0
T224	16459	0	0	0
T225	18030	0	0	0

gen_partitions[3].gen_buffered.FpvSecCmCtrlPartBufFsmCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	50	0	0
T20	850632	10	0	0
T21	866086	10	0	0
T22	849475	10	0	0
T51	15976	0	0	0
T171	15714	0	0	0
T219	0	10	0	0
T220	0	10	0	0
T221	13660	0	0	0
T222	15281	0	0	0
T223	18644	0	0	0
T224	16459	0	0	0
T225	18030	0	0	0

gen_partitions[4].gen_buffered.FpvSecCmCntPartBufCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	50	0	0
T20	850632	10	0	0
T21	866086	10	0	0
T22	849475	10	0	0
T51	15976	0	0	0
T171	15714	0	0	0
T219	0	10	0	0
T220	0	10	0	0
T221	13660	0	0	0
T222	15281	0	0	0
T223	18644	0	0	0
T224	16459	0	0	0
T225	18030	0	0	0

gen_partitions[4].gen_buffered.FpvSecCmCtrlPartBufFsmCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	50	0	0
T20	850632	10	0	0
T21	866086	10	0	0
T22	849475	10	0	0
T51	15976	0	0	0
T171	15714	0	0	0
T219	0	10	0	0
T220	0	10	0	0
T221	13660	0	0	0
T222	15281	0	0	0
T223	18644	0	0	0
T224	16459	0	0	0
T225	18030	0	0	0

gen_partitions[5].gen_buffered.FpvSecCmCntPartBufCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	50	0	0
T20	850632	10	0	0
T21	866086	10	0	0
T22	849475	10	0	0
T51	15976	0	0	0
T171	15714	0	0	0
T219	0	10	0	0
T220	0	10	0	0
T221	13660	0	0	0
T222	15281	0	0	0
T223	18644	0	0	0
T224	16459	0	0	0
T225	18030	0	0	0

gen_partitions[5].gen_buffered.FpvSecCmCtrlPartBufFsmCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	50	0	0
T20	850632	10	0	0
T21	866086	10	0	0
T22	849475	10	0	0
T51	15976	0	0	0
T171	15714	0	0	0
T219	0	10	0	0
T220	0	10	0	0
T221	13660	0	0	0
T222	15281	0	0	0
T223	18644	0	0	0
T224	16459	0	0	0
T225	18030	0	0	0

gen_partitions[6].gen_buffered.FpvSecCmCntPartBufCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	50	0	0
T20	850632	10	0	0
T21	866086	10	0	0
T22	849475	10	0	0
T51	15976	0	0	0
T171	15714	0	0	0
T219	0	10	0	0
T220	0	10	0	0
T221	13660	0	0	0
T222	15281	0	0	0
T223	18644	0	0	0
T224	16459	0	0	0
T225	18030	0	0	0

gen_partitions[6].gen_buffered.FpvSecCmCtrlPartBufFsmCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	50	0	0
T20	850632	10	0	0
T21	866086	10	0	0
T22	849475	10	0	0
T51	15976	0	0	0
T171	15714	0	0	0
T219	0	10	0	0
T220	0	10	0	0
T221	13660	0	0	0
T222	15281	0	0	0
T223	18644	0	0	0
T224	16459	0	0	0
T225	18030	0	0	0

gen_partitions[7].gen_lifecycle.FpvSecCmCntPartLcCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	50	0	0
T20	850632	10	0	0
T21	866086	10	0	0
T22	849475	10	0	0
T51	15976	0	0	0
T171	15714	0	0	0
T219	0	10	0	0
T220	0	10	0	0
T221	13660	0	0	0
T222	15281	0	0	0
T223	18644	0	0	0
T224	16459	0	0	0
T225	18030	0	0	0

gen_partitions[7].gen_lifecycle.FpvSecCmCtrlPartLcFsmCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	50	0	0
T20	850632	10	0	0
T21	866086	10	0	0
T22	849475	10	0	0
T51	15976	0	0	0
T171	15714	0	0	0
T219	0	10	0	0
T220	0	10	0	0
T221	13660	0	0	0
T222	15281	0	0	0
T223	18644	0	0	0
T224	16459	0	0	0
T225	18030	0	0	0

gen_reg_we_assert_generic.FpvSecCmPrimFsmCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	50	0	0
T20	850632	10	0	0
T21	866086	10	0	0
T22	849475	10	0	0
T51	15976	0	0	0
T171	15714	0	0	0
T219	0	10	0	0
T220	0	10	0	0
T221	13660	0	0	0
T222	15281	0	0	0
T223	18644	0	0	0
T224	16459	0	0	0
T225	18030	0	0	0

gen_reg_we_assert_generic.FpvSecCmPrimRegWeOnehotCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	50	0	0
T20	850632	10	0	0
T21	866086	10	0	0
T22	849475	10	0	0
T51	15976	0	0	0
T171	15714	0	0	0
T219	0	10	0	0
T220	0	10	0	0
T221	13660	0	0	0
T222	15281	0	0	0
T223	18644	0	0	0
T224	16459	0	0	0
T225	18030	0	0	0

Line Coverage for Instance : tb.dut

	Line No.	Total	Covered	Percent
TOTAL		142	139	97.89
CONT_ASSIGN	234	1	1	100.00
CONT_ASSIGN	234	1	1	100.00
CONT_ASSIGN	234	1	1	100.00
CONT_ASSIGN	234	1	1	100.00
CONT_ASSIGN	234	1	1	100.00
CONT_ASSIGN	234	1	1	100.00
CONT_ASSIGN	234	1	1	100.00
CONT_ASSIGN	234	1	1	100.00
ALWAYS	264	14	13	92.86
ALWAYS	288	3	3	100.00
CONT_ASSIGN	301	1	1	100.00
CONT_ASSIGN	302	1	1	100.00
CONT_ASSIGN	303	1	1	100.00
CONT_ASSIGN	304	1	1	100.00
CONT_ASSIGN	305	1	1	100.00
CONT_ASSIGN	306	1	1	100.00
CONT_ASSIGN	307	1	1	100.00
CONT_ASSIGN	309	1	1	100.00
ALWAYS	319	11	11	100.00
CONT_ASSIGN	374	1	1	100.00
CONT_ASSIGN	378	1	1	100.00
CONT_ASSIGN	382	1	1	100.00
CONT_ASSIGN	383	1	1	100.00
CONT_ASSIGN	384	1	1	100.00
CONT_ASSIGN	386	1	1	100.00
CONT_ASSIGN	394	1	1	100.00
CONT_ASSIGN	395	1	1	100.00
ALWAYS	398	3	3	100.00
ALWAYS	420	20	20	100.00
CONT_ASSIGN	474	1	1	100.00
CONT_ASSIGN	487	1	1	100.00
CONT_ASSIGN	495	1	1	100.00
ALWAYS	498	9	9	100.00
CONT_ASSIGN	549	1	1	100.00
CONT_ASSIGN	557	1	1	100.00
CONT_ASSIGN	604	1	1	100.00
CONT_ASSIGN	606	1	1	100.00
CONT_ASSIGN	729	1	1	100.00
CONT_ASSIGN	730	1	1	100.00
CONT_ASSIGN	731	1	1	100.00
CONT_ASSIGN	761	1	1	100.00
CONT_ASSIGN	763	1	1	100.00
ALWAYS	840	2	2	100.00
ALWAYS	898	2	2	100.00
ALWAYS	925	4	4	100.00
CONT_ASSIGN	952	1	1	100.00
ALWAYS	955	3	3	100.00
CONT_ASSIGN	1007	1	1	100.00
CONT_ASSIGN	1009	1	1	100.00
CONT_ASSIGN	1043	1	1	100.00
CONT_ASSIGN	1094	1	0	0.00
CONT_ASSIGN	1149	1	1	100.00
CONT_ASSIGN	1149	1	1	100.00
CONT_ASSIGN	1149	1	1	100.00
CONT_ASSIGN	1204	1	1	100.00
CONT_ASSIGN	1204	1	1	100.00
CONT_ASSIGN	1204	1	0	0.00
CONT_ASSIGN	1204	1	1	100.00
CONT_ASSIGN	1264	1	1	100.00
CONT_ASSIGN	1276	1	1	100.00
CONT_ASSIGN	1299	1	1	100.00
CONT_ASSIGN	1300	1	1	100.00
CONT_ASSIGN	1303	1	1	100.00
CONT_ASSIGN	1304	1	1	100.00
CONT_ASSIGN	1305	1	1	100.00
CONT_ASSIGN	1310	1	1	100.00
CONT_ASSIGN	1333	1	1	100.00
CONT_ASSIGN	1334	1	1	100.00
CONT_ASSIGN	1336	1	1	100.00
CONT_ASSIGN	1338	1	1	100.00
CONT_ASSIGN	1342	1	1	100.00
CONT_ASSIGN	1344	1	1	100.00
CONT_ASSIGN	1346	1	1	100.00
CONT_ASSIGN	1351	1	1	100.00
CONT_ASSIGN	1353	1	1	100.00
CONT_ASSIGN	1355	1	1	100.00
CONT_ASSIGN	1387	1	1	100.00
CONT_ASSIGN	1389	1	1	100.00
CONT_ASSIGN	1393	1	1	100.00
CONT_ASSIGN	1397	1	1	100.00
CONT_ASSIGN	1401	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_otp_ctrl_1.0/rtl/otp_ctrl.sv' or '../src/lowrisc_ip_otp_ctrl_1.0/rtl/otp_ctrl.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
234	8	8
264	1	1
265	1	1
266	1	1
267	1	1
268	1	1
269	1	1
272	0	1
			MISSING_ELSE
277	1	1
278	1	1
279	1	1
280	1	1
281	1	1
282	1	1
283	1	1
288	1	1
289	1	1
291	1	1
301	1	1
302	1	1
303	1	1
304	1	1
305	1	1
306	1	1
307	1	1
309	1	1
319	1	1
323	1	1
324	1	1
328	1	1
329	1	1
			MISSING_ELSE
331	1	1
332	1	1
			MISSING_ELSE
334	1	1
335	1	1
			MISSING_ELSE
338	1	1
339	1	1
			MISSING_ELSE
374	1	1
378	1	1
382	1	1
383	1	1
384	1	1
386	1	1
394	1	1
395	1	1
398	1	1
399	1	1
401	1	1
420	1	1
423	1	1
424	1	1
425	1	1
427	1	1
429	1	1
432	1	1
434	1	1
437	1	1
438	1	1
			MISSING_ELSE
442	1	1
444	1	1
448	1	1
451	1	1
453	1	1
458	1	1
459	1	1
			MISSING_ELSE
461	1	1
462	1	1
			MISSING_ELSE
467	1	1
474	1	1
487	1	1
495	1	1
498	1	1
499	1	1
500	1	1
501	1	1
502	1	1
504	1	1
505	1	1
506	1	1
507	1	1
549	1	1
557	1	1
604	1	1
606	1	1
729	1	1
730	1	1
731	1	1
761	1	1
763	1	1
840	1	1
841	1	1
898	1	1
899	1	1
925	1	1
926	1	1
927	1	1
928	1	1
952	1	1
955	1	1
956	1	1
958	1	1
1007	1	1
1009	1	1
1043	1	1
1094	0	1
1149	3	3
1204	3	4
1264	1	1
1276	1	1
1299	1	1
1300	1	1
1303	1	1
1304	1	1
1305	1	1
1310	1	1
1333	1	1
1334	1	1
1336	1	1
1338	1	1
1342	1	1
1344	1	1
1346	1	1
1351	1	1
1353	1	1
1355	1	1
1387	1	1
1389	1	1
1393	1	1
1397	1	1
1401	1	1

---

Cond Coverage for Instance : tb.dut

	Total	Covered	Percent
Conditions	105	93	88.57
Logical	105	93	88.57
Non-Logical	0	0
Event	0	0

 LINE       234
 EXPRESSION (({tlul_addr, 2'b0} >= 11'b0) & ({1'b0, {tlul_addr, 2'b0}} < gen_part_sel[0].PartEnd))
             --------------1-------------   --------------------------2--------------------------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       234
 EXPRESSION (({tlul_addr, 2'b0} >= 11'b00001000000) & ({1'b0, {tlul_addr, 2'b0}} < gen_part_sel[1].PartEnd))
             -------------------1------------------   --------------------------2--------------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T3,T6

 LINE       234
 EXPRESSION (({tlul_addr, 2'b0} >= 11'b01101100000) & ({1'b0, {tlul_addr, 2'b0}} < gen_part_sel[2].PartEnd))
             -------------------1------------------   --------------------------2--------------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T7,T12,T13
1	1	Covered	T1,T2,T3

 LINE       234
 EXPRESSION (({tlul_addr, 2'b0} >= 11'b11010000000) & ({1'b0, {tlul_addr, 2'b0}} < gen_part_sel[3].PartEnd))
             -------------------1------------------   --------------------------2--------------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T7,T12,T13
1	1	Covered	T7,T12,T13

 LINE       234
 EXPRESSION (({tlul_addr, 2'b0} >= 11'b11011010000) & ({1'b0, {tlul_addr, 2'b0}} < gen_part_sel[4].PartEnd))
             -------------------1------------------   --------------------------2--------------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T7,T12,T13
1	1	Covered	T7,T12,T13

 LINE       234
 EXPRESSION (({tlul_addr, 2'b0} >= 11'b11011111000) & ({1'b0, {tlul_addr, 2'b0}} < gen_part_sel[5].PartEnd))
             -------------------1------------------   --------------------------2--------------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T7,T12,T13
1	1	Covered	T7,T12,T13

 LINE       234
 EXPRESSION (({tlul_addr, 2'b0} >= 11'b11101010000) & ({1'b0, {tlul_addr, 2'b0}} < gen_part_sel[6].PartEnd))
             -------------------1------------------   --------------------------2--------------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T7,T12,T13
1	1	Covered	T7,T12,T13

 LINE       234
 EXPRESSION (({tlul_addr, 2'b0} >= 11'b11110101000) & ({1'b0, {tlul_addr, 2'b0}} < gen_part_sel[7].PartEnd))
             -------------------1------------------   --------------------------2--------------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T7,T12,T13

 LINE       268
 EXPRESSION (tlul_part_sel_oh != '0)
            ------------1-----------

-1-	Status	Tests
0	Not Covered
1	Covered	T1,T2,T3

 LINE       277
 EXPRESSION (((|part_tlul_gnt)) | tlul_oob_err_q)
             ---------1--------   -------2------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Not Covered
1	0	Covered	T1,T2,T3

 LINE       278
 EXPRESSION (((|part_tlul_rvalid)) | tlul_oob_err_q)
             ----------1----------   -------2------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Not Covered
1	0	Covered	T1,T2,T3

 LINE       374
 EXPRESSION (reg2hw.direct_access_cmd.digest.qe | reg2hw.direct_access_cmd.wr.qe | reg2hw.direct_access_cmd.rd.qe)
             -----------------1----------------   ---------------2--------------   ---------------3--------------

-1-	-2-	-3-	Status	Tests
0	0	0	Covered	T1,T2,T3
0	0	1	Not Covered
0	1	0	Not Covered
1	0	0	Not Covered

 LINE       394
 EXPRESSION (lci_prog_idle & dai_prog_idle)
             ------1------   ------2------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       425
 EXPRESSION (fatal_bus_integ_error_q | ((|intg_error)))
             -----------1-----------   -------2-------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T20,T21,T22
1	0	Not Covered

 LINE       434
 EXPRESSION (part_error[k] == MacroError)
            --------------1--------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Not Covered

 LINE       438
 EXPRESSION (part_error[k] == MacroEccUncorrError)
            -------------------1------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T37,T48,T58

 LINE       458
 EXPRESSION (fatal_macro_error_q || fatal_check_error_q)
             ---------1---------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T7,T107,T26
1	0	Covered	T9,T37,T48

 LINE       467
 EXPRESSION (chk_timeout | lfsr_fsm_err | scrmbl_fsm_err | ((|part_fsm_err)))
             -----1-----   ------2-----   -------3------   --------4--------

-1-	-2-	-3-	-4-	Status	Tests
0	0	0	0	Covered	T1,T2,T3
0	0	0	1	Covered	T9,T37,T48
0	0	1	0	Covered	T20,T21,T22
0	1	0	0	Covered	T20,T21,T22
1	0	0	0	Covered	T29,T95,T97

 LINE       557
 SUB-EXPRESSION (reg2hw.alert_test.recov_prim_otp_alert.q & reg2hw.alert_test.recov_prim_otp_alert.qe)
                 --------------------1-------------------   --------------------2--------------------

-1-	-2-	Status	Tests
0	1	Covered	T8,T209,T172
1	0	Covered	T1,T2,T3
1	1	Covered	T8,T209,T172

 LINE       557
 SUB-EXPRESSION (reg2hw.alert_test.fatal_prim_otp_alert.q & reg2hw.alert_test.fatal_prim_otp_alert.qe)
                 --------------------1-------------------   --------------------2--------------------

-1-	-2-	Status	Tests
0	1	Covered	T8,T209,T172
1	0	Covered	T1,T2,T3
1	1	Covered	T8,T209,T172

 LINE       557
 SUB-EXPRESSION (reg2hw.alert_test.fatal_bus_integ_error.q & reg2hw.alert_test.fatal_bus_integ_error.qe)
                 --------------------1--------------------   ---------------------2--------------------

-1-	-2-	Status	Tests
0	1	Covered	T8,T209,T172
1	0	Covered	T1,T2,T3
1	1	Covered	T8,T209,T172

 LINE       557
 SUB-EXPRESSION (reg2hw.alert_test.fatal_check_error.q & reg2hw.alert_test.fatal_check_error.qe)
                 ------------------1------------------   -------------------2------------------

-1-	-2-	Status	Tests
0	1	Covered	T8,T209,T172
1	0	Covered	T1,T2,T3
1	1	Covered	T8,T209,T172

 LINE       557
 SUB-EXPRESSION (reg2hw.alert_test.fatal_macro_error.q & reg2hw.alert_test.fatal_macro_error.qe)
                 ------------------1------------------   -------------------2------------------

-1-	-2-	Status	Tests
0	1	Covered	T8,T209,T172
1	0	Covered	T1,T2,T3
1	1	Covered	T8,T209,T172

 LINE       604
 EXPRESSION (reg2hw.check_trigger.integrity.q & reg2hw.check_trigger.integrity.qe)
             ----------------1---------------   ----------------2----------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       606
 EXPRESSION (reg2hw.check_trigger.consistency.q & reg2hw.check_trigger.consistency.qe)
             -----------------1----------------   -----------------2-----------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       729
 EXPRESSION (otp_prim_ready & otp_rsp_fifo_ready)
             -------1------   ---------2--------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       730
 EXPRESSION (otp_arb_valid & otp_rsp_fifo_ready)
             ------1------   ---------2--------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T3

 LINE       731
 EXPRESSION (otp_prim_ready & otp_prim_valid)
             -------1------   -------2------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       841
 EXPRESSION (otp_rvalid & otp_fifo_valid)
             -----1----   -------2------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T3

 LINE       1299
 EXPRESSION (part_init_done[HwCfgIdx] ? On : Off)
             ------------1-----------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       1303
 EXPRESSION (part_digest[Secret2Idx] != '0)
            ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T3,T6

 LINE       1333
 EXPRESSION (part_digest[Secret1Idx] != '0)
            ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       1351
 EXPRESSION ((part_digest[Secret0Idx] != '0) ? On : Off)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       1351
 SUB-EXPRESSION (part_digest[Secret0Idx] != '0)
                ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       1353
 EXPRESSION ((part_digest[Secret2Idx] != '0) ? On : Off)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T3,T6

 LINE       1353
 SUB-EXPRESSION (part_digest[Secret2Idx] != '0)
                ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T3,T6

 LINE       1355
 EXPRESSION ((part_digest[Secret2Idx] != '0) ? On : Off)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T3,T6

 LINE       1355
 SUB-EXPRESSION (part_digest[Secret2Idx] != '0)
                ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T3,T6

---

Toggle Coverage for Instance : tb.dut

	Total	Covered	Percent
Totals	141	134	95.04
Total Bits	9308	8984	96.52
Total Bits 0->1	4654	4492	96.52
Total Bits 1->0	4654	4492	96.52

Ports	141	134	95.04
Port Bits	9308	8984	96.52
Port Bits 0->1	4654	4492	96.52
Port Bits 1->0	4654	4492	96.52

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction	Exclude Annotation
clk_i	Yes	Yes	T16,T109,T110	Yes	T16,T109,T110	INPUT
rst_ni	Yes	Yes	T110,T115,T184	Yes	T16,T109,T110	INPUT
clk_edn_i	Yes	Yes	T16,T109,T110	Yes	T16,T109,T110	INPUT
rst_edn_ni	Yes	Yes	T110,T115,T184	Yes	T16,T109,T110	INPUT
edn_o.edn_req	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
edn_i.edn_bus[31:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
edn_i.edn_fips	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
edn_i.edn_ack	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
core_tl_i.d_ready	Yes	Yes	T109,T110,T114	Yes	T16,T109,T110	INPUT
core_tl_i.a_user.data_intg[6:0]	Yes	Yes	T16,T109,T110	Yes	T16,T109,T110	INPUT
core_tl_i.a_user.cmd_intg[6:0]	Yes	Yes	T16,T109,T110	Yes	T16,T109,T110	INPUT
core_tl_i.a_user.instr_type[3:0]	Yes	Yes	T110,T114,T111	Yes	T110,T114,T111	INPUT
core_tl_i.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		INPUT
core_tl_i.a_data[31:0]	Yes	Yes	T16,T109,T110	Yes	T16,T109,T110	INPUT
core_tl_i.a_mask[3:0]	Yes	Yes	T16,T109,T110	Yes	T110,T114,T111	INPUT
core_tl_i.a_address[31:0]	Yes	Yes	T110,T114,T111	Yes	T110,T114,T111	INPUT
core_tl_i.a_source[7:0]	Yes	Yes	T16,T109,T110	Yes	T16,T109,T110	INPUT
core_tl_i.a_size[1:0]	Yes	Yes	T110,T114,T111	Yes	T110,T114,T111	INPUT
core_tl_i.a_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
core_tl_i.a_opcode[2:0]	Yes	Yes	T16,T109,T110	Yes	T16,T109,T110	INPUT
core_tl_i.a_valid	Yes	Yes	T16,T109,T110	Yes	T16,T109,T110	INPUT
core_tl_o.a_ready	Yes	Yes	T16,T109,T110	Yes	T16,T109,T110	OUTPUT
core_tl_o.d_error	Yes	Yes	T110,T115,T184	Yes	T110,T115,T184	OUTPUT
core_tl_o.d_user.data_intg[6:0]	Yes	Yes	T16,T109,T110	Yes	T16,T109,T110	OUTPUT
core_tl_o.d_user.rsp_intg[5:0]	Yes	Yes	*T16,*T109,T110	Yes	T16,T109,T110	OUTPUT
core_tl_o.d_user.rsp_intg[6]	Unreachable	Unreachable		Unreachable		OUTPUT
core_tl_o.d_data[31:0]	Yes	Yes	T16,T109,T110	Yes	T16,T109,T110	OUTPUT
core_tl_o.d_sink	Unreachable	Unreachable		Unreachable		OUTPUT
core_tl_o.d_source[7:0]	Yes	Yes	T16,T109,T110	Yes	T16,T109,T110	OUTPUT
core_tl_o.d_size[1:0]	Yes	Yes	T110,T114,T111	Yes	T110,T114,T111	OUTPUT
core_tl_o.d_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
core_tl_o.d_opcode[0]	Yes	Yes	*T16,*T109,*T110	Yes	T16,T109,T110	OUTPUT
core_tl_o.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		OUTPUT
core_tl_o.d_valid	Yes	Yes	T16,T109,T110	Yes	T16,T109,T110	OUTPUT
prim_tl_i.d_ready	Yes	Yes	T109,T110,T114	Yes	T16,T109,T110	INPUT
prim_tl_i.a_user.data_intg[6:0]	Yes	Yes	T16,T109,T110	Yes	T16,T109,T110	INPUT
prim_tl_i.a_user.cmd_intg[6:0]	Yes	Yes	T16,T109,T110	Yes	T16,T109,T110	INPUT
prim_tl_i.a_user.instr_type[3:0]	Yes	Yes	T110,T112,T210	Yes	T110,T111,T182	INPUT
prim_tl_i.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		INPUT
prim_tl_i.a_data[31:0]	Yes	Yes	T16,T109,T110	Yes	T16,T109,T110	INPUT
prim_tl_i.a_mask[3:0]	Yes	Yes	T110,T114,T111	Yes	T110,T114,T182	INPUT
prim_tl_i.a_address[31:0]	Yes	Yes	T110,T114,T111	Yes	T110,T114,T115	INPUT
prim_tl_i.a_source[7:0]	Yes	Yes	T16,T109,T110	Yes	T16,T109,T110	INPUT
prim_tl_i.a_size[1:0]	Yes	Yes	T110,T114,T115	Yes	T110,T114,T115	INPUT
prim_tl_i.a_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
prim_tl_i.a_opcode[2:0]	Yes	Yes	T16,T109,T110	Yes	T16,T109,T110	INPUT
prim_tl_i.a_valid	Yes	Yes	T16,T109,T110	Yes	T16,T109,T110	INPUT
prim_tl_o.a_ready	Yes	Yes	T16,T109,T110	Yes	T16,T109,T110	OUTPUT
prim_tl_o.d_error	Yes	Yes	T16,T109,T110	Yes	T110,T115,T184	OUTPUT
prim_tl_o.d_user.data_intg[0]	Excluded	Excluded	*T16,*T109,*T110	Excluded	T16,T109,T110	OUTPUT	0->1:VC_COV_UNR / 1->0:VC_COV_UNR
prim_tl_o.d_user.data_intg[1]	Yes	Yes	*T16,*T109,*T110	Yes	T16,T109,T110	OUTPUT
prim_tl_o.d_user.data_intg[2]	Excluded	Excluded	*T16,*T109,*T110	Excluded	T16,T109,T110	OUTPUT	0->1:VC_COV_UNR / 1->0:VC_COV_UNR
prim_tl_o.d_user.data_intg[3]	Yes	Yes	*T16,*T109,*T110	Yes	T16,T109,T110	OUTPUT
prim_tl_o.d_user.data_intg[4]	Excluded	Excluded	*T16,*T109,*T110	Excluded	T16,T109,T110	OUTPUT	0->1:VC_COV_UNR / 1->0:VC_COV_UNR
prim_tl_o.d_user.data_intg[5]	Yes	Yes	*T16,*T109,*T110	Yes	T16,T109,T110	OUTPUT
prim_tl_o.d_user.data_intg[6]	Excluded	Excluded	T16,T109,T110	Excluded	T16,T109,T110	OUTPUT	0->1:VC_COV_UNR / 1->0:VC_COV_UNR
prim_tl_o.d_user.rsp_intg[5:0]	Excluded	Excluded	*T16,*T109,T110	Excluded	T16,T109,T110	OUTPUT	0->1:VC_COV_UNR / 1->0:VC_COV_UNR
prim_tl_o.d_user.rsp_intg[6]	Unreachable	Unreachable		Unreachable		OUTPUT
prim_tl_o.d_data[31:0]	Yes	Yes	T16,T109,T110	Yes	T16,T109,T110	OUTPUT
prim_tl_o.d_sink	Unreachable	Unreachable		Unreachable		OUTPUT
prim_tl_o.d_source[7:0]	Yes	Yes	T16,T109,T110	Yes	T16,T109,T110	OUTPUT
prim_tl_o.d_size[1:0]	Yes	Yes	T110,T114,T115	Yes	T110,T114,T115	OUTPUT
prim_tl_o.d_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
prim_tl_o.d_opcode[0]	Yes	Yes	*T16,*T109,*T110	Yes	T16,T109,T110	OUTPUT
prim_tl_o.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		OUTPUT
prim_tl_o.d_valid	Yes	Yes	T16,T109,T110	Yes	T16,T109,T110	OUTPUT
intr_otp_operation_done_o	Yes	Yes	T111,T112,T113	Yes	T111,T112,T113	OUTPUT
intr_otp_error_o	Yes	Yes	T111,T112,T113	Yes	T111,T112,T113	OUTPUT
alert_rx_i[0].ack_n	Yes	Yes	T16,T109,T110	Yes	T16,T109,T110	INPUT
alert_rx_i[0].ack_p	Yes	Yes	T16,T109,T110	Yes	T16,T109,T110	INPUT
alert_rx_i[0].ping_n	Unreachable	Unreachable		Unreachable		INPUT
alert_rx_i[0].ping_p	Unreachable	Unreachable		Unreachable		INPUT
alert_rx_i[1].ack_n	Yes	Yes	T16,T109,T110	Yes	T16,T109,T110	INPUT
alert_rx_i[1].ack_p	Yes	Yes	T16,T109,T183	Yes	T16,T109,T183	INPUT
alert_rx_i[1].ping_n	Unreachable	Unreachable		Unreachable		INPUT
alert_rx_i[1].ping_p	Unreachable	Unreachable		Unreachable		INPUT
alert_rx_i[2].ack_n	Yes	Yes	T16,T109,T110	Yes	T16,T109,T110	INPUT
alert_rx_i[2].ack_p	Yes	Yes	T16,T109,T110	Yes	T16,T109,T110	INPUT
alert_rx_i[2].ping_n	Unreachable	Unreachable		Unreachable		INPUT
alert_rx_i[2].ping_p	Unreachable	Unreachable		Unreachable		INPUT
alert_rx_i[3].ack_n	Yes	Yes	T16,T109,T110	Yes	T16,T109,T110	INPUT
alert_rx_i[3].ack_p	Yes	Yes	T16,T109,T110	Yes	T16,T109,T110	INPUT
alert_rx_i[3].ping_n	Unreachable	Unreachable		Unreachable		INPUT
alert_rx_i[3].ping_p	Unreachable	Unreachable		Unreachable		INPUT
alert_rx_i[4].ack_n	Yes	Yes	T16,T109,T110	Yes	T16,T109,T110	INPUT
alert_rx_i[4].ack_p	Yes	Yes	T16,T109,T114	Yes	T16,T109,T114	INPUT
alert_rx_i[4].ping_n	Unreachable	Unreachable		Unreachable		INPUT
alert_rx_i[4].ping_p	Unreachable	Unreachable		Unreachable		INPUT
alert_tx_o[0].alert_n	Yes	Yes	T16,T109,T110	Yes	T16,T109,T110	OUTPUT
alert_tx_o[0].alert_p	Yes	Yes	T16,T109,T110	Yes	T16,T109,T110	OUTPUT
alert_tx_o[1].alert_n	Yes	Yes	T16,T109,T110	Yes	T16,T109,T110	OUTPUT
alert_tx_o[1].alert_p	Yes	Yes	T16,T109,T183	Yes	T16,T109,T183	OUTPUT
alert_tx_o[2].alert_n	Yes	Yes	T16,T109,T110	Yes	T16,T109,T110	OUTPUT
alert_tx_o[2].alert_p	Yes	Yes	T16,T109,T110	Yes	T16,T109,T110	OUTPUT
alert_tx_o[3].alert_n	Yes	Yes	T16,T109,T110	Yes	T16,T109,T110	OUTPUT
alert_tx_o[3].alert_p	Yes	Yes	T16,T109,T110	Yes	T16,T109,T110	OUTPUT
alert_tx_o[4].alert_n	Yes	Yes	T16,T109,T110	Yes	T16,T109,T110	OUTPUT
alert_tx_o[4].alert_p	Yes	Yes	T16,T109,T114	Yes	T16,T109,T114	OUTPUT
obs_ctrl_i.obmen[3:0]	No	No		No		INPUT
obs_ctrl_i.obmsl[3:0]	No	No		No		INPUT
obs_ctrl_i.obgsl[3:0]	No	No		No		INPUT
otp_obs_o[7:0]	Unreachable	Unreachable		Unreachable		OUTPUT
otp_ast_pwr_seq_o.pwr_seq[1:0]	Excluded	Excluded		Excluded		OUTPUT	0->1:VC_COV_UNR / 1->0:VC_COV_UNR
otp_ast_pwr_seq_h_i.pwr_seq_h[1:0]	Yes	Yes	T115,T185,T211	Yes	T115,T185,T211	INPUT
pwr_otp_i.otp_init	Yes	Yes	T16,T109,T110	Yes	T16,T109,T110	INPUT
pwr_otp_o.otp_idle	Yes	Yes	T110,T115,T184	Yes	T16,T109,T110	OUTPUT
pwr_otp_o.otp_done	Yes	Yes	T110,T115,T184	Yes	T16,T109,T110	OUTPUT
lc_otp_vendor_test_i.ctrl[31:0]	No	No		No		INPUT
lc_otp_vendor_test_o.status[31:0]	Excluded	Excluded		Excluded		OUTPUT	0->1:VC_COV_UNR / 1->0:VC_COV_UNR
lc_otp_program_i.count[383:0]	Yes	Yes	T102,T212,T213	Yes	T121,T102,T212	INPUT
lc_otp_program_i.state[319:0]	Yes	Yes	T102,T213,T214	Yes	T102,T215,T216	INPUT
lc_otp_program_i.req	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
lc_otp_program_o.ack	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
lc_otp_program_o.err	Yes	Yes	T95,T121,T102	Yes	T95,T121,T102	OUTPUT
lc_creator_seed_sw_rw_en_i[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
lc_seed_hw_rd_en_i[3:0]	Yes	Yes	T115,T211,T217	Yes	T115,T211,T217	INPUT
lc_dft_en_i[3:0]	Yes	Yes	T110,T115,T185	Yes	T16,T110,T114	INPUT
lc_escalate_en_i[3:0]	Yes	Yes	T7,T107,T95	Yes	T7,T107,T95	INPUT
lc_check_byp_en_i[3:0]	Yes	Yes	T16,T109,T110	Yes	T16,T109,T110	INPUT
otp_lc_data_o.rma_token[127:0]	Yes	Yes	T11,T93,T95	Yes	T93,T95,T96	OUTPUT
otp_lc_data_o.rma_token_valid[3:0]	Yes	Yes	T2,T3,T6	Yes	T2,T3,T6	OUTPUT
otp_lc_data_o.test_exit_token[127:0]	Yes	Yes	T110,T115,T184	Yes	T16,T109,T110	OUTPUT
otp_lc_data_o.test_unlock_token[127:0]	Yes	Yes	T110,T115,T184	Yes	T16,T109,T110	OUTPUT
otp_lc_data_o.test_tokens_valid[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
otp_lc_data_o.secrets_valid[3:0]	Yes	Yes	T2,T3,T6	Yes	T2,T3,T6	OUTPUT
otp_lc_data_o.count[3:0]	Yes	Yes	*T16,*T109,*T110	Yes	T110,T115,T184	OUTPUT
otp_lc_data_o.count[4]	No	No		No		OUTPUT
otp_lc_data_o.count[8:5]	Yes	Yes	*T16,*T109,*T110	Yes	T110,T115,T184	OUTPUT
otp_lc_data_o.count[9]	No	No		No		OUTPUT
otp_lc_data_o.count[10]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	OUTPUT
otp_lc_data_o.count[11]	No	No		No		OUTPUT
otp_lc_data_o.count[15:12]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	OUTPUT
otp_lc_data_o.count[16]	No	No		No		OUTPUT
otp_lc_data_o.count[29:17]	Yes	Yes	*T16,*T109,*T110	Yes	T110,T115,T184	OUTPUT
otp_lc_data_o.count[32:30]	No	No		No		OUTPUT
otp_lc_data_o.count[41:33]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	OUTPUT
otp_lc_data_o.count[42]	No	No		No		OUTPUT
otp_lc_data_o.count[46:43]	Yes	Yes	*T16,*T109,*T110	Yes	T110,T115,T184	OUTPUT
otp_lc_data_o.count[47]	No	No		No		OUTPUT
otp_lc_data_o.count[54:48]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	OUTPUT
otp_lc_data_o.count[55]	No	No		No		OUTPUT
otp_lc_data_o.count[62:56]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	OUTPUT
otp_lc_data_o.count[65:63]	No	No		No		OUTPUT
otp_lc_data_o.count[76:66]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	OUTPUT
otp_lc_data_o.count[77]	No	No		No		OUTPUT
otp_lc_data_o.count[78]	Yes	Yes	*T16,*T109,*T110	Yes	T110,T115,T184	OUTPUT
otp_lc_data_o.count[79]	No	No		No		OUTPUT
otp_lc_data_o.count[84:80]	Yes	Yes	*T16,*T109,*T110	Yes	T110,T115,T184	OUTPUT
otp_lc_data_o.count[85]	No	No		No		OUTPUT
otp_lc_data_o.count[88:86]	Yes	Yes	*T16,*T109,*T110	Yes	T110,T115,T184	OUTPUT
otp_lc_data_o.count[89]	No	No		No		OUTPUT
otp_lc_data_o.count[101:90]	Yes	Yes	*T16,*T109,*T110	Yes	T110,T115,T184	OUTPUT
otp_lc_data_o.count[102]	No	No		No		OUTPUT
otp_lc_data_o.count[105:103]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	OUTPUT
otp_lc_data_o.count[106]	No	No		No		OUTPUT
otp_lc_data_o.count[118:107]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	OUTPUT
otp_lc_data_o.count[119]	No	No		No		OUTPUT
otp_lc_data_o.count[121:120]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
otp_lc_data_o.count[122]	No	No		No		OUTPUT
otp_lc_data_o.count[124:123]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	OUTPUT
otp_lc_data_o.count[125]	No	No		No		OUTPUT
otp_lc_data_o.count[137:126]	Yes	Yes	*T16,*T109,*T110	Yes	T110,T115,T184	OUTPUT
otp_lc_data_o.count[138]	No	No		No		OUTPUT
otp_lc_data_o.count[142:139]	Yes	Yes	*T16,*T109,*T110	Yes	T110,T115,T184	OUTPUT
otp_lc_data_o.count[143]	No	No		No		OUTPUT
otp_lc_data_o.count[147:144]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
otp_lc_data_o.count[148]	No	No		No		OUTPUT
otp_lc_data_o.count[158:149]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	OUTPUT
otp_lc_data_o.count[159]	No	No		No		OUTPUT
otp_lc_data_o.count[164:160]	Yes	Yes	*T16,*T109,*T110	Yes	T110,T115,T184	OUTPUT
otp_lc_data_o.count[165]	No	No		No		OUTPUT
otp_lc_data_o.count[171:166]	Yes	Yes	*T16,*T109,*T110	Yes	T110,T115,T184	OUTPUT
otp_lc_data_o.count[172]	No	No		No		OUTPUT
otp_lc_data_o.count[180:173]	Yes	Yes	*T16,*T109,*T110	Yes	T110,T115,T184	OUTPUT
otp_lc_data_o.count[181]	No	No		No		OUTPUT
otp_lc_data_o.count[185:182]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	OUTPUT
otp_lc_data_o.count[187:186]	No	No		No		OUTPUT
otp_lc_data_o.count[191:188]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	OUTPUT
otp_lc_data_o.count[192]	No	No		No		OUTPUT
otp_lc_data_o.count[193]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	OUTPUT
otp_lc_data_o.count[195:194]	No	No		No		OUTPUT
otp_lc_data_o.count[202:196]	Yes	Yes	*T16,*T109,*T110	Yes	T110,T115,T184	OUTPUT
otp_lc_data_o.count[203]	No	No		No		OUTPUT
otp_lc_data_o.count[215:204]	Yes	Yes	*T16,*T109,*T110	Yes	T110,T115,T184	OUTPUT
otp_lc_data_o.count[216]	No	No		No		OUTPUT
otp_lc_data_o.count[217]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	OUTPUT
otp_lc_data_o.count[218]	No	No		No		OUTPUT
otp_lc_data_o.count[225:219]	Yes	Yes	*T16,*T109,*T110	Yes	T110,T115,T184	OUTPUT
otp_lc_data_o.count[227:226]	No	No		No		OUTPUT
otp_lc_data_o.count[228]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	OUTPUT
otp_lc_data_o.count[229]	No	No		No		OUTPUT
otp_lc_data_o.count[237:230]	Yes	Yes	*T16,*T109,*T110	Yes	T110,T115,T184	OUTPUT
otp_lc_data_o.count[238]	No	No		No		OUTPUT
otp_lc_data_o.count[240:239]	Yes	Yes	*T16,*T109,*T110	Yes	T110,T115,T184	OUTPUT
otp_lc_data_o.count[241]	No	No		No		OUTPUT
otp_lc_data_o.count[243:242]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	OUTPUT
otp_lc_data_o.count[245:244]	No	No		No		OUTPUT
otp_lc_data_o.count[269:246]	Yes	Yes	*T16,*T109,*T110	Yes	T110,T115,T184	OUTPUT
otp_lc_data_o.count[270]	No	No		No		OUTPUT
otp_lc_data_o.count[292:271]	Yes	Yes	*T16,*T109,*T110	Yes	T110,T115,T184	OUTPUT
otp_lc_data_o.count[293]	No	No		No		OUTPUT
otp_lc_data_o.count[303:294]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	OUTPUT
otp_lc_data_o.count[304]	No	No		No		OUTPUT
otp_lc_data_o.count[312:305]	Yes	Yes	*T16,*T109,*T110	Yes	T110,T115,T184	OUTPUT
otp_lc_data_o.count[313]	No	No		No		OUTPUT
otp_lc_data_o.count[324:314]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	OUTPUT
otp_lc_data_o.count[325]	No	No		No		OUTPUT
otp_lc_data_o.count[327:326]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	OUTPUT
otp_lc_data_o.count[328]	No	No		No		OUTPUT
otp_lc_data_o.count[330:329]	Yes	Yes	*T16,*T109,*T110	Yes	T110,T115,T184	OUTPUT
otp_lc_data_o.count[331]	No	No		No		OUTPUT
otp_lc_data_o.count[343:332]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	OUTPUT
otp_lc_data_o.count[344]	No	No		No		OUTPUT
otp_lc_data_o.count[345]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	OUTPUT
otp_lc_data_o.count[346]	No	No		No		OUTPUT
otp_lc_data_o.count[357:347]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	OUTPUT
otp_lc_data_o.count[358]	No	No		No		OUTPUT
otp_lc_data_o.count[364:359]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	OUTPUT
otp_lc_data_o.count[365]	No	No		No		OUTPUT
otp_lc_data_o.count[366]	Yes	Yes	*T16,*T109,*T110	Yes	T110,T115,T184	OUTPUT
otp_lc_data_o.count[367]	No	No		No		OUTPUT
otp_lc_data_o.count[383:368]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
otp_lc_data_o.state[5:0]	Yes	Yes	*T16,*T109,*T110	Yes	T110,T115,T184	OUTPUT
otp_lc_data_o.state[6]	No	No		No		OUTPUT
otp_lc_data_o.state[12:7]	Yes	Yes	*T16,*T109,*T110	Yes	T110,T115,T184	OUTPUT
otp_lc_data_o.state[13]	No	No		No		OUTPUT
otp_lc_data_o.state[14]	Yes	Yes	*T16,*T109,*T110	Yes	T110,T115,T184	OUTPUT
otp_lc_data_o.state[16:15]	No	No		No		OUTPUT
otp_lc_data_o.state[17]	Yes	Yes	*T16,*T109,*T110	Yes	T110,T115,T184	OUTPUT
otp_lc_data_o.state[20:18]	No	No		No		OUTPUT
otp_lc_data_o.state[21]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	OUTPUT
otp_lc_data_o.state[22]	No	No		No		OUTPUT
otp_lc_data_o.state[31:23]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	OUTPUT
otp_lc_data_o.state[32]	No	No		No		OUTPUT
otp_lc_data_o.state[34:33]	Yes	Yes	*T16,*T109,*T110	Yes	T110,T115,T184	OUTPUT
otp_lc_data_o.state[37:35]	No	No		No		OUTPUT
otp_lc_data_o.state[46:38]	Yes	Yes	*T16,*T109,*T110	Yes	T110,T115,T184	OUTPUT
otp_lc_data_o.state[47]	No	No		No		OUTPUT
otp_lc_data_o.state[50:48]	Yes	Yes	*T16,*T109,*T110	Yes	T110,T115,T184	OUTPUT
otp_lc_data_o.state[51]	No	No		No		OUTPUT
otp_lc_data_o.state[52]	Yes	Yes	*T16,*T109,*T110	Yes	T110,T115,T184	OUTPUT
otp_lc_data_o.state[53]	No	No		No		OUTPUT
otp_lc_data_o.state[59:54]	Yes	Yes	*T16,*T109,*T110	Yes	T110,T115,T184	OUTPUT
otp_lc_data_o.state[60]	No	No		No		OUTPUT
otp_lc_data_o.state[61]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	OUTPUT
otp_lc_data_o.state[62]	No	No		No		OUTPUT
otp_lc_data_o.state[73:63]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	OUTPUT
otp_lc_data_o.state[74]	No	No		No		OUTPUT
otp_lc_data_o.state[83:75]	Yes	Yes	*T16,*T109,*T110	Yes	T110,T115,T184	OUTPUT
otp_lc_data_o.state[84]	No	No		No		OUTPUT
otp_lc_data_o.state[87:85]	Yes	Yes	*T16,*T109,*T110	Yes	T110,T115,T184	OUTPUT
otp_lc_data_o.state[88]	No	No		No		OUTPUT
otp_lc_data_o.state[101:89]	Yes	Yes	*T16,*T109,*T110	Yes	T110,T115,T184	OUTPUT
otp_lc_data_o.state[102]	No	No		No		OUTPUT
otp_lc_data_o.state[103]	Yes	Yes	*T16,*T109,*T110	Yes	T110,T115,T184	OUTPUT
otp_lc_data_o.state[104]	No	No		No		OUTPUT
otp_lc_data_o.state[105]	Yes	Yes	*T16,*T109,*T110	Yes	T110,T115,T184	OUTPUT
otp_lc_data_o.state[107:106]	No	No		No		OUTPUT
otp_lc_data_o.state[113:108]	Yes	Yes	*T16,*T109,*T110	Yes	T110,T115,T184	OUTPUT
otp_lc_data_o.state[115:114]	No	No		No		OUTPUT
otp_lc_data_o.state[121:116]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	OUTPUT
otp_lc_data_o.state[122]	No	No		No		OUTPUT
otp_lc_data_o.state[126:123]	Yes	Yes	*T16,*T109,*T110	Yes	T110,T115,T184	OUTPUT
otp_lc_data_o.state[127]	No	No		No		OUTPUT
otp_lc_data_o.state[136:128]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	OUTPUT
otp_lc_data_o.state[137]	No	No		No		OUTPUT
otp_lc_data_o.state[145:138]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	OUTPUT
otp_lc_data_o.state[147:146]	No	No		No		OUTPUT
otp_lc_data_o.state[152:148]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	OUTPUT
otp_lc_data_o.state[154:153]	No	No		No		OUTPUT
otp_lc_data_o.state[156:155]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	OUTPUT
otp_lc_data_o.state[158:157]	No	No		No		OUTPUT
otp_lc_data_o.state[160:159]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
otp_lc_data_o.state[161]	No	No		No		OUTPUT
otp_lc_data_o.state[163:162]	Yes	Yes	*T16,*T109,*T110	Yes	T110,T115,T184	OUTPUT
otp_lc_data_o.state[165:164]	No	No		No		OUTPUT
otp_lc_data_o.state[177:166]	Yes	Yes	*T16,*T109,*T110	Yes	T110,T115,T184	OUTPUT
otp_lc_data_o.state[178]	No	No		No		OUTPUT
otp_lc_data_o.state[180:179]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
otp_lc_data_o.state[181]	No	No		No		OUTPUT
otp_lc_data_o.state[182]	Yes	Yes	*T16,*T109,*T110	Yes	T110,T115,T184	OUTPUT
otp_lc_data_o.state[183]	No	No		No		OUTPUT
otp_lc_data_o.state[198:184]	Yes	Yes	*T16,*T109,*T110	Yes	T110,T115,T184	OUTPUT
otp_lc_data_o.state[199]	No	No		No		OUTPUT
otp_lc_data_o.state[206:200]	Yes	Yes	*T16,*T109,*T110	Yes	T110,T115,T184	OUTPUT
otp_lc_data_o.state[207]	No	No		No		OUTPUT
otp_lc_data_o.state[210:208]	Yes	Yes	T16,T109,T110	Yes	T110,T115,T184	OUTPUT
otp_lc_data_o.state[211]	No	No		No		OUTPUT
otp_lc_data_o.state[214:212]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	OUTPUT
otp_lc_data_o.state[215]	No	No		No		OUTPUT
otp_lc_data_o.state[217:216]	Yes	Yes	*T16,*T109,*T110	Yes	T110,T115,T184	OUTPUT
otp_lc_data_o.state[218]	No	No		No		OUTPUT
otp_lc_data_o.state[219]	Yes	Yes	*T1,*T3,*T6	Yes	T1,T3,T6	OUTPUT
otp_lc_data_o.state[221:220]	No	No		No		OUTPUT
otp_lc_data_o.state[230:222]	Yes	Yes	*T16,*T109,*T110	Yes	T110,T115,T184	OUTPUT
otp_lc_data_o.state[231]	No	No		No		OUTPUT
otp_lc_data_o.state[234:232]	Yes	Yes	T1,T3,T6	Yes	T1,T3,T6	OUTPUT
otp_lc_data_o.state[235]	No	No		No		OUTPUT
otp_lc_data_o.state[239:236]	Yes	Yes	*T16,*T109,*T110	Yes	T110,T115,T184	OUTPUT
otp_lc_data_o.state[240]	No	No		No		OUTPUT
otp_lc_data_o.state[243:241]	Yes	Yes	T16,T109,T110	Yes	T110,T115,T184	OUTPUT
otp_lc_data_o.state[244]	No	No		No		OUTPUT
otp_lc_data_o.state[246:245]	Yes	Yes	T1,T3,T6	Yes	T1,T3,T6	OUTPUT
otp_lc_data_o.state[247]	No	No		No		OUTPUT
otp_lc_data_o.state[263:248]	Yes	Yes	*T1,*T3,*T6	Yes	T1,T3,T6	OUTPUT
otp_lc_data_o.state[264]	No	No		No		OUTPUT
otp_lc_data_o.state[268:265]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	OUTPUT
otp_lc_data_o.state[269]	No	No		No		OUTPUT
otp_lc_data_o.state[273:270]	Yes	Yes	*T1,*T3,*T6	Yes	T1,T3,T6	OUTPUT
otp_lc_data_o.state[274]	No	No		No		OUTPUT
otp_lc_data_o.state[278:275]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	OUTPUT
otp_lc_data_o.state[280:279]	No	No		No		OUTPUT
otp_lc_data_o.state[294:281]	Yes	Yes	*T1,*T3,*T6	Yes	T1,T3,T6	OUTPUT
otp_lc_data_o.state[295]	No	No		No		OUTPUT
otp_lc_data_o.state[301:296]	Yes	Yes	*T16,*T109,*T110	Yes	T110,T115,T184	OUTPUT
otp_lc_data_o.state[302]	No	No		No		OUTPUT
otp_lc_data_o.state[306:303]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
otp_lc_data_o.state[307]	No	No		No		OUTPUT
otp_lc_data_o.state[319:308]	Yes	Yes	T16,T109,T110	Yes	T110,T115,T184	OUTPUT
otp_lc_data_o.error	Yes	Yes	T7,T9,T37	Yes	T7,T9,T37	OUTPUT
otp_lc_data_o.valid	Yes	Yes	T110,T115,T184	Yes	T16,T109,T110	OUTPUT
otp_keymgr_key_o.key_share1[255:0]	Yes	Yes	T6,T95,T98	Yes	T6,T95,T98	OUTPUT
otp_keymgr_key_o.key_share0[255:0]	Yes	Yes	T115,T184,T211	Yes	T111,T181,T115	OUTPUT
otp_keymgr_key_o.valid	Yes	Yes	T2,T3,T6	Yes	T2,T3,T6	OUTPUT
flash_otp_key_i.addr_req	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
flash_otp_key_i.data_req	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
flash_otp_key_o.seed_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
flash_otp_key_o.rand_key[127:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
flash_otp_key_o.key[127:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
flash_otp_key_o.addr_ack	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
flash_otp_key_o.data_ack	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
sram_otp_key_i[0].req	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
sram_otp_key_i[1].req	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
sram_otp_key_i[2].req	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
sram_otp_key_o[0].seed_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
sram_otp_key_o[0].nonce[127:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
sram_otp_key_o[0].key[127:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
sram_otp_key_o[0].ack	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
sram_otp_key_o[1].seed_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
sram_otp_key_o[1].nonce[127:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
sram_otp_key_o[1].key[127:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
sram_otp_key_o[1].ack	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
sram_otp_key_o[2].seed_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
sram_otp_key_o[2].nonce[127:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
sram_otp_key_o[2].key[127:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
sram_otp_key_o[2].ack	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
otbn_otp_key_i.req	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
otbn_otp_key_o.seed_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
otbn_otp_key_o.nonce[63:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
otbn_otp_key_o.key[127:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
otbn_otp_key_o.ack	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
otp_hw_cfg_o.data.device_id[255:0]	Yes	Yes	T218,T101,T137	Yes	T108,T218,T101	OUTPUT
otp_hw_cfg_o.data.manuf_state[255:0]	Yes	Yes	T16,T109,T110	Yes	T110,T115,T184	OUTPUT
otp_hw_cfg_o.data.en_sram_ifetch[7:0]	Yes	Yes	T16,T109,T110	Yes	T110,T115,T184	OUTPUT
otp_hw_cfg_o.data.en_csrng_sw_app_read[7:0]	Yes	Yes	T16,T109,T110	Yes	T110,T115,T184	OUTPUT
otp_hw_cfg_o.data.en_entropy_src_fw_read[7:0]	Yes	Yes	T16,T109,T110	Yes	T110,T115,T184	OUTPUT
otp_hw_cfg_o.data.en_entropy_src_fw_over[7:0]	Yes	Yes	T16,T109,T110	Yes	T110,T115,T184	OUTPUT
otp_hw_cfg_o.data.unallocated[31:0]	Yes	Yes	T95,T98,T102	Yes	T108,T95,T98	OUTPUT
otp_hw_cfg_o.data.hw_cfg_digest[63:0]	Yes	Yes	T16,T109,T110	Yes	T110,T115,T184	OUTPUT
otp_hw_cfg_o.valid[3:0]	Yes	Yes	T110,T115,T184	Yes	T16,T109,T110	OUTPUT
otp_ext_voltage_h_io	No	No		No		INOUT
scan_en_i	Yes	Yes	T115,T211,T186	Yes	T110,T115,T185	INPUT
scan_rst_ni	Yes	Yes	T115,T185,T211	Yes	T110,T115,T184	INPUT
scanmode_i[3:0]	Yes	Yes	T115,T211,T117	Yes	T115,T184,T185	INPUT
cio_test_o[7:0]	Excluded	Excluded		Excluded		OUTPUT	0->1:VC_COV_UNR / 1->0:VC_COV_UNR
cio_test_en_o[7:0]	Yes	Yes	T110,T115,T184	Yes	T16,T109,T110	OUTPUT

*Tests covering at least one bit in the range

---

Branch Coverage for Instance : tb.dut

	Line No.	Total	Covered	Percent
Branches		33	32	96.97
TERNARY	1299	2	2	100.00
TERNARY	1351	2	2	100.00
TERNARY	1353	2	2	100.00
TERNARY	1355	2	2	100.00
IF	267	3	2	66.67
IF	288	2	2	100.00
IF	328	2	2	100.00
IF	331	2	2	100.00
IF	334	2	2	100.00
IF	338	2	2	100.00
IF	398	2	2	100.00
IF	437	2	2	100.00
IF	458	2	2	100.00
IF	461	2	2	100.00
IF	498	2	2	100.00
IF	955	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_otp_ctrl_1.0/rtl/otp_ctrl.sv' or '../src/lowrisc_ip_otp_ctrl_1.0/rtl/otp_ctrl.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	1299	(part_init_done[HwCfgIdx]) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	1351	((part_digest[Secret0Idx] != '0)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	1353	((part_digest[Secret2Idx] != '0)) ? 

Branches:

-1-	Status	Tests
1	Covered	T2,T3,T6
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	1355	((part_digest[Secret2Idx] != '0)) ? 

Branches:

-1-	Status	Tests
1	Covered	T2,T3,T6
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	267	if (tlul_req)
-2-:	268	if ((tlul_part_sel_oh != '0))

Branches:

-1-	-2-	Status	Tests
1	1	Covered	T1,T2,T3
1	0	Not Covered
0	-	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	288	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	328	if ((!reg2hw.vendor_test_read_lock))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	331	if ((!reg2hw.creator_sw_cfg_read_lock))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	334	if ((!reg2hw.owner_sw_cfg_read_lock))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	338	if (lc_ctrl_pkg::lc_tx_test_false_loose(lc_creator_seed_sw_rw_en))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	398	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	437	if (otp_ctrl_part_pkg::PartInfo[k].ecc_fatal)

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	458	if ((fatal_macro_error_q || fatal_check_error_q))

Branches:

-1-	Status	Tests
1	Covered	T7,T9,T37
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	461	if (lc_ctrl_pkg::lc_tx_test_true_strict(lc_escalate_en[k]))

Branches:

-1-	Status	Tests
1	Covered	T7,T9,T37
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	498	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	955	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	64	64	100.00	64	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	64	64	100.00	64	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AlertTxKnown_A	2147483647	2147483647	0	0
CoreTlOutKnown_A	2147483647	2147483647	0	0
CreatorRootKeyShare0Size_A	1157	1157	0	0
CreatorRootKeyShare1Size_A	1157	1157	0	0
ErrorCodeWidth_A	1157	1157	0	0
FlashAddrKeySeedSize_A	1157	1157	0	0
FlashDataKeySeedSize_A	1157	1157	0	0
FlashOtpKeyRspKnown_A	2147483647	2147483647	0	0
FpvSecCmCntCnstyCheck_A	2147483647	50	0	0
FpvSecCmCntDaiCheck_A	2147483647	50	0	0
FpvSecCmCntIntegCheck_A	2147483647	50	0	0
FpvSecCmCntKdiEntropyCheck_A	2147483647	50	0	0
FpvSecCmCntKdiSeedCheck_A	2147483647	50	0	0
FpvSecCmCntLciCheck_A	2147483647	50	0	0
FpvSecCmCntScrmblCheck_A	2147483647	50	0	0
FpvSecCmCtrlDaiFsmCheck_A	2147483647	50	0	0
FpvSecCmCtrlKdiFsmCheck_A	2147483647	50	0	0
FpvSecCmCtrlLciFsmCheck_A	2147483647	50	0	0
FpvSecCmCtrlLfsrTimerFsmCheck_A	2147483647	50	0	0
FpvSecCmCtrlScrambleFsmCheck_A	2147483647	50	0	0
FpvSecCmDoubleLfsrCheck_A	2147483647	50	0	0
FpvSecCmRegWeOnehotCheck_A	2147483647	50	0	0
FpvSecCmTlLcGateFsm_A	2147483647	50	0	0
IntrOtpErrorKnown_A	2147483647	2147483647	0	0
IntrOtpOperationDoneKnown_A	2147483647	2147483647	0	0
LcOtpProgramRspKnown_A	2147483647	2147483647	0	0
LcSeedHwRdEnStable_A	2147483647	2276	0	0
LcStateSize_A	1157	1157	0	0
LcTransitionCntSize_A	1157	1157	0	0
OtpAstPwrSeqKnown_A	2147483647	2147483647	0	0
OtpErrorCode0_A	1157	1157	0	0
OtpErrorCode1_A	1157	1157	0	0
OtpErrorCode2_A	1157	1157	0	0
OtpErrorCode3_A	1157	1157	0	0
OtpErrorCode4_A	1157	1157	0	0
OtpHwCfgKnown_A	2147483647	2147483647	0	0
OtpIfWidth_A	1157	1157	0	0
OtpKeymgrKeyKnown_A	2147483647	2147483647	0	0
OtpLcDataKnown_A	2147483647	2147483647	0	0
OtpOtgnKeyKnown_A	2147483647	2147483647	0	0
OtpRespFifoUnderflow_A	2147483647	1341882	0	0
OtpSramKeyKnown_A	2147483647	2147483647	0	0
PartSelMustBeOnehot_A	2147483647	2147483647	0	0
PrimTlOutKnown_A	2147483647	2147483647	0	0
PwrOtpInitRspKnown_A	2147483647	2147483647	0	0
RmaTokenSize_A	1157	1157	0	0
SramDataKeySeedSize_A	1157	1157	0	0
TestExitTokenSize_A	1157	1157	0	0
TestUnlockTokenSize_A	1157	1157	0	0
gen_partitions[0].gen_unbuffered.FpvSecCmCtrlPartUnbufFsmCheck_A	2147483647	50	0	0
gen_partitions[1].gen_unbuffered.FpvSecCmCtrlPartUnbufFsmCheck_A	2147483647	50	0	0
gen_partitions[2].gen_unbuffered.FpvSecCmCtrlPartUnbufFsmCheck_A	2147483647	50	0	0
gen_partitions[3].gen_buffered.FpvSecCmCntPartBufCheck_A	2147483647	50	0	0
gen_partitions[3].gen_buffered.FpvSecCmCtrlPartBufFsmCheck_A	2147483647	50	0	0
gen_partitions[4].gen_buffered.FpvSecCmCntPartBufCheck_A	2147483647	50	0	0
gen_partitions[4].gen_buffered.FpvSecCmCtrlPartBufFsmCheck_A	2147483647	50	0	0
gen_partitions[5].gen_buffered.FpvSecCmCntPartBufCheck_A	2147483647	50	0	0
gen_partitions[5].gen_buffered.FpvSecCmCtrlPartBufFsmCheck_A	2147483647	50	0	0
gen_partitions[6].gen_buffered.FpvSecCmCntPartBufCheck_A	2147483647	50	0	0
gen_partitions[6].gen_buffered.FpvSecCmCtrlPartBufFsmCheck_A	2147483647	50	0	0
gen_partitions[7].gen_lifecycle.FpvSecCmCntPartLcCheck_A	2147483647	50	0	0
gen_partitions[7].gen_lifecycle.FpvSecCmCtrlPartLcFsmCheck_A	2147483647	50	0	0
gen_reg_we_assert_generic.FpvSecCmPrimFsmCheck_A	2147483647	50	0	0
gen_reg_we_assert_generic.FpvSecCmPrimRegWeOnehotCheck_A	2147483647	50	0	0

AlertTxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	73436	72051	0	0
T2	38018	37309	0	0
T3	110228	108967	0	0
T5	7499	6741	0	0
T6	50788	49798	0	0
T7	111091	111090	0	0
T8	8171	8083	0	0
T9	19415	19147	0	0
T10	10832	10630	0	0
T11	12755	12519	0	0

CoreTlOutKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	73436	72051	0	0
T2	38018	37309	0	0
T3	110228	108967	0	0
T5	7499	6741	0	0
T6	50788	49798	0	0
T7	111091	111090	0	0
T8	8171	8083	0	0
T9	19415	19147	0	0
T10	10832	10630	0	0
T11	12755	12519	0	0

CreatorRootKeyShare0Size_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1157	1157	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0

CreatorRootKeyShare1Size_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1157	1157	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0

ErrorCodeWidth_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1157	1157	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0

FlashAddrKeySeedSize_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1157	1157	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0

FlashDataKeySeedSize_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1157	1157	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0

FlashOtpKeyRspKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	73436	72051	0	0
T2	38018	37309	0	0
T3	110228	108967	0	0
T5	7499	6741	0	0
T6	50788	49798	0	0
T7	111091	111090	0	0
T8	8171	8083	0	0
T9	19415	19147	0	0
T10	10832	10630	0	0
T11	12755	12519	0	0

FpvSecCmCntCnstyCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	50	0	0
T20	850632	10	0	0
T21	866086	10	0	0
T22	849475	10	0	0
T51	15976	0	0	0
T171	15714	0	0	0
T219	0	10	0	0
T220	0	10	0	0
T221	13660	0	0	0
T222	15281	0	0	0
T223	18644	0	0	0
T224	16459	0	0	0
T225	18030	0	0	0

FpvSecCmCntDaiCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	50	0	0
T20	850632	10	0	0
T21	866086	10	0	0
T22	849475	10	0	0
T51	15976	0	0	0
T171	15714	0	0	0
T219	0	10	0	0
T220	0	10	0	0
T221	13660	0	0	0
T222	15281	0	0	0
T223	18644	0	0	0
T224	16459	0	0	0
T225	18030	0	0	0

FpvSecCmCntIntegCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	50	0	0
T20	850632	10	0	0
T21	866086	10	0	0
T22	849475	10	0	0
T51	15976	0	0	0
T171	15714	0	0	0
T219	0	10	0	0
T220	0	10	0	0
T221	13660	0	0	0
T222	15281	0	0	0
T223	18644	0	0	0
T224	16459	0	0	0
T225	18030	0	0	0

FpvSecCmCntKdiEntropyCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	50	0	0
T20	850632	10	0	0
T21	866086	10	0	0
T22	849475	10	0	0
T51	15976	0	0	0
T171	15714	0	0	0
T219	0	10	0	0
T220	0	10	0	0
T221	13660	0	0	0
T222	15281	0	0	0
T223	18644	0	0	0
T224	16459	0	0	0
T225	18030	0	0	0

FpvSecCmCntKdiSeedCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	50	0	0
T20	850632	10	0	0
T21	866086	10	0	0
T22	849475	10	0	0
T51	15976	0	0	0
T171	15714	0	0	0
T219	0	10	0	0
T220	0	10	0	0
T221	13660	0	0	0
T222	15281	0	0	0
T223	18644	0	0	0
T224	16459	0	0	0
T225	18030	0	0	0

FpvSecCmCntLciCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	50	0	0
T20	850632	10	0	0
T21	866086	10	0	0
T22	849475	10	0	0
T51	15976	0	0	0
T171	15714	0	0	0
T219	0	10	0	0
T220	0	10	0	0
T221	13660	0	0	0
T222	15281	0	0	0
T223	18644	0	0	0
T224	16459	0	0	0
T225	18030	0	0	0

FpvSecCmCntScrmblCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	50	0	0
T20	850632	10	0	0
T21	866086	10	0	0
T22	849475	10	0	0
T51	15976	0	0	0
T171	15714	0	0	0
T219	0	10	0	0
T220	0	10	0	0
T221	13660	0	0	0
T222	15281	0	0	0
T223	18644	0	0	0
T224	16459	0	0	0
T225	18030	0	0	0

FpvSecCmCtrlDaiFsmCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	50	0	0
T20	850632	10	0	0
T21	866086	10	0	0
T22	849475	10	0	0
T51	15976	0	0	0
T171	15714	0	0	0
T219	0	10	0	0
T220	0	10	0	0
T221	13660	0	0	0
T222	15281	0	0	0
T223	18644	0	0	0
T224	16459	0	0	0
T225	18030	0	0	0

FpvSecCmCtrlKdiFsmCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	50	0	0
T20	850632	10	0	0
T21	866086	10	0	0
T22	849475	10	0	0
T51	15976	0	0	0
T171	15714	0	0	0
T219	0	10	0	0
T220	0	10	0	0
T221	13660	0	0	0
T222	15281	0	0	0
T223	18644	0	0	0
T224	16459	0	0	0
T225	18030	0	0	0

FpvSecCmCtrlLciFsmCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	50	0	0
T20	850632	10	0	0
T21	866086	10	0	0
T22	849475	10	0	0
T51	15976	0	0	0
T171	15714	0	0	0
T219	0	10	0	0
T220	0	10	0	0
T221	13660	0	0	0
T222	15281	0	0	0
T223	18644	0	0	0
T224	16459	0	0	0
T225	18030	0	0	0

FpvSecCmCtrlLfsrTimerFsmCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	50	0	0
T20	850632	10	0	0
T21	866086	10	0	0
T22	849475	10	0	0
T51	15976	0	0	0
T171	15714	0	0	0
T219	0	10	0	0
T220	0	10	0	0
T221	13660	0	0	0
T222	15281	0	0	0
T223	18644	0	0	0
T224	16459	0	0	0
T225	18030	0	0	0

FpvSecCmCtrlScrambleFsmCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	50	0	0
T20	850632	10	0	0
T21	866086	10	0	0
T22	849475	10	0	0
T51	15976	0	0	0
T171	15714	0	0	0
T219	0	10	0	0
T220	0	10	0	0
T221	13660	0	0	0
T222	15281	0	0	0
T223	18644	0	0	0
T224	16459	0	0	0
T225	18030	0	0	0

FpvSecCmDoubleLfsrCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	50	0	0
T20	850632	10	0	0
T21	866086	10	0	0
T22	849475	10	0	0
T51	15976	0	0	0
T171	15714	0	0	0
T219	0	10	0	0
T220	0	10	0	0
T221	13660	0	0	0
T222	15281	0	0	0
T223	18644	0	0	0
T224	16459	0	0	0
T225	18030	0	0	0

FpvSecCmRegWeOnehotCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	50	0	0
T20	850632	10	0	0
T21	866086	10	0	0
T22	849475	10	0	0
T51	15976	0	0	0
T171	15714	0	0	0
T219	0	10	0	0
T220	0	10	0	0
T221	13660	0	0	0
T222	15281	0	0	0
T223	18644	0	0	0
T224	16459	0	0	0
T225	18030	0	0	0

FpvSecCmTlLcGateFsm_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	50	0	0
T20	850632	10	0	0
T21	866086	10	0	0
T22	849475	10	0	0
T51	15976	0	0	0
T171	15714	0	0	0
T219	0	10	0	0
T220	0	10	0	0
T221	13660	0	0	0
T222	15281	0	0	0
T223	18644	0	0	0
T224	16459	0	0	0
T225	18030	0	0	0

IntrOtpErrorKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	73436	72051	0	0
T2	38018	37309	0	0
T3	110228	108967	0	0
T5	7499	6741	0	0
T6	50788	49798	0	0
T7	111091	111090	0	0
T8	8171	8083	0	0
T9	19415	19147	0	0
T10	10832	10630	0	0
T11	12755	12519	0	0

IntrOtpOperationDoneKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	73436	72051	0	0
T2	38018	37309	0	0
T3	110228	108967	0	0
T5	7499	6741	0	0
T6	50788	49798	0	0
T7	111091	111090	0	0
T8	8171	8083	0	0
T9	19415	19147	0	0
T10	10832	10630	0	0
T11	12755	12519	0	0

LcOtpProgramRspKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	73436	72051	0	0
T2	38018	37309	0	0
T3	110228	108967	0	0
T5	7499	6741	0	0
T6	50788	49798	0	0
T7	111091	111090	0	0
T8	8171	8083	0	0
T9	19415	19147	0	0
T10	10832	10630	0	0
T11	12755	12519	0	0

LcSeedHwRdEnStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2276	0	0
T2	38018	6	0	0
T3	110228	6	0	0
T5	7499	0	0	0
T6	50788	7	0	0
T7	111091	0	0	0
T8	8171	0	0	0
T9	19415	0	0	0
T10	10832	1	0	0
T11	12755	0	0	0
T26	0	1	0	0
T29	0	5	0	0
T94	0	5	0	0
T95	0	40	0	0
T104	0	2	0	0
T106	9868	1	0	0

LcStateSize_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1157	1157	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0

LcTransitionCntSize_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1157	1157	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0

OtpAstPwrSeqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	73436	72051	0	0
T2	38018	37309	0	0
T3	110228	108967	0	0
T5	7499	6741	0	0
T6	50788	49798	0	0
T7	111091	111090	0	0
T8	8171	8083	0	0
T9	19415	19147	0	0
T10	10832	10630	0	0
T11	12755	12519	0	0

OtpErrorCode0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1157	1157	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0

OtpErrorCode1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1157	1157	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0

OtpErrorCode2_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1157	1157	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0

OtpErrorCode3_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1157	1157	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0

OtpErrorCode4_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1157	1157	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0

OtpHwCfgKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	73436	72051	0	0
T2	38018	37309	0	0
T3	110228	108967	0	0
T5	7499	6741	0	0
T6	50788	49798	0	0
T7	111091	111090	0	0
T8	8171	8083	0	0
T9	19415	19147	0	0
T10	10832	10630	0	0
T11	12755	12519	0	0

OtpIfWidth_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1157	1157	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0

OtpKeymgrKeyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	73436	72051	0	0
T2	38018	37309	0	0
T3	110228	108967	0	0
T5	7499	6741	0	0
T6	50788	49798	0	0
T7	111091	111090	0	0
T8	8171	8083	0	0
T9	19415	19147	0	0
T10	10832	10630	0	0
T11	12755	12519	0	0

OtpLcDataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	73436	72051	0	0
T2	38018	37309	0	0
T3	110228	108967	0	0
T5	7499	6741	0	0
T6	50788	49798	0	0
T7	111091	111090	0	0
T8	8171	8083	0	0
T9	19415	19147	0	0
T10	10832	10630	0	0
T11	12755	12519	0	0

OtpOtgnKeyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	73436	72051	0	0
T2	38018	37309	0	0
T3	110228	108967	0	0
T5	7499	6741	0	0
T6	50788	49798	0	0
T7	111091	111090	0	0
T8	8171	8083	0	0
T9	19415	19147	0	0
T10	10832	10630	0	0
T11	12755	12519	0	0

OtpRespFifoUnderflow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1341882	0	0
T1	73436	1479	0	0
T2	38018	841	0	0
T3	110228	1328	0	0
T5	7499	136	0	0
T6	50788	2598	0	0
T7	111091	1043	0	0
T8	8171	52	0	0
T9	19415	162	0	0
T10	10832	254	0	0
T11	12755	271	0	0

OtpSramKeyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	73436	72051	0	0
T2	38018	37309	0	0
T3	110228	108967	0	0
T5	7499	6741	0	0
T6	50788	49798	0	0
T7	111091	111090	0	0
T8	8171	8083	0	0
T9	19415	19147	0	0
T10	10832	10630	0	0
T11	12755	12519	0	0

PartSelMustBeOnehot_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	73436	72051	0	0
T2	38018	37309	0	0
T3	110228	108967	0	0
T5	7499	6741	0	0
T6	50788	49798	0	0
T7	111091	111090	0	0
T8	8171	8083	0	0
T9	19415	19147	0	0
T10	10832	10630	0	0
T11	12755	12519	0	0

PrimTlOutKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	73436	72051	0	0
T2	38018	37309	0	0
T3	110228	108967	0	0
T5	7499	6741	0	0
T6	50788	49798	0	0
T7	111091	111090	0	0
T8	8171	8083	0	0
T9	19415	19147	0	0
T10	10832	10630	0	0
T11	12755	12519	0	0

PwrOtpInitRspKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	73436	72051	0	0
T2	38018	37309	0	0
T3	110228	108967	0	0
T5	7499	6741	0	0
T6	50788	49798	0	0
T7	111091	111090	0	0
T8	8171	8083	0	0
T9	19415	19147	0	0
T10	10832	10630	0	0
T11	12755	12519	0	0

RmaTokenSize_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1157	1157	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0

SramDataKeySeedSize_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1157	1157	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0

TestExitTokenSize_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1157	1157	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0

TestUnlockTokenSize_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1157	1157	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0

gen_partitions[0].gen_unbuffered.FpvSecCmCtrlPartUnbufFsmCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	50	0	0
T20	850632	10	0	0
T21	866086	10	0	0
T22	849475	10	0	0
T51	15976	0	0	0
T171	15714	0	0	0
T219	0	10	0	0
T220	0	10	0	0
T221	13660	0	0	0
T222	15281	0	0	0
T223	18644	0	0	0
T224	16459	0	0	0
T225	18030	0	0	0

gen_partitions[1].gen_unbuffered.FpvSecCmCtrlPartUnbufFsmCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	50	0	0
T20	850632	10	0	0
T21	866086	10	0	0
T22	849475	10	0	0
T51	15976	0	0	0
T171	15714	0	0	0
T219	0	10	0	0
T220	0	10	0	0
T221	13660	0	0	0
T222	15281	0	0	0
T223	18644	0	0	0
T224	16459	0	0	0
T225	18030	0	0	0

gen_partitions[2].gen_unbuffered.FpvSecCmCtrlPartUnbufFsmCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	50	0	0
T20	850632	10	0	0
T21	866086	10	0	0
T22	849475	10	0	0
T51	15976	0	0	0
T171	15714	0	0	0
T219	0	10	0	0
T220	0	10	0	0
T221	13660	0	0	0
T222	15281	0	0	0
T223	18644	0	0	0
T224	16459	0	0	0
T225	18030	0	0	0

gen_partitions[3].gen_buffered.FpvSecCmCntPartBufCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	50	0	0
T20	850632	10	0	0
T21	866086	10	0	0
T22	849475	10	0	0
T51	15976	0	0	0
T171	15714	0	0	0
T219	0	10	0	0
T220	0	10	0	0
T221	13660	0	0	0
T222	15281	0	0	0
T223	18644	0	0	0
T224	16459	0	0	0
T225	18030	0	0	0

gen_partitions[3].gen_buffered.FpvSecCmCtrlPartBufFsmCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	50	0	0
T20	850632	10	0	0
T21	866086	10	0	0
T22	849475	10	0	0
T51	15976	0	0	0
T171	15714	0	0	0
T219	0	10	0	0
T220	0	10	0	0
T221	13660	0	0	0
T222	15281	0	0	0
T223	18644	0	0	0
T224	16459	0	0	0
T225	18030	0	0	0

gen_partitions[4].gen_buffered.FpvSecCmCntPartBufCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	50	0	0
T20	850632	10	0	0
T21	866086	10	0	0
T22	849475	10	0	0
T51	15976	0	0	0
T171	15714	0	0	0
T219	0	10	0	0
T220	0	10	0	0
T221	13660	0	0	0
T222	15281	0	0	0
T223	18644	0	0	0
T224	16459	0	0	0
T225	18030	0	0	0

gen_partitions[4].gen_buffered.FpvSecCmCtrlPartBufFsmCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	50	0	0
T20	850632	10	0	0
T21	866086	10	0	0
T22	849475	10	0	0
T51	15976	0	0	0
T171	15714	0	0	0
T219	0	10	0	0
T220	0	10	0	0
T221	13660	0	0	0
T222	15281	0	0	0
T223	18644	0	0	0
T224	16459	0	0	0
T225	18030	0	0	0

gen_partitions[5].gen_buffered.FpvSecCmCntPartBufCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	50	0	0
T20	850632	10	0	0
T21	866086	10	0	0
T22	849475	10	0	0
T51	15976	0	0	0
T171	15714	0	0	0
T219	0	10	0	0
T220	0	10	0	0
T221	13660	0	0	0
T222	15281	0	0	0
T223	18644	0	0	0
T224	16459	0	0	0
T225	18030	0	0	0

gen_partitions[5].gen_buffered.FpvSecCmCtrlPartBufFsmCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	50	0	0
T20	850632	10	0	0
T21	866086	10	0	0
T22	849475	10	0	0
T51	15976	0	0	0
T171	15714	0	0	0
T219	0	10	0	0
T220	0	10	0	0
T221	13660	0	0	0
T222	15281	0	0	0
T223	18644	0	0	0
T224	16459	0	0	0
T225	18030	0	0	0

gen_partitions[6].gen_buffered.FpvSecCmCntPartBufCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	50	0	0
T20	850632	10	0	0
T21	866086	10	0	0
T22	849475	10	0	0
T51	15976	0	0	0
T171	15714	0	0	0
T219	0	10	0	0
T220	0	10	0	0
T221	13660	0	0	0
T222	15281	0	0	0
T223	18644	0	0	0
T224	16459	0	0	0
T225	18030	0	0	0

gen_partitions[6].gen_buffered.FpvSecCmCtrlPartBufFsmCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	50	0	0
T20	850632	10	0	0
T21	866086	10	0	0
T22	849475	10	0	0
T51	15976	0	0	0
T171	15714	0	0	0
T219	0	10	0	0
T220	0	10	0	0
T221	13660	0	0	0
T222	15281	0	0	0
T223	18644	0	0	0
T224	16459	0	0	0
T225	18030	0	0	0

gen_partitions[7].gen_lifecycle.FpvSecCmCntPartLcCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	50	0	0
T20	850632	10	0	0
T21	866086	10	0	0
T22	849475	10	0	0
T51	15976	0	0	0
T171	15714	0	0	0
T219	0	10	0	0
T220	0	10	0	0
T221	13660	0	0	0
T222	15281	0	0	0
T223	18644	0	0	0
T224	16459	0	0	0
T225	18030	0	0	0

gen_partitions[7].gen_lifecycle.FpvSecCmCtrlPartLcFsmCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	50	0	0
T20	850632	10	0	0
T21	866086	10	0	0
T22	849475	10	0	0
T51	15976	0	0	0
T171	15714	0	0	0
T219	0	10	0	0
T220	0	10	0	0
T221	13660	0	0	0
T222	15281	0	0	0
T223	18644	0	0	0
T224	16459	0	0	0
T225	18030	0	0	0

gen_reg_we_assert_generic.FpvSecCmPrimFsmCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	50	0	0
T20	850632	10	0	0
T21	866086	10	0	0
T22	849475	10	0	0
T51	15976	0	0	0
T171	15714	0	0	0
T219	0	10	0	0
T220	0	10	0	0
T221	13660	0	0	0
T222	15281	0	0	0
T223	18644	0	0	0
T224	16459	0	0	0
T225	18030	0	0	0

gen_reg_we_assert_generic.FpvSecCmPrimRegWeOnehotCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	50	0	0
T20	850632	10	0	0
T21	866086	10	0	0
T22	849475	10	0	0
T51	15976	0	0	0
T171	15714	0	0	0
T219	0	10	0	0
T220	0	10	0	0
T221	13660	0	0	0
T222	15281	0	0	0
T223	18644	0	0	0
T224	16459	0	0	0
T225	18030	0	0	0