Unified Coverage Report :: Module :: otp_ctrl_core_reg_top

Module : otp_ctrl_core_reg_top

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.86	100.00	95.45			100.00	100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_ip_otp_ctrl_1.0/rtl/otp_ctrl_core_reg_top.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_reg_core	98.86	100.00	95.45			100.00	100.00

---

Module Instance : tb.dut.u_reg_core

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.86	100.00	95.45			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.28	99.59	96.83	100.00		100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
95.99	97.89	88.57	96.52		96.97	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_alert_test_fatal_bus_integ_error	100.00	100.00
u_alert_test_fatal_check_error	100.00	100.00
u_alert_test_fatal_macro_error	100.00	100.00
u_alert_test_fatal_prim_otp_alert	100.00	100.00
u_alert_test_recov_prim_otp_alert	100.00	100.00
u_check_regwen	100.00	100.00	100.00			100.00
u_check_timeout	100.00	100.00	100.00			100.00
u_check_trigger_consistency	100.00	100.00
u_check_trigger_integrity	100.00	100.00
u_check_trigger_regwen	100.00	100.00	100.00			100.00
u_chk	100.00	100.00		100.00			100.00
u_consistency_check_period	100.00	100.00	100.00			100.00
u_creator_sw_cfg_digest_0	100.00	100.00
u_creator_sw_cfg_digest_1	100.00	100.00
u_creator_sw_cfg_read_lock	100.00	100.00	100.00			100.00
u_direct_access_address	100.00	100.00	100.00			100.00
u_direct_access_cmd_digest	100.00	100.00
u_direct_access_cmd_rd	100.00	100.00
u_direct_access_cmd_wr	100.00	100.00
u_direct_access_rdata_0	100.00	100.00
u_direct_access_rdata_1	100.00	100.00
u_direct_access_regwen	100.00	100.00
u_direct_access_wdata_0	100.00	100.00	100.00			100.00
u_direct_access_wdata_1	100.00	100.00	100.00			100.00
u_err_code_err_code_0	100.00	100.00
u_err_code_err_code_1	100.00	100.00
u_err_code_err_code_2	100.00	100.00
u_err_code_err_code_3	100.00	100.00
u_err_code_err_code_4	100.00	100.00
u_err_code_err_code_5	100.00	100.00
u_err_code_err_code_6	100.00	100.00
u_err_code_err_code_7	100.00	100.00
u_err_code_err_code_8	100.00	100.00
u_err_code_err_code_9	100.00	100.00
u_hw_cfg_digest_0	100.00	100.00
u_hw_cfg_digest_1	100.00	100.00
u_integrity_check_period	100.00	100.00	100.00			100.00
u_intr_enable_otp_error	100.00	100.00	100.00			100.00
u_intr_enable_otp_operation_done	100.00	100.00	100.00			100.00
u_intr_state_otp_error	100.00	100.00	100.00			100.00
u_intr_state_otp_operation_done	100.00	100.00	100.00			100.00
u_intr_test_otp_error	100.00	100.00
u_intr_test_otp_operation_done	100.00	100.00
u_owner_sw_cfg_digest_0	100.00	100.00
u_owner_sw_cfg_digest_1	100.00	100.00
u_owner_sw_cfg_read_lock	100.00	100.00	100.00			100.00
u_prim_reg_we_check	100.00	100.00		100.00
u_reg_if	98.67	97.14	97.53			100.00	100.00
u_rsp_intg_gen	100.00	100.00					100.00
u_secret0_digest_0	100.00	100.00
u_secret0_digest_1	100.00	100.00
u_secret1_digest_0	100.00	100.00
u_secret1_digest_1	100.00	100.00
u_secret2_digest_0	100.00	100.00
u_secret2_digest_1	100.00	100.00
u_socket	99.24	98.75	98.21			100.00	100.00
u_status_bus_integ_error	100.00	100.00
u_status_check_pending	100.00	100.00
u_status_creator_sw_cfg_error	100.00	100.00
u_status_dai_error	100.00	100.00
u_status_dai_idle	100.00	100.00
u_status_hw_cfg_error	100.00	100.00
u_status_key_deriv_fsm_error	100.00	100.00
u_status_lci_error	100.00	100.00
u_status_lfsr_fsm_error	100.00	100.00
u_status_life_cycle_error	100.00	100.00
u_status_owner_sw_cfg_error	100.00	100.00
u_status_scrambling_fsm_error	100.00	100.00
u_status_secret0_error	100.00	100.00
u_status_secret1_error	100.00	100.00
u_status_secret2_error	100.00	100.00
u_status_timeout_error	100.00	100.00
u_status_vendor_test_error	100.00	100.00
u_vendor_test_digest_0	100.00	100.00
u_vendor_test_digest_1	100.00	100.00
u_vendor_test_read_lock	100.00	100.00	100.00			100.00

---

Since this is the module's only instance, the coverage report is the same as for the module.

Line Coverage for Module : otp_ctrl_core_reg_top

	Line No.	Total	Covered	Percent
TOTAL		255	255	100.00
ALWAYS	73	4	4	100.00
CONT_ASSIGN	82	1	1	100.00
CONT_ASSIGN	100	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
CONT_ASSIGN	103	1	1	100.00
CONT_ASSIGN	104	1	1	100.00
ALWAYS	130	3	3	100.00
CONT_ASSIGN	167	1	1	100.00
CONT_ASSIGN	168	1	1	100.00
CONT_ASSIGN	412	1	1	100.00
CONT_ASSIGN	427	1	1	100.00
CONT_ASSIGN	443	1	1	100.00
CONT_ASSIGN	449	1	1	100.00
CONT_ASSIGN	464	1	1	100.00
CONT_ASSIGN	480	1	1	100.00
CONT_ASSIGN	496	1	1	100.00
CONT_ASSIGN	512	1	1	100.00
CONT_ASSIGN	528	1	1	100.00
CONT_ASSIGN	960	1	1	100.00
CONT_ASSIGN	963	1	1	100.00
CONT_ASSIGN	978	1	1	100.00
CONT_ASSIGN	994	1	1	100.00
CONT_ASSIGN	1010	1	1	100.00
CONT_ASSIGN	1016	1	1	100.00
CONT_ASSIGN	1048	1	1	100.00
CONT_ASSIGN	1080	1	1	100.00
CONT_ASSIGN	1173	1	1	100.00
CONT_ASSIGN	1176	1	1	100.00
CONT_ASSIGN	1191	1	1	100.00
CONT_ASSIGN	1207	1	1	100.00
CONT_ASSIGN	1241	1	1	100.00
CONT_ASSIGN	1272	1	1	100.00
CONT_ASSIGN	1303	1	1	100.00
CONT_ASSIGN	1334	1	1	100.00
CONT_ASSIGN	1365	1	1	100.00
CONT_ASSIGN	1396	1	1	100.00
ALWAYS	1665	37	37	100.00
CONT_ASSIGN	1704	1	1	100.00
ALWAYS	1708	1	1	100.00
CONT_ASSIGN	1748	1	1	100.00
CONT_ASSIGN	1750	1	1	100.00
CONT_ASSIGN	1752	1	1	100.00
CONT_ASSIGN	1753	1	1	100.00
CONT_ASSIGN	1755	1	1	100.00
CONT_ASSIGN	1757	1	1	100.00
CONT_ASSIGN	1758	1	1	100.00
CONT_ASSIGN	1760	1	1	100.00
CONT_ASSIGN	1762	1	1	100.00
CONT_ASSIGN	1763	1	1	100.00
CONT_ASSIGN	1765	1	1	100.00
CONT_ASSIGN	1767	1	1	100.00
CONT_ASSIGN	1769	1	1	100.00
CONT_ASSIGN	1771	1	1	100.00
CONT_ASSIGN	1773	1	1	100.00
CONT_ASSIGN	1774	1	1	100.00
CONT_ASSIGN	1775	1	1	100.00
CONT_ASSIGN	1776	1	1	100.00
CONT_ASSIGN	1777	1	1	100.00
CONT_ASSIGN	1779	1	1	100.00
CONT_ASSIGN	1781	1	1	100.00
CONT_ASSIGN	1783	1	1	100.00
CONT_ASSIGN	1784	1	1	100.00
CONT_ASSIGN	1786	1	1	100.00
CONT_ASSIGN	1787	1	1	100.00
CONT_ASSIGN	1789	1	1	100.00
CONT_ASSIGN	1790	1	1	100.00
CONT_ASSIGN	1792	1	1	100.00
CONT_ASSIGN	1793	1	1	100.00
CONT_ASSIGN	1794	1	1	100.00
CONT_ASSIGN	1795	1	1	100.00
CONT_ASSIGN	1797	1	1	100.00
CONT_ASSIGN	1798	1	1	100.00
CONT_ASSIGN	1800	1	1	100.00
CONT_ASSIGN	1802	1	1	100.00
CONT_ASSIGN	1803	1	1	100.00
CONT_ASSIGN	1805	1	1	100.00
CONT_ASSIGN	1806	1	1	100.00
CONT_ASSIGN	1808	1	1	100.00
CONT_ASSIGN	1809	1	1	100.00
CONT_ASSIGN	1811	1	1	100.00
CONT_ASSIGN	1812	1	1	100.00
CONT_ASSIGN	1814	1	1	100.00
CONT_ASSIGN	1815	1	1	100.00
CONT_ASSIGN	1817	1	1	100.00
CONT_ASSIGN	1818	1	1	100.00
CONT_ASSIGN	1820	1	1	100.00
CONT_ASSIGN	1821	1	1	100.00
CONT_ASSIGN	1823	1	1	100.00
CONT_ASSIGN	1824	1	1	100.00
CONT_ASSIGN	1825	1	1	100.00
CONT_ASSIGN	1826	1	1	100.00
CONT_ASSIGN	1827	1	1	100.00
CONT_ASSIGN	1828	1	1	100.00
CONT_ASSIGN	1829	1	1	100.00
CONT_ASSIGN	1830	1	1	100.00
CONT_ASSIGN	1831	1	1	100.00
CONT_ASSIGN	1832	1	1	100.00
CONT_ASSIGN	1833	1	1	100.00
CONT_ASSIGN	1834	1	1	100.00
CONT_ASSIGN	1835	1	1	100.00
CONT_ASSIGN	1836	1	1	100.00
CONT_ASSIGN	1837	1	1	100.00
ALWAYS	1841	37	37	100.00
ALWAYS	1882	73	73	100.00
CONT_ASSIGN	2074	0	0
CONT_ASSIGN	2082	1	1	100.00
CONT_ASSIGN	2083	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_otp_ctrl_1.0/rtl/otp_ctrl_core_reg_top.sv' or '../src/lowrisc_ip_otp_ctrl_1.0/rtl/otp_ctrl_core_reg_top.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
73	1	1
74	1	1
75	1	1
76	1	1
			MISSING_ELSE
82	1	1
100	1	1
101	1	1
103	1	1
104	1	1
130	1	1
136	1	1
137	1	1
			MISSING_ELSE
167	1	1
168	1	1
412	1	1
427	1	1
443	1	1
449	1	1
464	1	1
480	1	1
496	1	1
512	1	1
528	1	1
960	1	1
963	1	1
978	1	1
994	1	1
1010	1	1
1016	1	1
1048	1	1
1080	1	1
1173	1	1
1176	1	1
1191	1	1
1207	1	1
1241	1	1
1272	1	1
1303	1	1
1334	1	1
1365	1	1
1396	1	1
1665	1	1
1666	1	1
1667	1	1
1668	1	1
1669	1	1
1670	1	1
1671	1	1
1672	1	1
1673	1	1
1674	1	1
1675	1	1
1676	1	1
1677	1	1
1678	1	1
1679	1	1
1680	1	1
1681	1	1
1682	1	1
1683	1	1
1684	1	1
1685	1	1
1686	1	1
1687	1	1
1688	1	1
1689	1	1
1690	1	1
1691	1	1
1692	1	1
1693	1	1
1694	1	1
1695	1	1
1696	1	1
1697	1	1
1698	1	1
1699	1	1
1700	1	1
1701	1	1
1704	1	1
1708	1	1
1748	1	1
1750	1	1
1752	1	1
1753	1	1
1755	1	1
1757	1	1
1758	1	1
1760	1	1
1762	1	1
1763	1	1
1765	1	1
1767	1	1
1769	1	1
1771	1	1
1773	1	1
1774	1	1
1775	1	1
1776	1	1
1777	1	1
1779	1	1
1781	1	1
1783	1	1
1784	1	1
1786	1	1
1787	1	1
1789	1	1
1790	1	1
1792	1	1
1793	1	1
1794	1	1
1795	1	1
1797	1	1
1798	1	1
1800	1	1
1802	1	1
1803	1	1
1805	1	1
1806	1	1
1808	1	1
1809	1	1
1811	1	1
1812	1	1
1814	1	1
1815	1	1
1817	1	1
1818	1	1
1820	1	1
1821	1	1
1823	1	1
1824	1	1
1825	1	1
1826	1	1
1827	1	1
1828	1	1
1829	1	1
1830	1	1
1831	1	1
1832	1	1
1833	1	1
1834	1	1
1835	1	1
1836	1	1
1837	1	1
1841	1	1
1842	1	1
1843	1	1
1844	1	1
1845	1	1
1846	1	1
1847	1	1
1848	1	1
1849	1	1
1850	1	1
1851	1	1
1852	1	1
1853	1	1
1854	1	1
1855	1	1
1856	1	1
1857	1	1
1858	1	1
1859	1	1
1860	1	1
1861	1	1
1862	1	1
1863	1	1
1864	1	1
1865	1	1
1866	1	1
1867	1	1
1868	1	1
1869	1	1
1870	1	1
1871	1	1
1872	1	1
1873	1	1
1874	1	1
1875	1	1
1876	1	1
1877	1	1
1882	1	1
1883	1	1
1885	1	1
1886	1	1
1890	1	1
1891	1	1
1895	1	1
1896	1	1
1900	1	1
1901	1	1
1902	1	1
1903	1	1
1904	1	1
1908	1	1
1909	1	1
1910	1	1
1911	1	1
1912	1	1
1913	1	1
1914	1	1
1915	1	1
1916	1	1
1917	1	1
1918	1	1
1919	1	1
1920	1	1
1921	1	1
1922	1	1
1923	1	1
1924	1	1
1928	1	1
1929	1	1
1930	1	1
1931	1	1
1932	1	1
1933	1	1
1934	1	1
1935	1	1
1936	1	1
1937	1	1
1941	1	1
1945	1	1
1946	1	1
1947	1	1
1951	1	1
1955	1	1
1959	1	1
1963	1	1
1967	1	1
1971	1	1
1975	1	1
1976	1	1
1980	1	1
1984	1	1
1988	1	1
1992	1	1
1996	1	1
2000	1	1
2004	1	1
2008	1	1
2012	1	1
2016	1	1
2020	1	1
2024	1	1
2028	1	1
2032	1	1
2036	1	1
2040	1	1
2044	1	1
2048	1	1
2052	1	1
2056	1	1
2060	1	1
2074		unreachable
2082	1	1
2083	1	1

---

Cond Coverage for Module : otp_ctrl_core_reg_top

	Total	Covered	Percent
Conditions	418	399	95.45
Logical	418	399	95.45
Non-Logical	0	0
Event	0	0

This module contains a very large number of conditions, so the report has been split into multiple pages, by source line number. Click on the line number range in the table below to see the condition coverage for that section of the module.

Line numbers	Percent
63-1830	96.92
1831-1837	75.00

---

Branch Coverage for Module : otp_ctrl_core_reg_top

	Line No.	Total	Covered	Percent
Branches		46	46	100.00
TERNARY	1704	2	2	100.00
IF	73	3	3	100.00
TERNARY	130	2	2	100.00
IF	136	2	2	100.00
CASE	1883	37	37	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_otp_ctrl_1.0/rtl/otp_ctrl_core_reg_top.sv' or '../src/lowrisc_ip_otp_ctrl_1.0/rtl/otp_ctrl_core_reg_top.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	1704	((reg_re || reg_we)) ? 

Branches:

-1-	Status	Tests
1	Covered	T16,T109,T110
0	Covered	T16,T109,T110

	LineNo.	Expression
-1-:	73	if ((!rst_ni))
-2-:	75	if ((intg_err || reg_we_err))

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T16,T109,T110
0	1	Covered	T115,T211,T217
0	0	Covered	T16,T109,T110

	LineNo.	Expression
-1-:	130	((tl_i.a_address[(AW - 1):0] inside {[4096:6143]})) ? 

Branches:

-1-	Status	Tests
1	Covered	T110,T114,T111
0	Covered	T16,T109,T110

	LineNo.	Expression
-1-:	136	if (intg_err)

Branches:

-1-	Status	Tests
1	Covered	T115,T211,T217
0	Covered	T16,T109,T110

	LineNo.	Expression
-1-:	1883	case (1'b1)

Branches:

-1-	Status	Tests
addr_hit[0]	Covered	T16,T109,T110
addr_hit[1]	Covered	T16,T109,T110
addr_hit[2]	Covered	T16,T109,T110
addr_hit[3]	Covered	T16,T109,T110
addr_hit[4]	Covered	T16,T109,T110
addr_hit[5]	Covered	T16,T109,T110
addr_hit[6]	Covered	T16,T109,T110
addr_hit[7]	Covered	T16,T109,T110
addr_hit[8]	Covered	T16,T109,T110
addr_hit[9]	Covered	T16,T109,T110
addr_hit[10]	Covered	T16,T109,T110
addr_hit[11]	Covered	T16,T109,T110
addr_hit[12]	Covered	T16,T109,T110
addr_hit[13]	Covered	T16,T109,T110
addr_hit[14]	Covered	T16,T109,T110
addr_hit[15]	Covered	T16,T109,T110
addr_hit[16]	Covered	T16,T109,T110
addr_hit[17]	Covered	T16,T109,T110
addr_hit[18]	Covered	T16,T109,T110
addr_hit[19]	Covered	T16,T109,T110
addr_hit[20]	Covered	T16,T109,T110
addr_hit[21]	Covered	T16,T109,T110
addr_hit[22]	Covered	T16,T109,T110
addr_hit[23]	Covered	T16,T109,T110
addr_hit[24]	Covered	T16,T109,T110
addr_hit[25]	Covered	T16,T109,T110
addr_hit[26]	Covered	T16,T109,T110
addr_hit[27]	Covered	T16,T109,T110
addr_hit[28]	Covered	T16,T109,T110
addr_hit[29]	Covered	T16,T109,T110
addr_hit[30]	Covered	T16,T109,T110
addr_hit[31]	Covered	T16,T109,T110
addr_hit[32]	Covered	T16,T109,T110
addr_hit[33]	Covered	T16,T109,T110
addr_hit[34]	Covered	T16,T109,T110
addr_hit[35]	Covered	T16,T109,T110
default	Covered	T16,T109,T110

---

Assert Coverage for Module : otp_ctrl_core_reg_top

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
en2addrHit	2147483647	7087276	0	0
reAfterRv	2147483647	7087269	0	0
rePulse	2147483647	4026747	0	0
wePulse	2147483647	3060522	0	0

en2addrHit

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	7087276	0	0
T16	3780	290	0	0
T109	5297	252	0	0
T110	6803	58	0	0
T111	3691	40	0	0
T112	3722	40	0	0
T113	4025	40	0	0
T114	4145	87	0	0
T181	3152	40	0	0
T182	3704	22	0	0
T183	5844	290	0	0

reAfterRv

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	7087269	0	0
T16	3780	290	0	0
T109	5297	252	0	0
T110	6803	58	0	0
T111	3691	40	0	0
T112	3722	40	0	0
T113	4025	40	0	0
T114	4145	87	0	0
T181	3152	40	0	0
T182	3704	22	0	0
T183	5844	290	0	0

rePulse

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	4026747	0	0
T16	3780	92	0	0
T109	5297	94	0	0
T110	6803	27	0	0
T111	3691	20	0	0
T112	3722	20	0	0
T113	4025	20	0	0
T114	4145	29	0	0
T181	3152	20	0	0
T182	3704	11	0	0
T183	5844	102	0	0

wePulse

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	3060522	0	0
T16	3780	198	0	0
T109	5297	158	0	0
T110	6803	31	0	0
T111	3691	20	0	0
T112	3722	20	0	0
T113	4025	20	0	0
T114	4145	58	0	0
T181	3152	20	0	0
T182	3704	11	0	0
T183	5844	188	0	0