Unified Coverage Report :: Module :: otp_ctrl_part_unbuf

Module : otp_ctrl_part_unbuf

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
92.06	98.11	97.78		66.67	97.73	100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_ip_otp_ctrl_1.0/rtl/otp_ctrl_part_unbuf.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.gen_partitions[0].gen_unbuffered.u_part_unbuf	93.17	97.62	95.56		83.33	93.18	96.15
tb.dut.gen_partitions[1].gen_unbuffered.u_part_unbuf	98.33	100.00	100.00		91.67	100.00	100.00
tb.dut.gen_partitions[2].gen_unbuffered.u_part_unbuf	98.33	100.00	100.00		91.67	100.00	100.00

---

Module Instance : tb.dut.gen_partitions[0].gen_unbuffered.u_part_unbuf

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.17	97.62	95.56		83.33	93.18	96.15

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.53	98.44	95.74	97.87	83.33	94.64	97.14

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
95.99	97.89	88.57	96.52		96.97	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_digest_write_lock.u_prim_mubi8_sender_write_lock	100.00	100.00				100.00	100.00
u_otp_ctrl_ecc_reg	99.57	100.00	100.00	97.87		100.00	100.00
u_prim_mubi8_sender_read_lock_pre	100.00	100.00				100.00	100.00
u_prim_mubi8_sender_write_lock_pre	100.00	100.00				100.00	100.00
u_state_regs	100.00	100.00				100.00	100.00

---

Module Instance : tb.dut.gen_partitions[1].gen_unbuffered.u_part_unbuf

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.33	100.00	100.00		91.67	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.26	100.00	100.00	97.87	91.67	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
95.99	97.89	88.57	96.52		96.97	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_digest_write_lock.u_prim_mubi8_sender_write_lock	100.00	100.00				100.00	100.00
u_otp_ctrl_ecc_reg	99.57	100.00	100.00	97.87		100.00	100.00
u_prim_mubi8_sender_read_lock_pre	100.00	100.00				100.00	100.00
u_prim_mubi8_sender_write_lock_pre	100.00	100.00				100.00	100.00
u_state_regs	100.00	100.00				100.00	100.00

---

Module Instance : tb.dut.gen_partitions[2].gen_unbuffered.u_part_unbuf

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.33	100.00	100.00		91.67	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.26	100.00	100.00	97.87	91.67	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
95.99	97.89	88.57	96.52		96.97	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_digest_write_lock.u_prim_mubi8_sender_write_lock	100.00	100.00				100.00	100.00
u_otp_ctrl_ecc_reg	99.57	100.00	100.00	97.87		100.00	100.00
u_prim_mubi8_sender_read_lock_pre	100.00	100.00				100.00	100.00
u_prim_mubi8_sender_write_lock_pre	100.00	100.00				100.00	100.00
u_state_regs	100.00	100.00				100.00	100.00

Line Coverage for Module : otp_ctrl_part_unbuf ( parameter Info=8196,DigestOffset=56,StateWidth=10 )
Line Coverage for Module self-instances :

SCORE	LINE
93.17	97.62

tb.dut.gen_partitions[0].gen_unbuffered.u_part_unbuf

	Line No.	Total	Covered	Percent
TOTAL		88	83	94.32
CONT_ASSIGN	137	1	1	100.00
ALWAYS	147	67	62	92.54
CONT_ASSIGN	328	1	1	100.00
CONT_ASSIGN	330	1	1	100.00
CONT_ASSIGN	335	1	1	100.00
CONT_ASSIGN	336	1	1	100.00
CONT_ASSIGN	340	1	1	100.00
CONT_ASSIGN	344	1	1	100.00
CONT_ASSIGN	371	1	1	100.00
CONT_ASSIGN	396	1	1	100.00
CONT_ASSIGN	430	1	1	100.00
ALWAYS	437	3	3	100.00
ALWAYS	440	8	8	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_otp_ctrl_1.0/rtl/otp_ctrl_part_unbuf.sv' or '../src/lowrisc_ip_otp_ctrl_1.0/rtl/otp_ctrl_part_unbuf.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
137	1	1
147	1	1
150	1	1
153	1	1
154	1	1
157	1	1
158	1	1
159	1	1
162	1	1
165	1	1
166	1	1
167	1	1
169	1	1
174	1	1
175	1	1
			MISSING_ELSE
183	1	1
184	1	1
185	1	1
			==> MISSING_ELSE
193	1	1
194	1	1
197	1	1
199	1	1
205	1	1
206	1	1
			MISSING_ELSE
209	0	1
210	0	1
			MISSING_ELSE
218	1	1
219	1	1
220	1	1
221	1	1
222	1	1
			MISSING_ELSE
231	1	1
233	1	1
236	1	1
237	1	1
238	1	1
239	1	1
			MISSING_ELSE
242	1	1
243	1	1
244	1	1
245	1	1
253	1	1
254	1	1
255	1	1
258	1	1
260	1	1
266	1	1
267	1	1
			MISSING_ELSE
270	0	1
271	0	1
273	0	1
			MISSING_ELSE
282	1	1
283	1	1
			MISSING_ELSE
287	1	1
288	1	1
289	1	1
290	1	1
291	1	1
292	1	1
			MISSING_ELSE
308	1	1
309	1	1
310	1	1
311	1	1
			MISSING_ELSE
			MISSING_ELSE
315	1	1
316	1	1
317	1	1
318	1	1
319	1	1
			MISSING_ELSE
			MISSING_ELSE
328	1	1
330	1	1
335	1	1
336	1	1
340	1	1
344	1	1
371	1	1
396	1	1
430	1	1
437	3	3
440	1	1
441	1	1
442	1	1
443	1	1
445	1	1
446	1	1
447	1	1
448	1	1
			MISSING_ELSE

---

Line Coverage for Module : otp_ctrl_part_unbuf ( parameter Info=16879621,DigestOffset=856,StateWidth=10 )
Line Coverage for Module self-instances :

SCORE	LINE
98.33	100.00

tb.dut.gen_partitions[1].gen_unbuffered.u_part_unbuf

	Line No.	Total	Covered	Percent
TOTAL		88	88	100.00
CONT_ASSIGN	137	1	1	100.00
ALWAYS	147	67	67	100.00
CONT_ASSIGN	328	1	1	100.00
CONT_ASSIGN	330	1	1	100.00
CONT_ASSIGN	335	1	1	100.00
CONT_ASSIGN	336	1	1	100.00
CONT_ASSIGN	340	1	1	100.00
CONT_ASSIGN	344	1	1	100.00
CONT_ASSIGN	371	1	1	100.00
CONT_ASSIGN	396	1	1	100.00
CONT_ASSIGN	430	1	1	100.00
ALWAYS	437	3	3	100.00
ALWAYS	440	8	8	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_otp_ctrl_1.0/rtl/otp_ctrl_part_unbuf.sv' or '../src/lowrisc_ip_otp_ctrl_1.0/rtl/otp_ctrl_part_unbuf.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
137	1	1
147	1	1
150	1	1
153	1	1
154	1	1
157	1	1
158	1	1
159	1	1
162	1	1
165	1	1
166	1	1
167	1	1
169	1	1
174	1	1
175	1	1
			MISSING_ELSE
183	1	1
184	1	1
185	1	1
			MISSING_ELSE
193	1	1
194	1	1
197	1	1
199	1	1
205	1	1
206	1	1
			MISSING_ELSE
209	1	1
210	1	1
			MISSING_ELSE
218	1	1
219	1	1
220	1	1
221	1	1
222	1	1
			MISSING_ELSE
231	1	1
233	1	1
236	1	1
237	1	1
238	1	1
239	1	1
			MISSING_ELSE
242	1	1
243	1	1
244	1	1
245	1	1
253	1	1
254	1	1
255	1	1
258	1	1
260	1	1
266	1	1
267	1	1
			MISSING_ELSE
270	1	1
271	1	1
273	1	1
			MISSING_ELSE
282	1	1
283	1	1
			MISSING_ELSE
287	1	1
288	1	1
289	1	1
290	1	1
291	1	1
292	1	1
			MISSING_ELSE
308	1	1
309	1	1
310	1	1
311	1	1
			MISSING_ELSE
			MISSING_ELSE
315	1	1
316	1	1
317	1	1
318	1	1
319	1	1
			MISSING_ELSE
			MISSING_ELSE
328	1	1
330	1	1
335	1	1
336	1	1
340	1	1
344	1	1
371	1	1
396	1	1
430	1	1
437	3	3
440	1	1
441	1	1
442	1	1
443	1	1
445	1	1
446	1	1
447	1	1
448	1	1
			MISSING_ELSE

---

Line Coverage for Module : otp_ctrl_part_unbuf ( parameter Info=226594821,DigestOffset=1656,StateWidth=10 )
Line Coverage for Module self-instances :

SCORE	LINE
98.33	100.00

tb.dut.gen_partitions[2].gen_unbuffered.u_part_unbuf

	Line No.	Total	Covered	Percent
TOTAL		88	88	100.00
CONT_ASSIGN	137	1	1	100.00
ALWAYS	147	67	67	100.00
CONT_ASSIGN	328	1	1	100.00
CONT_ASSIGN	330	1	1	100.00
CONT_ASSIGN	335	1	1	100.00
CONT_ASSIGN	336	1	1	100.00
CONT_ASSIGN	340	1	1	100.00
CONT_ASSIGN	344	1	1	100.00
CONT_ASSIGN	371	1	1	100.00
CONT_ASSIGN	396	1	1	100.00
CONT_ASSIGN	430	1	1	100.00
ALWAYS	437	3	3	100.00
ALWAYS	440	8	8	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_otp_ctrl_1.0/rtl/otp_ctrl_part_unbuf.sv' or '../src/lowrisc_ip_otp_ctrl_1.0/rtl/otp_ctrl_part_unbuf.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
137	1	1
147	1	1
150	1	1
153	1	1
154	1	1
157	1	1
158	1	1
159	1	1
162	1	1
165	1	1
166	1	1
167	1	1
169	1	1
174	1	1
175	1	1
			MISSING_ELSE
183	1	1
184	1	1
185	1	1
			MISSING_ELSE
193	1	1
194	1	1
197	1	1
199	1	1
205	1	1
206	1	1
			MISSING_ELSE
209	1	1
210	1	1
			MISSING_ELSE
218	1	1
219	1	1
220	1	1
221	1	1
222	1	1
			MISSING_ELSE
231	1	1
233	1	1
236	1	1
237	1	1
238	1	1
239	1	1
			MISSING_ELSE
242	1	1
243	1	1
244	1	1
245	1	1
253	1	1
254	1	1
255	1	1
258	1	1
260	1	1
266	1	1
267	1	1
			MISSING_ELSE
270	1	1
271	1	1
273	1	1
			MISSING_ELSE
282	1	1
283	1	1
			MISSING_ELSE
287	1	1
288	1	1
289	1	1
290	1	1
291	1	1
292	1	1
			MISSING_ELSE
308	1	1
309	1	1
310	1	1
311	1	1
			MISSING_ELSE
			MISSING_ELSE
315	1	1
316	1	1
317	1	1
318	1	1
319	1	1
			MISSING_ELSE
			MISSING_ELSE
328	1	1
330	1	1
335	1	1
336	1	1
340	1	1
344	1	1
371	1	1
396	1	1
430	1	1
437	3	3
440	1	1
441	1	1
442	1	1
443	1	1
445	1	1
446	1	1
447	1	1
448	1	1
			MISSING_ELSE

---

Cond Coverage for Module : otp_ctrl_part_unbuf ( parameter Info=8196,DigestOffset=56,StateWidth=10 )
Cond Coverage for Module self-instances :

SCORE	COND
93.17	95.56

tb.dut.gen_partitions[0].gen_unbuffered.u_part_unbuf

	Total	Covered	Percent
Conditions	45	43	95.56
Logical	45	43	95.56
Non-Logical	0	0
Event	0	0

 LINE       197
 EXPRESSION ((((!1'b0)) && (otp_err_e'(otp_err_i) == MacroEccUncorrError)) || (otp_err_e'(otp_err_i) inside {NoError, MacroEccCorrError}))
             ------------------------------1------------------------------    -----------------------------2-----------------------------

-1-	-2-	Status	Tests
0	0	Not Covered
0	1	Covered	T1,T2,T3
1	0	Covered	T38,T124,T50

 LINE       197
 SUB-EXPRESSION (((!1'b0)) && (otp_err_e'(otp_err_i) == MacroEccUncorrError))
                 ----1----    -----------------------2----------------------

-1-	-2-	Status	Tests
-	0	Covered	T1,T2,T3
-	1	Covered	T38,T124,T50

 LINE       197
 SUB-EXPRESSION (otp_err_e'(otp_err_i) == MacroEccUncorrError)
                -----------------------1----------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T38,T124,T50

 LINE       205
 EXPRESSION (otp_err_e'(otp_err_i) != NoError)
            -----------------1----------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T26,T23,T59

 LINE       258
 EXPRESSION ((((!1'b0)) && (otp_err_e'(otp_err_i) == MacroEccUncorrError)) || (otp_err_e'(otp_err_i) inside {NoError, MacroEccCorrError}))
             ------------------------------1------------------------------    -----------------------------2-----------------------------

-1-	-2-	Status	Tests
0	0	Not Covered
0	1	Covered	T1,T3,T5
1	0	Covered	T118,T119,T102

 LINE       258
 SUB-EXPRESSION (((!1'b0)) && (otp_err_e'(otp_err_i) == MacroEccUncorrError))
                 ----1----    -----------------------2----------------------

-1-	-2-	Status	Tests
-	0	Covered	T1,T3,T5
-	1	Covered	T118,T119,T102

 LINE       258
 SUB-EXPRESSION (otp_err_e'(otp_err_i) == MacroEccUncorrError)
                -----------------------1----------------------

-1-	Status	Tests
0	Covered	T1,T3,T5
1	Covered	T118,T119,T102

 LINE       266
 EXPRESSION (otp_err_e'(otp_err_i) != NoError)
            -----------------1----------------

-1-	Status	Tests
0	Covered	T1,T3,T5
1	Covered	T29,T118,T119

 LINE       282
 EXPRESSION (error_q == NoError)
            ----------1---------

-1-	Status	Tests
0	Covered	T7,T9,T37
1	Covered	T20,T21,T22

 LINE       310
 EXPRESSION (state_q != ErrorSt)
            ----------1---------

-1-	Status	Tests
0	Covered	T125,T126,T127
1	Covered	T125,T126,T127

 LINE       318
 EXPRESSION (state_q != ErrorSt)
            ----------1---------

-1-	Status	Tests
0	Covered	T7,T9,T37
1	Covered	T7,T9,T37

 LINE       330
 EXPRESSION ((tlul_rvalid_o && (tlul_rerror_o == '0)) ? otp_rdata_i[31:0] : '0)
             --------------------1-------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T3,T5

 LINE       330
 SUB-EXPRESSION (tlul_rvalid_o && (tlul_rerror_o == '0))
                 ------1------    ----------2----------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T3,T5

 LINE       330
 SUB-EXPRESSION (tlul_rerror_o == '0)
                ----------1----------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       335
 EXPRESSION ((otp_addr_sel == DigestAddrSel) ? DigestOffset : ({tlul_addr_q, 2'b0}))
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T3,T5
1	Covered	T1,T2,T3

 LINE       335
 SUB-EXPRESSION (otp_addr_sel == DigestAddrSel)
                ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       344
 EXPRESSION 
 Number  Term
      1  (otp_addr_sel == DigestAddrSel) ? (2'((unsigned'(((otp_ctrl_pkg::ScrmblBlockWidth / otp_ctrl_pkg::OtpWidth) - 1))))) : (2'((unsigned'(((32 / otp_ctrl_pkg::OtpWidth) - 1))))))

-1-	Status	Tests
0	Covered	T1,T3,T5
1	Covered	T1,T2,T3

 LINE       344
 SUB-EXPRESSION (otp_addr_sel == DigestAddrSel)
                ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       371
 EXPRESSION (((~init_done_o)) ? MuBi8True : MuBi8False)
             --------1-------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       396
 EXPRESSION ((digest_o != '0) ? MuBi8True : MuBi8False)
             --------1-------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T6,T107

 LINE       396
 SUB-EXPRESSION (digest_o != '0)
                --------1-------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T6,T107

---

Cond Coverage for Module : otp_ctrl_part_unbuf ( parameter Info=16879621,DigestOffset=856,StateWidth=10 + Info=226594821,DigestOffset=1656,StateWidth=10 )
Cond Coverage for Module self-instances :

SCORE	COND
98.33	100.00

tb.dut.gen_partitions[1].gen_unbuffered.u_part_unbuf

SCORE	COND
98.33	100.00

tb.dut.gen_partitions[2].gen_unbuffered.u_part_unbuf

	Total	Covered	Percent
Conditions	35	35	100.00
Logical	35	35	100.00
Non-Logical	0	0
Event	0	0

 LINE       197
 EXPRESSION ((((!1'b1) && (otp_err_e'(otp_err_i) == MacroEccUncorrError))) || (otp_err_e'(otp_err_i) inside {NoError, MacroEccCorrError}))
             ------------------------------1------------------------------    -----------------------------2-----------------------------

-1-	-2-	Status	Tests
0	0	Covered	T37,T128,T86
0	1	Covered	T1,T2,T3
1	0	Unreachable

 LINE       205
 EXPRESSION (otp_err_e'(otp_err_i) != NoError)
            -----------------1----------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T37,T58,T59

 LINE       258
 EXPRESSION ((((!1'b1) && (otp_err_e'(otp_err_i) == MacroEccUncorrError))) || (otp_err_e'(otp_err_i) inside {NoError, MacroEccCorrError}))
             ------------------------------1------------------------------    -----------------------------2-----------------------------

-1-	-2-	Status	Tests
0	0	Covered	T119,T123,T129
0	1	Covered	T1,T2,T3
1	0	Unreachable

 LINE       266
 EXPRESSION (otp_err_e'(otp_err_i) != NoError)
            -----------------1----------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T29,T118,T130

 LINE       282
 EXPRESSION (error_q == NoError)
            ----------1---------

-1-	Status	Tests
0	Covered	T7,T9,T37
1	Covered	T20,T21,T22

 LINE       310
 EXPRESSION (state_q != ErrorSt)
            ----------1---------

-1-	Status	Tests
0	Covered	T131,T125,T126
1	Covered	T131,T125,T126

 LINE       318
 EXPRESSION (state_q != ErrorSt)
            ----------1---------

-1-	Status	Tests
0	Covered	T7,T9,T37
1	Covered	T7,T9,T37

 LINE       330
 EXPRESSION ((tlul_rvalid_o && (tlul_rerror_o == '0)) ? otp_rdata_i[31:0] : '0)
             --------------------1-------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       330
 SUB-EXPRESSION (tlul_rvalid_o && (tlul_rerror_o == '0))
                 ------1------    ----------2----------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       330
 SUB-EXPRESSION (tlul_rerror_o == '0)
                ----------1----------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       335
 EXPRESSION ((otp_addr_sel == DigestAddrSel) ? DigestOffset : ({tlul_addr_q, 2'b0}))
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       335
 SUB-EXPRESSION (otp_addr_sel == DigestAddrSel)
                ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       344
 EXPRESSION 
 Number  Term
      1  (otp_addr_sel == DigestAddrSel) ? (2'((unsigned'(((otp_ctrl_pkg::ScrmblBlockWidth / otp_ctrl_pkg::OtpWidth) - 1))))) : (2'((unsigned'(((32 / otp_ctrl_pkg::OtpWidth) - 1))))))

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       344
 SUB-EXPRESSION (otp_addr_sel == DigestAddrSel)
                ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       371
 EXPRESSION (((~init_done_o)) ? MuBi8True : MuBi8False)
             --------1-------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       396
 EXPRESSION ((digest_o != '0) ? MuBi8True : MuBi8False)
             --------1-------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       396
 SUB-EXPRESSION (digest_o != '0)
                --------1-------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

---

FSM Coverage for Module : otp_ctrl_part_unbuf

Summary for FSM :: state_q

	Total	Covered	Percent
States	7	7	100.00	(Not included in score)
Transitions	13	12	92.31
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
ErrorSt	209	Covered	T16
IdleSt	199	Covered	T16
InitSt	175	Covered	T16
InitWaitSt	185	Covered	T16
ReadSt	221	Covered	T16
ReadWaitSt	239	Covered	T16
ResetSt	173	Covered	T16

transitions	Line No.	Covered	Tests
IdleSt->ErrorSt	309	Covered	T16
IdleSt->ReadSt	221	Covered	T16
InitSt->ErrorSt	309	Covered	T16
InitSt->InitWaitSt	185	Covered	T16
InitWaitSt->ErrorSt	209	Covered	T16
InitWaitSt->IdleSt	199	Covered	T16
ReadSt->ErrorSt	309	Not Covered
ReadSt->IdleSt	242	Covered	T16
ReadSt->ReadWaitSt	239	Covered	T16
ReadWaitSt->ErrorSt	270	Covered	T16
ReadWaitSt->IdleSt	260	Covered	T16
ResetSt->ErrorSt	309	Covered	T16
ResetSt->InitSt	175	Covered	T16

Summary for FSM :: error_q

	Total	Covered	Percent
States	5	5	100.00	(Not included in score)
Transitions	20	10	50.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: error_q

---

states	Line No.	Covered	Tests
AccessError	243	Covered	T16
CheckFailError	311	Covered	T16
FsmStateError	283	Covered	T16
MacroEccCorrError	206	Covered	T16
NoError	220	Covered	T16

transitions	Line No.	Covered	Tests
AccessError->CheckFailError	311	Not Covered
AccessError->FsmStateError	319	Covered	T16
AccessError->MacroEccCorrError	206	Not Covered
AccessError->NoError	220	Covered	T16
CheckFailError->AccessError	243	Not Covered
CheckFailError->FsmStateError	319	Not Covered
CheckFailError->MacroEccCorrError	206	Not Covered
CheckFailError->NoError	220	Covered	T16
FsmStateError->AccessError	243	Not Covered
FsmStateError->CheckFailError	311	Not Covered
FsmStateError->MacroEccCorrError	206	Not Covered
FsmStateError->NoError	220	Covered	T16
MacroEccCorrError->AccessError	243	Not Covered
MacroEccCorrError->CheckFailError	311	Not Covered
MacroEccCorrError->FsmStateError	319	Covered	T16
MacroEccCorrError->NoError	220	Covered	T16
NoError->AccessError	243	Covered	T16
NoError->CheckFailError	311	Covered	T16
NoError->FsmStateError	283	Covered	T16
NoError->MacroEccCorrError	206	Covered	T16

---

Branch Coverage for Module : otp_ctrl_part_unbuf ( parameter Info=16879621,DigestOffset=856,StateWidth=10 )
Branch Coverage for Module self-instances :

SCORE	BRANCH
98.33	100.00

tb.dut.gen_partitions[1].gen_unbuffered.u_part_unbuf

	Line No.	Total	Covered	Percent
Branches		44	44	100.00
TERNARY	330	2	2	100.00
TERNARY	335	2	2	100.00
TERNARY	344	2	2	100.00
TERNARY	371	2	2	100.00
TERNARY	396	2	2	100.00
CASE	169	23	23	100.00
IF	308	3	3	100.00
IF	315	3	3	100.00
IF	437	2	2	100.00
IF	440	3	3	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_otp_ctrl_1.0/rtl/otp_ctrl_part_unbuf.sv' or '../src/lowrisc_ip_otp_ctrl_1.0/rtl/otp_ctrl_part_unbuf.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	330	((tlul_rvalid_o && (tlul_rerror_o == '0))) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T3,T6
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	335	((otp_addr_sel == DigestAddrSel)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T3,T6

	LineNo.	Expression
-1-:	344	((otp_addr_sel == DigestAddrSel)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T3,T6

	LineNo.	Expression
-1-:	371	((~init_done_o)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	396	((digest_o != '0)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T3,T6
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	169	case (state_q)
-2-:	174	if (init_req_i)
-3-:	184	if (otp_gnt_i)
-4-:	193	if (otp_rvalid_i)
-5-:	197	if ((((!1'b1) && (otp_err_e'(otp_err_i) == MacroEccUncorrError)) || (otp_err_e'(otp_err_i) inside {NoError, MacroEccCorrError})))
-6-:	205	if ((otp_err_e'(otp_err_i) != NoError))
-7-:	219	if (tlul_req_i)
-8-:	233	if (((({tlul_addr_q, 2'b0} >= 11'b00001000000) && ({1'b0, tlul_addr_q, 2'b0} < PartEnd)) && prim_mubi_pkg::mubi8_test_false_strict(access_o.read_lock)))
-9-:	238	if (otp_gnt_i)
-10-:	254	if (otp_rvalid_i)
-11-:	258	if ((((!1'b1) && (otp_err_e'(otp_err_i) == MacroEccUncorrError)) || (otp_err_e'(otp_err_i) inside {NoError, MacroEccCorrError})))
-12-:	266	if ((otp_err_e'(otp_err_i) != NoError))
-13-:	282	if ((error_q == NoError))
-14-:	287	if (pending_tlul_error_q)
-15-:	290	if (tlul_req_i)

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	-9-	-10-	-11-	-12-	-13-	-14-	-15-	Status	Tests
ResetSt	1	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
ResetSt	0	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
InitSt	-	1	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
InitSt	-	0	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
InitWaitSt	-	-	1	1	1	-	-	-	-	-	-	-	-	-	Covered	T37,T59,T41
InitWaitSt	-	-	1	1	0	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
InitWaitSt	-	-	1	0	-	-	-	-	-	-	-	-	-	-	Covered	T128,T86,T90
InitWaitSt	-	-	0	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
IdleSt	-	-	-	-	-	1	-	-	-	-	-	-	-	-	Covered	T1,T3,T6
IdleSt	-	-	-	-	-	0	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
ReadSt	-	-	-	-	-	-	1	1	-	-	-	-	-	-	Covered	T1,T3,T6
ReadSt	-	-	-	-	-	-	1	0	-	-	-	-	-	-	Covered	T6,T93,T32
ReadSt	-	-	-	-	-	-	0	-	-	-	-	-	-	-	Covered	T1,T3,T6
ReadWaitSt	-	-	-	-	-	-	-	-	1	1	1	-	-	-	Covered	T29,T118,T130
ReadWaitSt	-	-	-	-	-	-	-	-	1	1	0	-	-	-	Covered	T1,T3,T6
ReadWaitSt	-	-	-	-	-	-	-	-	1	0	-	-	-	-	Covered	T119,T123,T132
ReadWaitSt	-	-	-	-	-	-	-	-	0	-	-	-	-	-	Covered	T1,T3,T6
ErrorSt	-	-	-	-	-	-	-	-	-	-	-	1	-	-	Covered	T20,T21,T22
ErrorSt	-	-	-	-	-	-	-	-	-	-	-	0	-	-	Covered	T7,T9,T37
ErrorSt	-	-	-	-	-	-	-	-	-	-	-	-	1	-	Covered	T7,T9,T107
ErrorSt	-	-	-	-	-	-	-	-	-	-	-	-	0	1	Covered	T7,T9,T107
ErrorSt	-	-	-	-	-	-	-	-	-	-	-	-	0	0	Covered	T7,T9,T37
default	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T20,T21,T22

	LineNo.	Expression
-1-:	308	if (ecc_err)
-2-:	310	if ((state_q != ErrorSt))

Branches:

-1-	-2-	Status	Tests
1	1	Covered	T126,T127,T133
1	0	Covered	T126,T127,T133
0	-	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	315	if (lc_ctrl_pkg::lc_tx_test_true_loose(escalate_en_i))
-2-:	318	if ((state_q != ErrorSt))

Branches:

-1-	-2-	Status	Tests
1	1	Covered	T7,T9,T37
1	0	Covered	T7,T9,T37
0	-	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	437	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	440	if ((!rst_ni))
-2-:	447	if (tlul_gnt_o)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T1,T3,T6
0	0	Covered	T1,T2,T3

---

Branch Coverage for Module : otp_ctrl_part_unbuf ( parameter Info=226594821,DigestOffset=1656,StateWidth=10 )
Branch Coverage for Module self-instances :

SCORE	BRANCH
98.33	100.00

tb.dut.gen_partitions[2].gen_unbuffered.u_part_unbuf

	Line No.	Total	Covered	Percent
Branches		44	44	100.00
TERNARY	330	2	2	100.00
TERNARY	335	2	2	100.00
TERNARY	344	2	2	100.00
TERNARY	371	2	2	100.00
TERNARY	396	2	2	100.00
CASE	169	23	23	100.00
IF	308	3	3	100.00
IF	315	3	3	100.00
IF	437	2	2	100.00
IF	440	3	3	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_otp_ctrl_1.0/rtl/otp_ctrl_part_unbuf.sv' or '../src/lowrisc_ip_otp_ctrl_1.0/rtl/otp_ctrl_part_unbuf.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	330	((tlul_rvalid_o && (tlul_rerror_o == '0))) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	335	((otp_addr_sel == DigestAddrSel)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	344	((otp_addr_sel == DigestAddrSel)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	371	((~init_done_o)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	396	((digest_o != '0)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	169	case (state_q)
-2-:	174	if (init_req_i)
-3-:	184	if (otp_gnt_i)
-4-:	193	if (otp_rvalid_i)
-5-:	197	if ((((!1'b1) && (otp_err_e'(otp_err_i) == MacroEccUncorrError)) || (otp_err_e'(otp_err_i) inside {NoError, MacroEccCorrError})))
-6-:	205	if ((otp_err_e'(otp_err_i) != NoError))
-7-:	219	if (tlul_req_i)
-8-:	233	if (((({tlul_addr_q, 2'b0} >= 11'b01101100000) && ({1'b0, tlul_addr_q, 2'b0} < PartEnd)) && prim_mubi_pkg::mubi8_test_false_strict(access_o.read_lock)))
-9-:	238	if (otp_gnt_i)
-10-:	254	if (otp_rvalid_i)
-11-:	258	if ((((!1'b1) && (otp_err_e'(otp_err_i) == MacroEccUncorrError)) || (otp_err_e'(otp_err_i) inside {NoError, MacroEccCorrError})))
-12-:	266	if ((otp_err_e'(otp_err_i) != NoError))
-13-:	282	if ((error_q == NoError))
-14-:	287	if (pending_tlul_error_q)
-15-:	290	if (tlul_req_i)

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	-9-	-10-	-11-	-12-	-13-	-14-	-15-	Status	Tests
ResetSt	1	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
ResetSt	0	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
InitSt	-	1	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
InitSt	-	0	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
InitWaitSt	-	-	1	1	1	-	-	-	-	-	-	-	-	-	Covered	T58,T59,T60
InitWaitSt	-	-	1	1	0	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
InitWaitSt	-	-	1	0	-	-	-	-	-	-	-	-	-	-	Covered	T37,T134,T135
InitWaitSt	-	-	0	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
IdleSt	-	-	-	-	-	1	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
IdleSt	-	-	-	-	-	0	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
ReadSt	-	-	-	-	-	-	1	1	-	-	-	-	-	-	Covered	T1,T2,T3
ReadSt	-	-	-	-	-	-	1	0	-	-	-	-	-	-	Covered	T93,T136,T137
ReadSt	-	-	-	-	-	-	0	-	-	-	-	-	-	-	Covered	T1,T2,T3
ReadWaitSt	-	-	-	-	-	-	-	-	1	1	1	-	-	-	Covered	T29,T118,T130
ReadWaitSt	-	-	-	-	-	-	-	-	1	1	0	-	-	-	Covered	T1,T2,T3
ReadWaitSt	-	-	-	-	-	-	-	-	1	0	-	-	-	-	Covered	T129,T138,T139
ReadWaitSt	-	-	-	-	-	-	-	-	0	-	-	-	-	-	Covered	T1,T2,T3
ErrorSt	-	-	-	-	-	-	-	-	-	-	-	1	-	-	Covered	T20,T21,T22
ErrorSt	-	-	-	-	-	-	-	-	-	-	-	0	-	-	Covered	T7,T9,T37
ErrorSt	-	-	-	-	-	-	-	-	-	-	-	-	1	-	Covered	T7,T9,T107
ErrorSt	-	-	-	-	-	-	-	-	-	-	-	-	0	1	Covered	T7,T9,T107
ErrorSt	-	-	-	-	-	-	-	-	-	-	-	-	0	0	Covered	T7,T9,T37
default	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T20,T21,T22

	LineNo.	Expression
-1-:	308	if (ecc_err)
-2-:	310	if ((state_q != ErrorSt))

Branches:

-1-	-2-	Status	Tests
1	1	Covered	T131,T125,T140
1	0	Covered	T131,T125,T140
0	-	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	315	if (lc_ctrl_pkg::lc_tx_test_true_loose(escalate_en_i))
-2-:	318	if ((state_q != ErrorSt))

Branches:

-1-	-2-	Status	Tests
1	1	Covered	T7,T9,T107
1	0	Covered	T7,T9,T37
0	-	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	437	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	440	if ((!rst_ni))
-2-:	447	if (tlul_gnt_o)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
0	0	Covered	T1,T2,T3

---

Branch Coverage for Module : otp_ctrl_part_unbuf ( parameter Info=8196,DigestOffset=56,StateWidth=10 )
Branch Coverage for Module self-instances :

SCORE	BRANCH
93.17	93.18

tb.dut.gen_partitions[0].gen_unbuffered.u_part_unbuf

	Line No.	Total	Covered	Percent
Branches		44	41	93.18
TERNARY	330	2	2	100.00
TERNARY	335	2	2	100.00
TERNARY	344	2	2	100.00
TERNARY	371	2	2	100.00
TERNARY	396	2	2	100.00
CASE	169	23	20	86.96
IF	308	3	3	100.00
IF	315	3	3	100.00
IF	437	2	2	100.00
IF	440	3	3	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_otp_ctrl_1.0/rtl/otp_ctrl_part_unbuf.sv' or '../src/lowrisc_ip_otp_ctrl_1.0/rtl/otp_ctrl_part_unbuf.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	330	((tlul_rvalid_o && (tlul_rerror_o == '0))) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T3,T5
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	335	((otp_addr_sel == DigestAddrSel)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T3,T5

	LineNo.	Expression
-1-:	344	((otp_addr_sel == DigestAddrSel)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T3,T5

	LineNo.	Expression
-1-:	371	((~init_done_o)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	396	((digest_o != '0)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T6,T107
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	169	case (state_q)
-2-:	174	if (init_req_i)
-3-:	184	if (otp_gnt_i)
-4-:	193	if (otp_rvalid_i)
-5-:	197	if ((((!1'b0) && (otp_err_e'(otp_err_i) == MacroEccUncorrError)) || (otp_err_e'(otp_err_i) inside {NoError, MacroEccCorrError})))
-6-:	205	if ((otp_err_e'(otp_err_i) != NoError))
-7-:	219	if (tlul_req_i)
-8-:	233	if (((({tlul_addr_q, 2'b0} >= 11'b0) && ({1'b0, tlul_addr_q, 2'b0} < PartEnd)) && prim_mubi_pkg::mubi8_test_false_strict(access_o.read_lock)))
-9-:	238	if (otp_gnt_i)
-10-:	254	if (otp_rvalid_i)
-11-:	258	if ((((!1'b0) && (otp_err_e'(otp_err_i) == MacroEccUncorrError)) || (otp_err_e'(otp_err_i) inside {NoError, MacroEccCorrError})))
-12-:	266	if ((otp_err_e'(otp_err_i) != NoError))
-13-:	282	if ((error_q == NoError))
-14-:	287	if (pending_tlul_error_q)
-15-:	290	if (tlul_req_i)

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	-9-	-10-	-11-	-12-	-13-	-14-	-15-	Status	Tests
ResetSt	1	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
ResetSt	0	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
InitSt	-	1	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
InitSt	-	0	-	-	-	-	-	-	-	-	-	-	-	-	Not Covered
InitWaitSt	-	-	1	1	1	-	-	-	-	-	-	-	-	-	Covered	T26,T23,T59
InitWaitSt	-	-	1	1	0	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
InitWaitSt	-	-	1	0	-	-	-	-	-	-	-	-	-	-	Not Covered
InitWaitSt	-	-	0	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
IdleSt	-	-	-	-	-	1	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
IdleSt	-	-	-	-	-	0	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
ReadSt	-	-	-	-	-	-	1	1	-	-	-	-	-	-	Covered	T1,T3,T5
ReadSt	-	-	-	-	-	-	1	0	-	-	-	-	-	-	Covered	T6,T93,T32
ReadSt	-	-	-	-	-	-	0	-	-	-	-	-	-	-	Covered	T1,T2,T3
ReadWaitSt	-	-	-	-	-	-	-	-	1	1	1	-	-	-	Covered	T29,T118,T119
ReadWaitSt	-	-	-	-	-	-	-	-	1	1	0	-	-	-	Covered	T1,T3,T5
ReadWaitSt	-	-	-	-	-	-	-	-	1	0	-	-	-	-	Not Covered
ReadWaitSt	-	-	-	-	-	-	-	-	0	-	-	-	-	-	Covered	T1,T3,T5
ErrorSt	-	-	-	-	-	-	-	-	-	-	-	1	-	-	Covered	T20,T21,T22
ErrorSt	-	-	-	-	-	-	-	-	-	-	-	0	-	-	Covered	T7,T9,T37
ErrorSt	-	-	-	-	-	-	-	-	-	-	-	-	1	-	Covered	T7,T9,T107
ErrorSt	-	-	-	-	-	-	-	-	-	-	-	-	0	1	Covered	T7,T9,T107
ErrorSt	-	-	-	-	-	-	-	-	-	-	-	-	0	0	Covered	T7,T9,T37
default	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T20,T21,T22

	LineNo.	Expression
-1-:	308	if (ecc_err)
-2-:	310	if ((state_q != ErrorSt))

Branches:

-1-	-2-	Status	Tests
1	1	Covered	T125,T126,T127
1	0	Covered	T125,T126,T127
0	-	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	315	if (lc_ctrl_pkg::lc_tx_test_true_loose(escalate_en_i))
-2-:	318	if ((state_q != ErrorSt))

Branches:

-1-	-2-	Status	Tests
1	1	Covered	T7,T9,T37
1	0	Covered	T7,T9,T37
0	-	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	437	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	440	if ((!rst_ni))
-2-:	447	if (tlul_gnt_o)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
0	0	Covered	T1,T2,T3

---

Assert Coverage for Module : otp_ctrl_part_unbuf

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	26	26	100.00	26	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	26	26	100.00	26	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AccessKnown_A	2147483647	2147483647	0	0
DigestKnown_A	2147483647	2147483647	0	0
DigestOffsetMustBeRepresentable_A	3471	3471	0	0
EccErrorState_A	2147483647	93082	0	0
ErrorKnown_A	2147483647	2147483647	0	0
FsmStateKnown_A	2147483647	2147483647	0	0
InitDoneKnown_A	2147483647	2147483647	0	0
InitReadLocksPartition_A	2147483647	1159337972	0	0
InitWriteLocksPartition_A	2147483647	1159337972	0	0
OffsetMustBeBlockAligned_A	3471	3471	0	0
OtpAddrKnown_A	2147483647	2147483647	0	0
OtpCmdKnown_A	2147483647	2147483647	0	0
OtpErrorState_A	2147483647	115	0	0
OtpReqKnown_A	2147483647	2147483647	0	0
OtpSizeKnown_A	2147483647	2147483647	0	0
OtpWdataKnown_A	2147483647	2147483647	0	0
ReadLockPropagation_A	2147483647	2147483647	0	0
SizeMustBeBlockAligned_A	3471	3471	0	0
TlulGntKnown_A	2147483647	2147483647	0	0
TlulRdataKnown_A	2147483647	2147483647	0	0
TlulReadOnReadLock_A	2147483647	33090	0	0
TlulRerrorKnown_A	2147483647	2147483647	0	0
TlulRvalidKnown_A	2147483647	2147483647	0	0
WriteLockPropagation_A	2147483647	3290978	0	0
gen_digest_write_lock.DigestWriteLocksPartition_A	2147483647	47634616	0	0
u_state_regs_A	2147483647	2147483647	0	0

AccessKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	220308	216153	0	0
T2	114054	111927	0	0
T3	330684	326901	0	0
T5	22497	20223	0	0
T6	152364	149394	0	0
T7	333273	333270	0	0
T8	24513	24249	0	0
T9	58245	57441	0	0
T10	32496	31890	0	0
T11	38265	37557	0	0

DigestKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	220308	216153	0	0
T2	114054	111927	0	0
T3	330684	326901	0	0
T5	22497	20223	0	0
T6	152364	149394	0	0
T7	333273	333270	0	0
T8	24513	24249	0	0
T9	58245	57441	0	0
T10	32496	31890	0	0
T11	38265	37557	0	0

DigestOffsetMustBeRepresentable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	3471	3471	0	0
T1	3	3	0	0
T2	3	3	0	0
T3	3	3	0	0
T5	3	3	0	0
T6	3	3	0	0
T7	3	3	0	0
T8	3	3	0	0
T9	3	3	0	0
T10	3	3	0	0
T11	3	3	0	0

EccErrorState_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	93082	0	0
T20	850632	0	0	0
T80	15324	0	0	0
T95	551829	0	0	0
T96	52693	0	0	0
T104	41425	0	0	0
T123	59997	0	0	0
T125	12073	6936	0	0
T126	29366	7158	0	0
T127	11537	4358	0	0
T131	15303	3498	0	0
T133	0	4720	0	0
T134	10859	0	0	0
T140	0	2220	0	0
T141	0	3283	0	0
T142	0	7599	0	0
T143	0	2166	0	0
T144	0	9957	0	0
T145	0	3115	0	0
T146	0	6648	0	0
T147	0	3431	0	0
T148	0	5832	0	0
T149	0	5428	0	0
T150	0	3996	0	0
T151	0	3107	0	0
T152	14219	0	0	0
T153	3926	0	0	0
T154	22123	0	0	0
T155	3629	0	0	0
T156	26704	0	0	0
T157	42338	0	0	0
T158	27968	0	0	0
T159	10552	0	0	0
T160	20269	0	0	0
T161	28702	0	0	0

ErrorKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	220308	216153	0	0
T2	114054	111927	0	0
T3	330684	326901	0	0
T5	22497	20223	0	0
T6	152364	149394	0	0
T7	333273	333270	0	0
T8	24513	24249	0	0
T9	58245	57441	0	0
T10	32496	31890	0	0
T11	38265	37557	0	0

FsmStateKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	220308	216153	0	0
T2	114054	111927	0	0
T3	330684	326901	0	0
T5	22497	20223	0	0
T6	152364	149394	0	0
T7	333273	333270	0	0
T8	24513	24249	0	0
T9	58245	57441	0	0
T10	32496	31890	0	0
T11	38265	37557	0	0

InitDoneKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	220308	216153	0	0
T2	114054	111927	0	0
T3	330684	326901	0	0
T5	22497	20223	0	0
T6	152364	149394	0	0
T7	333273	333270	0	0
T8	24513	24249	0	0
T9	58245	57441	0	0
T10	32496	31890	0	0
T11	38265	37557	0	0

InitReadLocksPartition_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1159337972	0	0
T1	220308	4788	0	0
T2	114054	1767	0	0
T3	330684	3093	0	0
T5	22497	1677	0	0
T6	152364	4023	0	0
T7	333273	2998873	0	0
T8	24513	216	0	0
T9	58245	30120	0	0
T10	32496	525	0	0
T11	38265	684	0	0

InitWriteLocksPartition_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1159337972	0	0
T1	220308	4788	0	0
T2	114054	1767	0	0
T3	330684	3093	0	0
T5	22497	1677	0	0
T6	152364	4023	0	0
T7	333273	2998873	0	0
T8	24513	216	0	0
T9	58245	30120	0	0
T10	32496	525	0	0
T11	38265	684	0	0

OffsetMustBeBlockAligned_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	3471	3471	0	0
T1	3	3	0	0
T2	3	3	0	0
T3	3	3	0	0
T5	3	3	0	0
T6	3	3	0	0
T7	3	3	0	0
T8	3	3	0	0
T9	3	3	0	0
T10	3	3	0	0
T11	3	3	0	0

OtpAddrKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	220308	216153	0	0
T2	114054	111927	0	0
T3	330684	326901	0	0
T5	22497	20223	0	0
T6	152364	149394	0	0
T7	333273	333270	0	0
T8	24513	24249	0	0
T9	58245	57441	0	0
T10	32496	31890	0	0
T11	38265	37557	0	0

OtpCmdKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	220308	216153	0	0
T2	114054	111927	0	0
T3	330684	326901	0	0
T5	22497	20223	0	0
T6	152364	149394	0	0
T7	333273	333270	0	0
T8	24513	24249	0	0
T9	58245	57441	0	0
T10	32496	31890	0	0
T11	38265	37557	0	0

OtpErrorState_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	115	0	0
T14	129965	0	0	0
T23	13191	0	0	0
T26	17138	0	0	0
T37	12955	1	0	0
T48	11194	0	0	0
T55	14469	0	0	0
T58	13271	0	0	0
T86	12422	1	0	0
T90	0	1	0	0
T93	43989	0	0	0
T94	64629	0	0	0
T101	73239	0	0	0
T102	432713	0	0	0
T103	70031	0	0	0
T107	14899	0	0	0
T108	10909	0	0	0
T119	37267	1	0	0
T121	12117	0	0	0
T123	0	1	0	0
T124	0	1	0	0
T128	15433	1	0	0
T129	0	1	0	0
T134	10859	1	0	0
T135	0	1	0	0
T162	0	1	0	0
T163	0	1	0	0
T164	0	1	0	0
T165	0	1	0	0
T166	0	1	0	0
T167	0	1	0	0
T168	0	1	0	0
T169	0	1	0	0
T170	0	1	0	0
T171	0	1	0	0
T172	5274	0	0	0

OtpReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	220308	216153	0	0
T2	114054	111927	0	0
T3	330684	326901	0	0
T5	22497	20223	0	0
T6	152364	149394	0	0
T7	333273	333270	0	0
T8	24513	24249	0	0
T9	58245	57441	0	0
T10	32496	31890	0	0
T11	38265	37557	0	0

OtpSizeKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	220308	216153	0	0
T2	114054	111927	0	0
T3	330684	326901	0	0
T5	22497	20223	0	0
T6	152364	149394	0	0
T7	333273	333270	0	0
T8	24513	24249	0	0
T9	58245	57441	0	0
T10	32496	31890	0	0
T11	38265	37557	0	0

OtpWdataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	220308	216153	0	0
T2	114054	111927	0	0
T3	330684	326901	0	0
T5	22497	20223	0	0
T6	152364	149394	0	0
T7	333273	333270	0	0
T8	24513	24249	0	0
T9	58245	57441	0	0
T10	32496	31890	0	0
T11	38265	37557	0	0

ReadLockPropagation_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	220308	26145	0	0
T2	114054	9653	0	0
T3	330684	84444	0	0
T5	22497	0	0	0
T6	152364	10105	0	0
T7	333273	328128	0	0
T8	24513	0	0	0
T9	58245	20888	0	0
T10	32496	0	0	0
T11	38265	0	0	0
T29	0	3466	0	0
T93	0	13120	0	0
T94	0	1095	0	0
T106	0	5480	0	0
T107	0	3383	0	0

SizeMustBeBlockAligned_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	3471	3471	0	0
T1	3	3	0	0
T2	3	3	0	0
T3	3	3	0	0
T5	3	3	0	0
T6	3	3	0	0
T7	3	3	0	0
T8	3	3	0	0
T9	3	3	0	0
T10	3	3	0	0
T11	3	3	0	0

TlulGntKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	220308	216153	0	0
T2	114054	111927	0	0
T3	330684	326901	0	0
T5	22497	20223	0	0
T6	152364	149394	0	0
T7	333273	333270	0	0
T8	24513	24249	0	0
T9	58245	57441	0	0
T10	32496	31890	0	0
T11	38265	37557	0	0

TlulRdataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	220308	216153	0	0
T2	114054	111927	0	0
T3	330684	326901	0	0
T5	22497	20223	0	0
T6	152364	149394	0	0
T7	333273	333270	0	0
T8	24513	24249	0	0
T9	58245	57441	0	0
T10	32496	31890	0	0
T11	38265	37557	0	0

TlulReadOnReadLock_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	33090	0	0
T1	220308	15	0	0
T2	114054	3	0	0
T3	330684	59	0	0
T5	22497	0	0	0
T6	152364	17	0	0
T7	333273	34	0	0
T8	24513	0	0	0
T9	58245	61	0	0
T10	32496	0	0	0
T11	38265	0	0	0
T29	0	44	0	0
T93	0	27	0	0
T95	0	93	0	0
T106	0	2	0	0
T107	0	51	0	0
T173	0	2	0	0
T174	0	15	0	0

TlulRerrorKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	220308	216153	0	0
T2	114054	111927	0	0
T3	330684	326901	0	0
T5	22497	20223	0	0
T6	152364	149394	0	0
T7	333273	333270	0	0
T8	24513	24249	0	0
T9	58245	57441	0	0
T10	32496	31890	0	0
T11	38265	37557	0	0

TlulRvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	220308	216153	0	0
T2	114054	111927	0	0
T3	330684	326901	0	0
T5	22497	20223	0	0
T6	152364	149394	0	0
T7	333273	333270	0	0
T8	24513	24249	0	0
T9	58245	57441	0	0
T10	32496	31890	0	0
T11	38265	37557	0	0

WriteLockPropagation_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	3290978	0	0
T1	220308	9179	0	0
T2	114054	0	0	0
T3	330684	13557	0	0
T5	22497	0	0	0
T6	152364	4619	0	0
T7	333273	0	0	0
T8	24513	0	0	0
T9	58245	0	0	0
T10	32496	0	0	0
T11	38265	0	0	0
T93	0	1407	0	0
T94	0	1004	0	0
T95	0	48417	0	0
T96	0	3048	0	0
T98	0	34333	0	0
T99	0	35378	0	0
T100	0	15357	0	0
T102	0	5060	0	0
T103	0	7806	0	0
T104	0	1050	0	0
T105	0	299	0	0
T175	0	2130	0	0
T176	0	3725	0	0
T177	0	2816	0	0
T178	0	3510	0	0

gen_digest_write_lock.DigestWriteLocksPartition_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	47634616	0	0
T1	220308	161789	0	0
T2	114054	5006	0	0
T3	330684	183203	0	0
T5	22497	0	0	0
T6	152364	81992	0	0
T7	333273	0	0	0
T8	24513	0	0	0
T9	58245	0	0	0
T10	32496	0	0	0
T11	38265	0	0	0
T37	0	2670	0	0
T93	0	67446	0	0
T94	0	87288	0	0
T95	0	324416	0	0
T98	0	44165	0	0
T99	0	239570	0	0
T100	0	36443	0	0
T101	0	35634	0	0
T102	0	18477	0	0
T103	0	42590	0	0
T106	0	4216	0	0
T107	0	8547	0	0
T173	0	94488	0	0
T174	0	5163	0	0

u_state_regs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	220308	216153	0	0
T2	114054	111927	0	0
T3	330684	326901	0	0
T5	22497	20223	0	0
T6	152364	149394	0	0
T7	333273	333270	0	0
T8	24513	24249	0	0
T9	58245	57441	0	0
T10	32496	31890	0	0
T11	38265	37557	0	0

Line Coverage for Instance : tb.dut.gen_partitions[0].gen_unbuffered.u_part_unbuf

	Line No.	Total	Covered	Percent
TOTAL		84	82	97.62
CONT_ASSIGN	137	1	1	100.00
ALWAYS	147	63	61	96.83
CONT_ASSIGN	328	1	1	100.00
CONT_ASSIGN	330	1	1	100.00
CONT_ASSIGN	335	1	1	100.00
CONT_ASSIGN	336	1	1	100.00
CONT_ASSIGN	340	1	1	100.00
CONT_ASSIGN	344	1	1	100.00
CONT_ASSIGN	371	1	1	100.00
CONT_ASSIGN	396	1	1	100.00
CONT_ASSIGN	430	1	1	100.00
ALWAYS	437	3	3	100.00
ALWAYS	440	8	8	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_otp_ctrl_1.0/rtl/otp_ctrl_part_unbuf.sv' or '../src/lowrisc_ip_otp_ctrl_1.0/rtl/otp_ctrl_part_unbuf.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
137	1	1
147	1	1
150	1	1
153	1	1
154	1	1
157	1	1
158	1	1
159	1	1
162	1	1
165	1	1
166	1	1
167	1	1
169	1	1
174	1	1
175	1	1
			MISSING_ELSE
183	1	1
184	1	1
185	1	1
			==> MISSING_ELSE
193	1	1
194	1	1
197	1	1
199	1	1
205	1	1
206	1	1
			MISSING_ELSE
209	0	1
210	0	1
			MISSING_ELSE
218	1	1
219	1	1
220	1	1
221	1	1
222	1	1
			MISSING_ELSE
231	1	1
233	1	1
236	1	1
237	1	1
238	1	1
239	1	1
			MISSING_ELSE
242	1	1
243	1	1
244	1	1
245	1	1
253	1	1
254	1	1
255	1	1
258	1	1
260	1	1
266	1	1
267	1	1
			MISSING_ELSE
270		excluded
			Exclude Annotation: VC_COV_UNR
271		excluded
			Exclude Annotation: VC_COV_UNR
273		excluded
			Exclude Annotation: VC_COV_UNR
			MISSING_ELSE
282	1	1
283		excluded
			Exclude Annotation: VC_COV_UNR
			MISSING_ELSE
287	1	1
288	1	1
289	1	1
290	1	1
291	1	1
292	1	1
			MISSING_ELSE
308	1	1
309	1	1
310	1	1
311	1	1
			MISSING_ELSE
			MISSING_ELSE
315	1	1
316	1	1
317	1	1
318	1	1
319	1	1
			MISSING_ELSE
			MISSING_ELSE
328	1	1
330	1	1
335	1	1
336	1	1
340	1	1
344	1	1
371	1	1
396	1	1
430	1	1
437	3	3
440	1	1
441	1	1
442	1	1
443	1	1
445	1	1
446	1	1
447	1	1
448	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.gen_partitions[0].gen_unbuffered.u_part_unbuf

	Total	Covered	Percent
Conditions	45	43	95.56
Logical	45	43	95.56
Non-Logical	0	0
Event	0	0

 LINE       197
 EXPRESSION ((((!1'b0)) && (otp_err_e'(otp_err_i) == MacroEccUncorrError)) || (otp_err_e'(otp_err_i) inside {NoError, MacroEccCorrError}))
             ------------------------------1------------------------------    -----------------------------2-----------------------------

-1-	-2-	Status	Tests
0	0	Not Covered
0	1	Covered	T1,T2,T3
1	0	Covered	T38,T124,T50

 LINE       197
 SUB-EXPRESSION (((!1'b0)) && (otp_err_e'(otp_err_i) == MacroEccUncorrError))
                 ----1----    -----------------------2----------------------

-1-	-2-	Status	Tests
-	0	Covered	T1,T2,T3
-	1	Covered	T38,T124,T50

 LINE       197
 SUB-EXPRESSION (otp_err_e'(otp_err_i) == MacroEccUncorrError)
                -----------------------1----------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T38,T124,T50

 LINE       205
 EXPRESSION (otp_err_e'(otp_err_i) != NoError)
            -----------------1----------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T26,T23,T59

 LINE       258
 EXPRESSION ((((!1'b0)) && (otp_err_e'(otp_err_i) == MacroEccUncorrError)) || (otp_err_e'(otp_err_i) inside {NoError, MacroEccCorrError}))
             ------------------------------1------------------------------    -----------------------------2-----------------------------

-1-	-2-	Status	Tests
0	0	Not Covered
0	1	Covered	T1,T3,T5
1	0	Covered	T118,T119,T102

 LINE       258
 SUB-EXPRESSION (((!1'b0)) && (otp_err_e'(otp_err_i) == MacroEccUncorrError))
                 ----1----    -----------------------2----------------------

-1-	-2-	Status	Tests
-	0	Covered	T1,T3,T5
-	1	Covered	T118,T119,T102

 LINE       258
 SUB-EXPRESSION (otp_err_e'(otp_err_i) == MacroEccUncorrError)
                -----------------------1----------------------

-1-	Status	Tests
0	Covered	T1,T3,T5
1	Covered	T118,T119,T102

 LINE       266
 EXPRESSION (otp_err_e'(otp_err_i) != NoError)
            -----------------1----------------

-1-	Status	Tests
0	Covered	T1,T3,T5
1	Covered	T29,T118,T119

 LINE       282
 EXPRESSION (error_q == NoError)
            ----------1---------

-1-	Status	Tests
0	Covered	T7,T9,T37
1	Covered	T20,T21,T22

 LINE       310
 EXPRESSION (state_q != ErrorSt)
            ----------1---------

-1-	Status	Tests
0	Covered	T125,T126,T127
1	Covered	T125,T126,T127

 LINE       318
 EXPRESSION (state_q != ErrorSt)
            ----------1---------

-1-	Status	Tests
0	Covered	T7,T9,T37
1	Covered	T7,T9,T37

 LINE       330
 EXPRESSION ((tlul_rvalid_o && (tlul_rerror_o == '0)) ? otp_rdata_i[31:0] : '0)
             --------------------1-------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T3,T5

 LINE       330
 SUB-EXPRESSION (tlul_rvalid_o && (tlul_rerror_o == '0))
                 ------1------    ----------2----------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T3,T5

 LINE       330
 SUB-EXPRESSION (tlul_rerror_o == '0)
                ----------1----------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       335
 EXPRESSION ((otp_addr_sel == DigestAddrSel) ? DigestOffset : ({tlul_addr_q, 2'b0}))
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T3,T5
1	Covered	T1,T2,T3

 LINE       335
 SUB-EXPRESSION (otp_addr_sel == DigestAddrSel)
                ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       344
 EXPRESSION 
 Number  Term
      1  (otp_addr_sel == DigestAddrSel) ? (2'((unsigned'(((otp_ctrl_pkg::ScrmblBlockWidth / otp_ctrl_pkg::OtpWidth) - 1))))) : (2'((unsigned'(((32 / otp_ctrl_pkg::OtpWidth) - 1))))))

-1-	Status	Tests
0	Covered	T1,T3,T5
1	Covered	T1,T2,T3

 LINE       344
 SUB-EXPRESSION (otp_addr_sel == DigestAddrSel)
                ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       371
 EXPRESSION (((~init_done_o)) ? MuBi8True : MuBi8False)
             --------1-------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       396
 EXPRESSION ((digest_o != '0) ? MuBi8True : MuBi8False)
             --------1-------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T6,T107

 LINE       396
 SUB-EXPRESSION (digest_o != '0)
                --------1-------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T6,T107

---

FSM Coverage for Instance : tb.dut.gen_partitions[0].gen_unbuffered.u_part_unbuf

Summary for FSM :: state_q

	Total	Covered	Percent
States	7	7	100.00	(Not included in score)
Transitions	13	10	76.92
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
ErrorSt	209	Covered	T16
IdleSt	199	Covered	T16
InitSt	175	Covered	T16
InitWaitSt	185	Covered	T16
ReadSt	221	Covered	T16
ReadWaitSt	239	Covered	T16
ResetSt	173	Covered	T16

transitions	Line No.	Covered	Tests
IdleSt->ErrorSt	309	Covered	T16
IdleSt->ReadSt	221	Covered	T16
InitSt->ErrorSt	309	Not Covered
InitSt->InitWaitSt	185	Covered	T16
InitWaitSt->ErrorSt	209	Covered	T16
InitWaitSt->IdleSt	199	Covered	T16
ReadSt->ErrorSt	309	Not Covered
ReadSt->IdleSt	242	Covered	T16
ReadSt->ReadWaitSt	239	Covered	T16
ReadWaitSt->ErrorSt	270	Not Covered
ReadWaitSt->IdleSt	260	Covered	T16
ResetSt->ErrorSt	309	Covered	T16
ResetSt->InitSt	175	Covered	T16

Summary for FSM :: error_q

	Total	Covered	Percent
States	5	5	100.00	(Not included in score)
Transitions	11	10	90.91
Sequences	0	0

State, Transition and Sequence Details for FSM :: error_q

---

states	Line No.	Covered	Tests
AccessError	243	Covered	T16
CheckFailError	311	Covered	T16
FsmStateError	283	Covered	T16
MacroEccCorrError	206	Covered	T16
NoError	220	Covered	T16

transitions	Line No.	Covered	Tests	Exclude Annotation
AccessError->CheckFailError	311	Excluded		VC_COV_UNR
AccessError->FsmStateError	319	Covered	T16
AccessError->MacroEccCorrError	206	Excluded		VC_COV_UNR
AccessError->NoError	220	Covered	T16
CheckFailError->AccessError	243	Excluded		VC_COV_UNR
CheckFailError->FsmStateError	319	Excluded		VC_COV_UNR
CheckFailError->MacroEccCorrError	206	Excluded		VC_COV_UNR
CheckFailError->NoError	220	Covered	T16
FsmStateError->AccessError	243	Excluded		VC_COV_UNR
FsmStateError->CheckFailError	311	Excluded		VC_COV_UNR
FsmStateError->MacroEccCorrError	206	Excluded		VC_COV_UNR
FsmStateError->NoError	220	Covered	T16
MacroEccCorrError->AccessError	243	Excluded		VC_COV_UNR
MacroEccCorrError->CheckFailError	311	Not Covered
MacroEccCorrError->FsmStateError	319	Covered	T16
MacroEccCorrError->NoError	220	Covered	T16
NoError->AccessError	243	Covered	T16
NoError->CheckFailError	311	Covered	T16
NoError->FsmStateError	283	Covered	T16
NoError->MacroEccCorrError	206	Covered	T16

---

Branch Coverage for Instance : tb.dut.gen_partitions[0].gen_unbuffered.u_part_unbuf

	Line No.	Total	Covered	Percent
Branches		44	41	93.18
TERNARY	330	2	2	100.00
TERNARY	335	2	2	100.00
TERNARY	344	2	2	100.00
TERNARY	371	2	2	100.00
TERNARY	396	2	2	100.00
CASE	169	23	20	86.96
IF	308	3	3	100.00
IF	315	3	3	100.00
IF	437	2	2	100.00
IF	440	3	3	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_otp_ctrl_1.0/rtl/otp_ctrl_part_unbuf.sv' or '../src/lowrisc_ip_otp_ctrl_1.0/rtl/otp_ctrl_part_unbuf.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	330	((tlul_rvalid_o && (tlul_rerror_o == '0))) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T3,T5
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	335	((otp_addr_sel == DigestAddrSel)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T3,T5

	LineNo.	Expression
-1-:	344	((otp_addr_sel == DigestAddrSel)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T3,T5

	LineNo.	Expression
-1-:	371	((~init_done_o)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	396	((digest_o != '0)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T6,T107
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	169	case (state_q)
-2-:	174	if (init_req_i)
-3-:	184	if (otp_gnt_i)
-4-:	193	if (otp_rvalid_i)
-5-:	197	if ((((!1'b0) && (otp_err_e'(otp_err_i) == MacroEccUncorrError)) || (otp_err_e'(otp_err_i) inside {NoError, MacroEccCorrError})))
-6-:	205	if ((otp_err_e'(otp_err_i) != NoError))
-7-:	219	if (tlul_req_i)
-8-:	233	if (((({tlul_addr_q, 2'b0} >= 11'b0) && ({1'b0, tlul_addr_q, 2'b0} < PartEnd)) && prim_mubi_pkg::mubi8_test_false_strict(access_o.read_lock)))
-9-:	238	if (otp_gnt_i)
-10-:	254	if (otp_rvalid_i)
-11-:	258	if ((((!1'b0) && (otp_err_e'(otp_err_i) == MacroEccUncorrError)) || (otp_err_e'(otp_err_i) inside {NoError, MacroEccCorrError})))
-12-:	266	if ((otp_err_e'(otp_err_i) != NoError))
-13-:	282	if ((error_q == NoError))
-14-:	287	if (pending_tlul_error_q)
-15-:	290	if (tlul_req_i)

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	-9-	-10-	-11-	-12-	-13-	-14-	-15-	Status	Tests
ResetSt	1	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
ResetSt	0	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
InitSt	-	1	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
InitSt	-	0	-	-	-	-	-	-	-	-	-	-	-	-	Not Covered
InitWaitSt	-	-	1	1	1	-	-	-	-	-	-	-	-	-	Covered	T26,T23,T59
InitWaitSt	-	-	1	1	0	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
InitWaitSt	-	-	1	0	-	-	-	-	-	-	-	-	-	-	Not Covered
InitWaitSt	-	-	0	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
IdleSt	-	-	-	-	-	1	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
IdleSt	-	-	-	-	-	0	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
ReadSt	-	-	-	-	-	-	1	1	-	-	-	-	-	-	Covered	T1,T3,T5
ReadSt	-	-	-	-	-	-	1	0	-	-	-	-	-	-	Covered	T6,T93,T32
ReadSt	-	-	-	-	-	-	0	-	-	-	-	-	-	-	Covered	T1,T2,T3
ReadWaitSt	-	-	-	-	-	-	-	-	1	1	1	-	-	-	Covered	T29,T118,T119
ReadWaitSt	-	-	-	-	-	-	-	-	1	1	0	-	-	-	Covered	T1,T3,T5
ReadWaitSt	-	-	-	-	-	-	-	-	1	0	-	-	-	-	Not Covered
ReadWaitSt	-	-	-	-	-	-	-	-	0	-	-	-	-	-	Covered	T1,T3,T5
ErrorSt	-	-	-	-	-	-	-	-	-	-	-	1	-	-	Covered	T20,T21,T22
ErrorSt	-	-	-	-	-	-	-	-	-	-	-	0	-	-	Covered	T7,T9,T37
ErrorSt	-	-	-	-	-	-	-	-	-	-	-	-	1	-	Covered	T7,T9,T107
ErrorSt	-	-	-	-	-	-	-	-	-	-	-	-	0	1	Covered	T7,T9,T107
ErrorSt	-	-	-	-	-	-	-	-	-	-	-	-	0	0	Covered	T7,T9,T37
default	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T20,T21,T22

	LineNo.	Expression
-1-:	308	if (ecc_err)
-2-:	310	if ((state_q != ErrorSt))

Branches:

-1-	-2-	Status	Tests
1	1	Covered	T125,T126,T127
1	0	Covered	T125,T126,T127
0	-	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	315	if (lc_ctrl_pkg::lc_tx_test_true_loose(escalate_en_i))
-2-:	318	if ((state_q != ErrorSt))

Branches:

-1-	-2-	Status	Tests
1	1	Covered	T7,T9,T37
1	0	Covered	T7,T9,T37
0	-	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	437	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	440	if ((!rst_ni))
-2-:	447	if (tlul_gnt_o)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
0	0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.gen_partitions[0].gen_unbuffered.u_part_unbuf

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	26	26	100.00	25	96.15
Cover properties	0	0		0
Cover sequences	0	0		0
Total	26	26	100.00	25	96.15

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AccessKnown_A	2147483647	2147483647	0	0
DigestKnown_A	2147483647	2147483647	0	0
DigestOffsetMustBeRepresentable_A	1157	1157	0	0
EccErrorState_A	2147483647	26748	0	0
ErrorKnown_A	2147483647	2147483647	0	0
FsmStateKnown_A	2147483647	2147483647	0	0
InitDoneKnown_A	2147483647	2147483647	0	0
InitReadLocksPartition_A	2147483647	386268318	0	0
InitWriteLocksPartition_A	2147483647	386268318	0	0
OffsetMustBeBlockAligned_A	1157	1157	0	0
OtpAddrKnown_A	2147483647	2147483647	0	0
OtpCmdKnown_A	2147483647	2147483647	0	0
OtpErrorState_A	2147483647	0	0	0
OtpReqKnown_A	2147483647	2147483647	0	0
OtpSizeKnown_A	2147483647	2147483647	0	0
OtpWdataKnown_A	2147483647	2147483647	0	0
ReadLockPropagation_A	2147483647	1250074276	0	0
SizeMustBeBlockAligned_A	1157	1157	0	0
TlulGntKnown_A	2147483647	2147483647	0	0
TlulRdataKnown_A	2147483647	2147483647	0	0
TlulReadOnReadLock_A	2147483647	10913	0	0
TlulRerrorKnown_A	2147483647	2147483647	0	0
TlulRvalidKnown_A	2147483647	2147483647	0	0
WriteLockPropagation_A	2147483647	351398	0	0
gen_digest_write_lock.DigestWriteLocksPartition_A	2147483647	6644542	0	0
u_state_regs_A	2147483647	2147483647	0	0

AccessKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	73436	72051	0	0
T2	38018	37309	0	0
T3	110228	108967	0	0
T5	7499	6741	0	0
T6	50788	49798	0	0
T7	111091	111090	0	0
T8	8171	8083	0	0
T9	19415	19147	0	0
T10	10832	10630	0	0
T11	12755	12519	0	0

DigestKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	73436	72051	0	0
T2	38018	37309	0	0
T3	110228	108967	0	0
T5	7499	6741	0	0
T6	50788	49798	0	0
T7	111091	111090	0	0
T8	8171	8083	0	0
T9	19415	19147	0	0
T10	10832	10630	0	0
T11	12755	12519	0	0

DigestOffsetMustBeRepresentable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1157	1157	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0

EccErrorState_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	26748	0	0
T123	59997	0	0	0
T125	12073	3468	0	0
T126	14683	3579	0	0
T127	0	2179	0	0
T134	10859	0	0	0
T142	0	2533	0	0
T144	0	3319	0	0
T146	0	2216	0	0
T147	0	3431	0	0
T148	0	2916	0	0
T151	0	3107	0	0
T153	3926	0	0	0
T154	22123	0	0	0
T155	3629	0	0	0
T156	13352	0	0	0
T157	21169	0	0	0
T158	13984	0	0	0

ErrorKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	73436	72051	0	0
T2	38018	37309	0	0
T3	110228	108967	0	0
T5	7499	6741	0	0
T6	50788	49798	0	0
T7	111091	111090	0	0
T8	8171	8083	0	0
T9	19415	19147	0	0
T10	10832	10630	0	0
T11	12755	12519	0	0

FsmStateKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	73436	72051	0	0
T2	38018	37309	0	0
T3	110228	108967	0	0
T5	7499	6741	0	0
T6	50788	49798	0	0
T7	111091	111090	0	0
T8	8171	8083	0	0
T9	19415	19147	0	0
T10	10832	10630	0	0
T11	12755	12519	0	0

InitDoneKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	73436	72051	0	0
T2	38018	37309	0	0
T3	110228	108967	0	0
T5	7499	6741	0	0
T6	50788	49798	0	0
T7	111091	111090	0	0
T8	8171	8083	0	0
T9	19415	19147	0	0
T10	10832	10630	0	0
T11	12755	12519	0	0

InitReadLocksPartition_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	386268318	0	0
T1	73436	1307	0	0
T2	38018	436	0	0
T3	110228	787	0	0
T5	7499	525	0	0
T6	50788	1120	0	0
T7	111091	999614	0	0
T8	8171	55	0	0
T9	19415	9989	0	0
T10	10832	141	0	0
T11	12755	177	0	0

InitWriteLocksPartition_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	386268318	0	0
T1	73436	1307	0	0
T2	38018	436	0	0
T3	110228	787	0	0
T5	7499	525	0	0
T6	50788	1120	0	0
T7	111091	999614	0	0
T8	8171	55	0	0
T9	19415	9989	0	0
T10	10832	141	0	0
T11	12755	177	0	0

OffsetMustBeBlockAligned_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1157	1157	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0

OtpAddrKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	73436	72051	0	0
T2	38018	37309	0	0
T3	110228	108967	0	0
T5	7499	6741	0	0
T6	50788	49798	0	0
T7	111091	111090	0	0
T8	8171	8083	0	0
T9	19415	19147	0	0
T10	10832	10630	0	0
T11	12755	12519	0	0

OtpCmdKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	73436	72051	0	0
T2	38018	37309	0	0
T3	110228	108967	0	0
T5	7499	6741	0	0
T6	50788	49798	0	0
T7	111091	111090	0	0
T8	8171	8083	0	0
T9	19415	19147	0	0
T10	10832	10630	0	0
T11	12755	12519	0	0

OtpErrorState_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	0	0	0

OtpReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	73436	72051	0	0
T2	38018	37309	0	0
T3	110228	108967	0	0
T5	7499	6741	0	0
T6	50788	49798	0	0
T7	111091	111090	0	0
T8	8171	8083	0	0
T9	19415	19147	0	0
T10	10832	10630	0	0
T11	12755	12519	0	0

OtpSizeKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	73436	72051	0	0
T2	38018	37309	0	0
T3	110228	108967	0	0
T5	7499	6741	0	0
T6	50788	49798	0	0
T7	111091	111090	0	0
T8	8171	8083	0	0
T9	19415	19147	0	0
T10	10832	10630	0	0
T11	12755	12519	0	0

OtpWdataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	73436	72051	0	0
T2	38018	37309	0	0
T3	110228	108967	0	0
T5	7499	6741	0	0
T6	50788	49798	0	0
T7	111091	111090	0	0
T8	8171	8083	0	0
T9	19415	19147	0	0
T10	10832	10630	0	0
T11	12755	12519	0	0

ReadLockPropagation_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1250074276	0	0
T1	73436	9948	0	0
T2	38018	5631	0	0
T3	110228	28753	0	0
T5	7499	0	0	0
T6	50788	3500	0	0
T7	111091	110712	0	0
T8	8171	0	0	0
T9	19415	0	0	0
T10	10832	0	0	0
T11	12755	0	0	0
T29	0	3466	0	0
T93	0	4227	0	0
T94	0	433	0	0
T106	0	2824	0	0
T107	0	877	0	0

SizeMustBeBlockAligned_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1157	1157	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0

TlulGntKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	73436	72051	0	0
T2	38018	37309	0	0
T3	110228	108967	0	0
T5	7499	6741	0	0
T6	50788	49798	0	0
T7	111091	111090	0	0
T8	8171	8083	0	0
T9	19415	19147	0	0
T10	10832	10630	0	0
T11	12755	12519	0	0

TlulRdataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	73436	72051	0	0
T2	38018	37309	0	0
T3	110228	108967	0	0
T5	7499	6741	0	0
T6	50788	49798	0	0
T7	111091	111090	0	0
T8	8171	8083	0	0
T9	19415	19147	0	0
T10	10832	10630	0	0
T11	12755	12519	0	0

TlulReadOnReadLock_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	10913	0	0
T1	73436	5	0	0
T2	38018	2	0	0
T3	110228	18	0	0
T5	7499	0	0	0
T6	50788	6	0	0
T7	111091	10	0	0
T8	8171	0	0	0
T9	19415	9	0	0
T10	10832	0	0	0
T11	12755	0	0	0
T29	0	15	0	0
T93	0	5	0	0
T106	0	2	0	0
T107	0	18	0	0

TlulRerrorKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	73436	72051	0	0
T2	38018	37309	0	0
T3	110228	108967	0	0
T5	7499	6741	0	0
T6	50788	49798	0	0
T7	111091	111090	0	0
T8	8171	8083	0	0
T9	19415	19147	0	0
T10	10832	10630	0	0
T11	12755	12519	0	0

TlulRvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	73436	72051	0	0
T2	38018	37309	0	0
T3	110228	108967	0	0
T5	7499	6741	0	0
T6	50788	49798	0	0
T7	111091	111090	0	0
T8	8171	8083	0	0
T9	19415	19147	0	0
T10	10832	10630	0	0
T11	12755	12519	0	0

WriteLockPropagation_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	351398	0	0
T1	73436	1634	0	0
T2	38018	0	0	0
T3	110228	0	0	0
T5	7499	0	0	0
T6	50788	2034	0	0
T7	111091	0	0	0
T8	8171	0	0	0
T9	19415	0	0	0
T10	10832	0	0	0
T11	12755	0	0	0
T98	0	3349	0	0
T99	0	3559	0	0
T100	0	11140	0	0
T103	0	1918	0	0
T175	0	2130	0	0
T176	0	3725	0	0
T177	0	2816	0	0
T178	0	3510	0	0

gen_digest_write_lock.DigestWriteLocksPartition_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	6644542	0	0
T1	73436	39036	0	0
T2	38018	0	0	0
T3	110228	0	0	0
T5	7499	0	0	0
T6	50788	15252	0	0
T7	111091	0	0	0
T8	8171	0	0	0
T9	19415	0	0	0
T10	10832	0	0	0
T11	12755	0	0	0
T95	0	50910	0	0
T98	0	44165	0	0
T99	0	239570	0	0
T100	0	36443	0	0
T101	0	35634	0	0
T102	0	18477	0	0
T103	0	42590	0	0
T107	0	2866	0	0

u_state_regs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	73436	72051	0	0
T2	38018	37309	0	0
T3	110228	108967	0	0
T5	7499	6741	0	0
T6	50788	49798	0	0
T7	111091	111090	0	0
T8	8171	8083	0	0
T9	19415	19147	0	0
T10	10832	10630	0	0
T11	12755	12519	0	0

Line Coverage for Instance : tb.dut.gen_partitions[1].gen_unbuffered.u_part_unbuf

	Line No.	Total	Covered	Percent
TOTAL		87	87	100.00
CONT_ASSIGN	137	1	1	100.00
ALWAYS	147	66	66	100.00
CONT_ASSIGN	328	1	1	100.00
CONT_ASSIGN	330	1	1	100.00
CONT_ASSIGN	335	1	1	100.00
CONT_ASSIGN	336	1	1	100.00
CONT_ASSIGN	340	1	1	100.00
CONT_ASSIGN	344	1	1	100.00
CONT_ASSIGN	371	1	1	100.00
CONT_ASSIGN	396	1	1	100.00
CONT_ASSIGN	430	1	1	100.00
ALWAYS	437	3	3	100.00
ALWAYS	440	8	8	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_otp_ctrl_1.0/rtl/otp_ctrl_part_unbuf.sv' or '../src/lowrisc_ip_otp_ctrl_1.0/rtl/otp_ctrl_part_unbuf.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
137	1	1
147	1	1
150	1	1
153	1	1
154	1	1
157	1	1
158	1	1
159	1	1
162	1	1
165	1	1
166	1	1
167	1	1
169	1	1
174	1	1
175	1	1
			MISSING_ELSE
183	1	1
184	1	1
185	1	1
			MISSING_ELSE
193	1	1
194	1	1
197	1	1
199	1	1
205	1	1
206	1	1
			MISSING_ELSE
209	1	1
210	1	1
			MISSING_ELSE
218	1	1
219	1	1
220	1	1
221	1	1
222	1	1
			MISSING_ELSE
231	1	1
233	1	1
236	1	1
237	1	1
238	1	1
239	1	1
			MISSING_ELSE
242	1	1
243	1	1
244	1	1
245	1	1
253	1	1
254	1	1
255	1	1
258	1	1
260	1	1
266	1	1
267	1	1
			MISSING_ELSE
270	1	1
271	1	1
273	1	1
			MISSING_ELSE
282	1	1
283		excluded
			Exclude Annotation: VC_COV_UNR
			MISSING_ELSE
287	1	1
288	1	1
289	1	1
290	1	1
291	1	1
292	1	1
			MISSING_ELSE
308	1	1
309	1	1
310	1	1
311	1	1
			MISSING_ELSE
			MISSING_ELSE
315	1	1
316	1	1
317	1	1
318	1	1
319	1	1
			MISSING_ELSE
			MISSING_ELSE
328	1	1
330	1	1
335	1	1
336	1	1
340	1	1
344	1	1
371	1	1
396	1	1
430	1	1
437	3	3
440	1	1
441	1	1
442	1	1
443	1	1
445	1	1
446	1	1
447	1	1
448	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.gen_partitions[1].gen_unbuffered.u_part_unbuf

	Total	Covered	Percent
Conditions	35	35	100.00
Logical	35	35	100.00
Non-Logical	0	0
Event	0	0

 LINE       197
 EXPRESSION ((((!1'b1) && (otp_err_e'(otp_err_i) == MacroEccUncorrError))) || (otp_err_e'(otp_err_i) inside {NoError, MacroEccCorrError}))
             ------------------------------1------------------------------    -----------------------------2-----------------------------

-1-	-2-	Status	Tests
0	0	Covered	T128,T86,T90
0	1	Covered	T1,T2,T3
1	0	Unreachable

 LINE       205
 EXPRESSION (otp_err_e'(otp_err_i) != NoError)
            -----------------1----------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T37,T59,T41

 LINE       258
 EXPRESSION ((((!1'b1) && (otp_err_e'(otp_err_i) == MacroEccUncorrError))) || (otp_err_e'(otp_err_i) inside {NoError, MacroEccCorrError}))
             ------------------------------1------------------------------    -----------------------------2-----------------------------

-1-	-2-	Status	Tests
0	0	Covered	T119,T123,T132
0	1	Covered	T1,T3,T6
1	0	Unreachable

 LINE       266
 EXPRESSION (otp_err_e'(otp_err_i) != NoError)
            -----------------1----------------

-1-	Status	Tests
0	Covered	T1,T3,T6
1	Covered	T29,T118,T130

 LINE       282
 EXPRESSION (error_q == NoError)
            ----------1---------

-1-	Status	Tests
0	Covered	T7,T9,T37
1	Covered	T20,T21,T22

 LINE       310
 EXPRESSION (state_q != ErrorSt)
            ----------1---------

-1-	Status	Tests
0	Covered	T126,T127,T133
1	Covered	T126,T127,T133

 LINE       318
 EXPRESSION (state_q != ErrorSt)
            ----------1---------

-1-	Status	Tests
0	Covered	T7,T9,T37
1	Covered	T7,T9,T37

 LINE       330
 EXPRESSION ((tlul_rvalid_o && (tlul_rerror_o == '0)) ? otp_rdata_i[31:0] : '0)
             --------------------1-------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T3,T6

 LINE       330
 SUB-EXPRESSION (tlul_rvalid_o && (tlul_rerror_o == '0))
                 ------1------    ----------2----------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T3,T6
1	1	Covered	T1,T3,T6

 LINE       330
 SUB-EXPRESSION (tlul_rerror_o == '0)
                ----------1----------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       335
 EXPRESSION ((otp_addr_sel == DigestAddrSel) ? DigestOffset : ({tlul_addr_q, 2'b0}))
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T3,T6
1	Covered	T1,T2,T3

 LINE       335
 SUB-EXPRESSION (otp_addr_sel == DigestAddrSel)
                ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       344
 EXPRESSION 
 Number  Term
      1  (otp_addr_sel == DigestAddrSel) ? (2'((unsigned'(((otp_ctrl_pkg::ScrmblBlockWidth / otp_ctrl_pkg::OtpWidth) - 1))))) : (2'((unsigned'(((32 / otp_ctrl_pkg::OtpWidth) - 1))))))

-1-	Status	Tests
0	Covered	T1,T3,T6
1	Covered	T1,T2,T3

 LINE       344
 SUB-EXPRESSION (otp_addr_sel == DigestAddrSel)
                ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       371
 EXPRESSION (((~init_done_o)) ? MuBi8True : MuBi8False)
             --------1-------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       396
 EXPRESSION ((digest_o != '0) ? MuBi8True : MuBi8False)
             --------1-------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T3,T6

 LINE       396
 SUB-EXPRESSION (digest_o != '0)
                --------1-------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T3,T6

---

FSM Coverage for Instance : tb.dut.gen_partitions[1].gen_unbuffered.u_part_unbuf

Summary for FSM :: state_q

	Total	Covered	Percent
States	7	7	100.00	(Not included in score)
Transitions	13	12	92.31
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
ErrorSt	209	Covered	T16
IdleSt	199	Covered	T16
InitSt	175	Covered	T16
InitWaitSt	185	Covered	T16
ReadSt	221	Covered	T16
ReadWaitSt	239	Covered	T16
ResetSt	173	Covered	T16

transitions	Line No.	Covered	Tests
IdleSt->ErrorSt	309	Covered	T16
IdleSt->ReadSt	221	Covered	T16
InitSt->ErrorSt	309	Covered	T16
InitSt->InitWaitSt	185	Covered	T16
InitWaitSt->ErrorSt	209	Covered	T16
InitWaitSt->IdleSt	199	Covered	T16
ReadSt->ErrorSt	309	Not Covered
ReadSt->IdleSt	242	Covered	T16
ReadSt->ReadWaitSt	239	Covered	T16
ReadWaitSt->ErrorSt	270	Covered	T16
ReadWaitSt->IdleSt	260	Covered	T16
ResetSt->ErrorSt	309	Covered	T16
ResetSt->InitSt	175	Covered	T16

Summary for FSM :: error_q

	Total	Covered	Percent
States	5	5	100.00	(Not included in score)
Transitions	11	10	90.91
Sequences	0	0

State, Transition and Sequence Details for FSM :: error_q

---

states	Line No.	Covered	Tests
AccessError	243	Covered	T16
CheckFailError	311	Covered	T16
FsmStateError	283	Covered	T16
MacroEccCorrError	206	Covered	T16
NoError	220	Covered	T16

transitions	Line No.	Covered	Tests	Exclude Annotation
AccessError->CheckFailError	311	Excluded		VC_COV_UNR
AccessError->FsmStateError	319	Covered	T16
AccessError->MacroEccCorrError	206	Excluded		VC_COV_UNR
AccessError->NoError	220	Covered	T16
CheckFailError->AccessError	243	Excluded		VC_COV_UNR
CheckFailError->FsmStateError	319	Excluded		VC_COV_UNR
CheckFailError->MacroEccCorrError	206	Excluded		VC_COV_UNR
CheckFailError->NoError	220	Covered	T16
FsmStateError->AccessError	243	Excluded		VC_COV_UNR
FsmStateError->CheckFailError	311	Excluded		VC_COV_UNR
FsmStateError->MacroEccCorrError	206	Excluded		VC_COV_UNR
FsmStateError->NoError	220	Covered	T16
MacroEccCorrError->AccessError	243	Excluded		VC_COV_UNR
MacroEccCorrError->CheckFailError	311	Not Covered
MacroEccCorrError->FsmStateError	319	Covered	T16
MacroEccCorrError->NoError	220	Covered	T16
NoError->AccessError	243	Covered	T16
NoError->CheckFailError	311	Covered	T16
NoError->FsmStateError	283	Covered	T16
NoError->MacroEccCorrError	206	Covered	T16

---

Branch Coverage for Instance : tb.dut.gen_partitions[1].gen_unbuffered.u_part_unbuf

	Line No.	Total	Covered	Percent
Branches		44	44	100.00
TERNARY	330	2	2	100.00
TERNARY	335	2	2	100.00
TERNARY	344	2	2	100.00
TERNARY	371	2	2	100.00
TERNARY	396	2	2	100.00
CASE	169	23	23	100.00
IF	308	3	3	100.00
IF	315	3	3	100.00
IF	437	2	2	100.00
IF	440	3	3	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_otp_ctrl_1.0/rtl/otp_ctrl_part_unbuf.sv' or '../src/lowrisc_ip_otp_ctrl_1.0/rtl/otp_ctrl_part_unbuf.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	330	((tlul_rvalid_o && (tlul_rerror_o == '0))) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T3,T6
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	335	((otp_addr_sel == DigestAddrSel)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T3,T6

	LineNo.	Expression
-1-:	344	((otp_addr_sel == DigestAddrSel)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T3,T6

	LineNo.	Expression
-1-:	371	((~init_done_o)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	396	((digest_o != '0)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T3,T6
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	169	case (state_q)
-2-:	174	if (init_req_i)
-3-:	184	if (otp_gnt_i)
-4-:	193	if (otp_rvalid_i)
-5-:	197	if ((((!1'b1) && (otp_err_e'(otp_err_i) == MacroEccUncorrError)) || (otp_err_e'(otp_err_i) inside {NoError, MacroEccCorrError})))
-6-:	205	if ((otp_err_e'(otp_err_i) != NoError))
-7-:	219	if (tlul_req_i)
-8-:	233	if (((({tlul_addr_q, 2'b0} >= 11'b00001000000) && ({1'b0, tlul_addr_q, 2'b0} < PartEnd)) && prim_mubi_pkg::mubi8_test_false_strict(access_o.read_lock)))
-9-:	238	if (otp_gnt_i)
-10-:	254	if (otp_rvalid_i)
-11-:	258	if ((((!1'b1) && (otp_err_e'(otp_err_i) == MacroEccUncorrError)) || (otp_err_e'(otp_err_i) inside {NoError, MacroEccCorrError})))
-12-:	266	if ((otp_err_e'(otp_err_i) != NoError))
-13-:	282	if ((error_q == NoError))
-14-:	287	if (pending_tlul_error_q)
-15-:	290	if (tlul_req_i)

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	-9-	-10-	-11-	-12-	-13-	-14-	-15-	Status	Tests
ResetSt	1	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
ResetSt	0	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
InitSt	-	1	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
InitSt	-	0	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
InitWaitSt	-	-	1	1	1	-	-	-	-	-	-	-	-	-	Covered	T37,T59,T41
InitWaitSt	-	-	1	1	0	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
InitWaitSt	-	-	1	0	-	-	-	-	-	-	-	-	-	-	Covered	T128,T86,T90
InitWaitSt	-	-	0	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
IdleSt	-	-	-	-	-	1	-	-	-	-	-	-	-	-	Covered	T1,T3,T6
IdleSt	-	-	-	-	-	0	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
ReadSt	-	-	-	-	-	-	1	1	-	-	-	-	-	-	Covered	T1,T3,T6
ReadSt	-	-	-	-	-	-	1	0	-	-	-	-	-	-	Covered	T6,T93,T32
ReadSt	-	-	-	-	-	-	0	-	-	-	-	-	-	-	Covered	T1,T3,T6
ReadWaitSt	-	-	-	-	-	-	-	-	1	1	1	-	-	-	Covered	T29,T118,T130
ReadWaitSt	-	-	-	-	-	-	-	-	1	1	0	-	-	-	Covered	T1,T3,T6
ReadWaitSt	-	-	-	-	-	-	-	-	1	0	-	-	-	-	Covered	T119,T123,T132
ReadWaitSt	-	-	-	-	-	-	-	-	0	-	-	-	-	-	Covered	T1,T3,T6
ErrorSt	-	-	-	-	-	-	-	-	-	-	-	1	-	-	Covered	T20,T21,T22
ErrorSt	-	-	-	-	-	-	-	-	-	-	-	0	-	-	Covered	T7,T9,T37
ErrorSt	-	-	-	-	-	-	-	-	-	-	-	-	1	-	Covered	T7,T9,T107
ErrorSt	-	-	-	-	-	-	-	-	-	-	-	-	0	1	Covered	T7,T9,T107
ErrorSt	-	-	-	-	-	-	-	-	-	-	-	-	0	0	Covered	T7,T9,T37
default	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T20,T21,T22

	LineNo.	Expression
-1-:	308	if (ecc_err)
-2-:	310	if ((state_q != ErrorSt))

Branches:

-1-	-2-	Status	Tests
1	1	Covered	T126,T127,T133
1	0	Covered	T126,T127,T133
0	-	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	315	if (lc_ctrl_pkg::lc_tx_test_true_loose(escalate_en_i))
-2-:	318	if ((state_q != ErrorSt))

Branches:

-1-	-2-	Status	Tests
1	1	Covered	T7,T9,T37
1	0	Covered	T7,T9,T37
0	-	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	437	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	440	if ((!rst_ni))
-2-:	447	if (tlul_gnt_o)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T1,T3,T6
0	0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.gen_partitions[1].gen_unbuffered.u_part_unbuf

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	26	26	100.00	26	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	26	26	100.00	26	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AccessKnown_A	2147483647	2147483647	0	0
DigestKnown_A	2147483647	2147483647	0	0
DigestOffsetMustBeRepresentable_A	1157	1157	0	0
EccErrorState_A	2147483647	27978	0	0
ErrorKnown_A	2147483647	2147483647	0	0
FsmStateKnown_A	2147483647	2147483647	0	0
InitDoneKnown_A	2147483647	2147483647	0	0
InitReadLocksPartition_A	2147483647	386446339	0	0
InitWriteLocksPartition_A	2147483647	386446339	0	0
OffsetMustBeBlockAligned_A	1157	1157	0	0
OtpAddrKnown_A	2147483647	2147483647	0	0
OtpCmdKnown_A	2147483647	2147483647	0	0
OtpErrorState_A	2147483647	60	0	0
OtpReqKnown_A	2147483647	2147483647	0	0
OtpSizeKnown_A	2147483647	2147483647	0	0
OtpWdataKnown_A	2147483647	2147483647	0	0
ReadLockPropagation_A	2147483647	1208907203	0	0
SizeMustBeBlockAligned_A	1157	1157	0	0
TlulGntKnown_A	2147483647	2147483647	0	0
TlulRdataKnown_A	2147483647	2147483647	0	0
TlulReadOnReadLock_A	2147483647	11040	0	0
TlulRerrorKnown_A	2147483647	2147483647	0	0
TlulRvalidKnown_A	2147483647	2147483647	0	0
WriteLockPropagation_A	2147483647	1590318	0	0
gen_digest_write_lock.DigestWriteLocksPartition_A	2147483647	21185675	0	0
u_state_regs_A	2147483647	2147483647	0	0

AccessKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	73436	72051	0	0
T2	38018	37309	0	0
T3	110228	108967	0	0
T5	7499	6741	0	0
T6	50788	49798	0	0
T7	111091	111090	0	0
T8	8171	8083	0	0
T9	19415	19147	0	0
T10	10832	10630	0	0
T11	12755	12519	0	0

DigestKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	73436	72051	0	0
T2	38018	37309	0	0
T3	110228	108967	0	0
T5	7499	6741	0	0
T6	50788	49798	0	0
T7	111091	111090	0	0
T8	8171	8083	0	0
T9	19415	19147	0	0
T10	10832	10630	0	0
T11	12755	12519	0	0

DigestOffsetMustBeRepresentable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1157	1157	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0

EccErrorState_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	27978	0	0
T20	850632	0	0	0
T80	15324	0	0	0
T126	14683	3579	0	0
T127	11537	2179	0	0
T133	0	2360	0	0
T142	0	2533	0	0
T143	0	2166	0	0
T144	0	3319	0	0
T146	0	2216	0	0
T148	0	2916	0	0
T149	0	2714	0	0
T150	0	3996	0	0
T156	13352	0	0	0
T157	21169	0	0	0
T158	13984	0	0	0
T159	10552	0	0	0
T160	20269	0	0	0
T161	28702	0	0	0

ErrorKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	73436	72051	0	0
T2	38018	37309	0	0
T3	110228	108967	0	0
T5	7499	6741	0	0
T6	50788	49798	0	0
T7	111091	111090	0	0
T8	8171	8083	0	0
T9	19415	19147	0	0
T10	10832	10630	0	0
T11	12755	12519	0	0

FsmStateKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	73436	72051	0	0
T2	38018	37309	0	0
T3	110228	108967	0	0
T5	7499	6741	0	0
T6	50788	49798	0	0
T7	111091	111090	0	0
T8	8171	8083	0	0
T9	19415	19147	0	0
T10	10832	10630	0	0
T11	12755	12519	0	0

InitDoneKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	73436	72051	0	0
T2	38018	37309	0	0
T3	110228	108967	0	0
T5	7499	6741	0	0
T6	50788	49798	0	0
T7	111091	111090	0	0
T8	8171	8083	0	0
T9	19415	19147	0	0
T10	10832	10630	0	0
T11	12755	12519	0	0

InitReadLocksPartition_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	386446339	0	0
T1	73436	1596	0	0
T2	38018	589	0	0
T3	110228	1034	0	0
T5	7499	559	0	0
T6	50788	1341	0	0
T7	111091	999624	0	0
T8	8171	72	0	0
T9	19415	10040	0	0
T10	10832	175	0	0
T11	12755	228	0	0

InitWriteLocksPartition_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	386446339	0	0
T1	73436	1596	0	0
T2	38018	589	0	0
T3	110228	1034	0	0
T5	7499	559	0	0
T6	50788	1341	0	0
T7	111091	999624	0	0
T8	8171	72	0	0
T9	19415	10040	0	0
T10	10832	175	0	0
T11	12755	228	0	0

OffsetMustBeBlockAligned_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1157	1157	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0

OtpAddrKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	73436	72051	0	0
T2	38018	37309	0	0
T3	110228	108967	0	0
T5	7499	6741	0	0
T6	50788	49798	0	0
T7	111091	111090	0	0
T8	8171	8083	0	0
T9	19415	19147	0	0
T10	10832	10630	0	0
T11	12755	12519	0	0

OtpCmdKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	73436	72051	0	0
T2	38018	37309	0	0
T3	110228	108967	0	0
T5	7499	6741	0	0
T6	50788	49798	0	0
T7	111091	111090	0	0
T8	8171	8083	0	0
T9	19415	19147	0	0
T10	10832	10630	0	0
T11	12755	12519	0	0

OtpErrorState_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	60	0	0
T14	129965	0	0	0
T55	14469	0	0	0
T86	12422	1	0	0
T90	0	1	0	0
T101	73239	0	0	0
T102	432713	0	0	0
T103	70031	0	0	0
T119	37267	1	0	0
T121	12117	0	0	0
T123	0	1	0	0
T128	15433	1	0	0
T162	0	1	0	0
T163	0	1	0	0
T164	0	1	0	0
T165	0	1	0	0
T166	0	1	0	0
T172	5274	0	0	0

OtpReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	73436	72051	0	0
T2	38018	37309	0	0
T3	110228	108967	0	0
T5	7499	6741	0	0
T6	50788	49798	0	0
T7	111091	111090	0	0
T8	8171	8083	0	0
T9	19415	19147	0	0
T10	10832	10630	0	0
T11	12755	12519	0	0

OtpSizeKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	73436	72051	0	0
T2	38018	37309	0	0
T3	110228	108967	0	0
T5	7499	6741	0	0
T6	50788	49798	0	0
T7	111091	111090	0	0
T8	8171	8083	0	0
T9	19415	19147	0	0
T10	10832	10630	0	0
T11	12755	12519	0	0

OtpWdataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	73436	72051	0	0
T2	38018	37309	0	0
T3	110228	108967	0	0
T5	7499	6741	0	0
T6	50788	49798	0	0
T7	111091	111090	0	0
T8	8171	8083	0	0
T9	19415	19147	0	0
T10	10832	10630	0	0
T11	12755	12519	0	0

ReadLockPropagation_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1208907203	0	0
T1	73436	7925	0	0
T2	38018	2305	0	0
T3	110228	25975	0	0
T5	7499	0	0	0
T6	50788	3023	0	0
T7	111091	106714	0	0
T8	8171	0	0	0
T9	19415	9073	0	0
T10	10832	0	0	0
T11	12755	0	0	0
T93	0	4411	0	0
T94	0	490	0	0
T106	0	1329	0	0
T107	0	1257	0	0

SizeMustBeBlockAligned_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1157	1157	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0

TlulGntKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	73436	72051	0	0
T2	38018	37309	0	0
T3	110228	108967	0	0
T5	7499	6741	0	0
T6	50788	49798	0	0
T7	111091	111090	0	0
T8	8171	8083	0	0
T9	19415	19147	0	0
T10	10832	10630	0	0
T11	12755	12519	0	0

TlulRdataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	73436	72051	0	0
T2	38018	37309	0	0
T3	110228	108967	0	0
T5	7499	6741	0	0
T6	50788	49798	0	0
T7	111091	111090	0	0
T8	8171	8083	0	0
T9	19415	19147	0	0
T10	10832	10630	0	0
T11	12755	12519	0	0

TlulReadOnReadLock_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	11040	0	0
T1	73436	4	0	0
T2	38018	0	0	0
T3	110228	23	0	0
T5	7499	0	0	0
T6	50788	6	0	0
T7	111091	7	0	0
T8	8171	0	0	0
T9	19415	24	0	0
T10	10832	0	0	0
T11	12755	0	0	0
T29	0	15	0	0
T93	0	13	0	0
T95	0	93	0	0
T107	0	17	0	0
T174	0	15	0	0

TlulRerrorKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	73436	72051	0	0
T2	38018	37309	0	0
T3	110228	108967	0	0
T5	7499	6741	0	0
T6	50788	49798	0	0
T7	111091	111090	0	0
T8	8171	8083	0	0
T9	19415	19147	0	0
T10	10832	10630	0	0
T11	12755	12519	0	0

TlulRvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	73436	72051	0	0
T2	38018	37309	0	0
T3	110228	108967	0	0
T5	7499	6741	0	0
T6	50788	49798	0	0
T7	111091	111090	0	0
T8	8171	8083	0	0
T9	19415	19147	0	0
T10	10832	10630	0	0
T11	12755	12519	0	0

WriteLockPropagation_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1590318	0	0
T1	73436	1563	0	0
T2	38018	0	0	0
T3	110228	4889	0	0
T5	7499	0	0	0
T6	50788	503	0	0
T7	111091	0	0	0
T8	8171	0	0	0
T9	19415	0	0	0
T10	10832	0	0	0
T11	12755	0	0	0
T95	0	15149	0	0
T98	0	20764	0	0
T99	0	3777	0	0
T100	0	4217	0	0
T102	0	5060	0	0
T103	0	5888	0	0
T105	0	299	0	0

gen_digest_write_lock.DigestWriteLocksPartition_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	21185675	0	0
T1	73436	61504	0	0
T2	38018	0	0	0
T3	110228	91712	0	0
T5	7499	0	0	0
T6	50788	33455	0	0
T7	111091	0	0	0
T8	8171	0	0	0
T9	19415	0	0	0
T10	10832	0	0	0
T11	12755	0	0	0
T93	0	33808	0	0
T94	0	49782	0	0
T95	0	273506	0	0
T106	0	4216	0	0
T107	0	2849	0	0
T173	0	28740	0	0
T174	0	2590	0	0

u_state_regs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	73436	72051	0	0
T2	38018	37309	0	0
T3	110228	108967	0	0
T5	7499	6741	0	0
T6	50788	49798	0	0
T7	111091	111090	0	0
T8	8171	8083	0	0
T9	19415	19147	0	0
T10	10832	10630	0	0
T11	12755	12519	0	0

Line Coverage for Instance : tb.dut.gen_partitions[2].gen_unbuffered.u_part_unbuf

	Line No.	Total	Covered	Percent
TOTAL		87	87	100.00
CONT_ASSIGN	137	1	1	100.00
ALWAYS	147	66	66	100.00
CONT_ASSIGN	328	1	1	100.00
CONT_ASSIGN	330	1	1	100.00
CONT_ASSIGN	335	1	1	100.00
CONT_ASSIGN	336	1	1	100.00
CONT_ASSIGN	340	1	1	100.00
CONT_ASSIGN	344	1	1	100.00
CONT_ASSIGN	371	1	1	100.00
CONT_ASSIGN	396	1	1	100.00
CONT_ASSIGN	430	1	1	100.00
ALWAYS	437	3	3	100.00
ALWAYS	440	8	8	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_otp_ctrl_1.0/rtl/otp_ctrl_part_unbuf.sv' or '../src/lowrisc_ip_otp_ctrl_1.0/rtl/otp_ctrl_part_unbuf.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
137	1	1
147	1	1
150	1	1
153	1	1
154	1	1
157	1	1
158	1	1
159	1	1
162	1	1
165	1	1
166	1	1
167	1	1
169	1	1
174	1	1
175	1	1
			MISSING_ELSE
183	1	1
184	1	1
185	1	1
			MISSING_ELSE
193	1	1
194	1	1
197	1	1
199	1	1
205	1	1
206	1	1
			MISSING_ELSE
209	1	1
210	1	1
			MISSING_ELSE
218	1	1
219	1	1
220	1	1
221	1	1
222	1	1
			MISSING_ELSE
231	1	1
233	1	1
236	1	1
237	1	1
238	1	1
239	1	1
			MISSING_ELSE
242	1	1
243	1	1
244	1	1
245	1	1
253	1	1
254	1	1
255	1	1
258	1	1
260	1	1
266	1	1
267	1	1
			MISSING_ELSE
270	1	1
271	1	1
273	1	1
			MISSING_ELSE
282	1	1
283		excluded
			Exclude Annotation: VC_COV_UNR
			MISSING_ELSE
287	1	1
288	1	1
289	1	1
290	1	1
291	1	1
292	1	1
			MISSING_ELSE
308	1	1
309	1	1
310	1	1
311	1	1
			MISSING_ELSE
			MISSING_ELSE
315	1	1
316	1	1
317	1	1
318	1	1
319	1	1
			MISSING_ELSE
			MISSING_ELSE
328	1	1
330	1	1
335	1	1
336	1	1
340	1	1
344	1	1
371	1	1
396	1	1
430	1	1
437	3	3
440	1	1
441	1	1
442	1	1
443	1	1
445	1	1
446	1	1
447	1	1
448	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.gen_partitions[2].gen_unbuffered.u_part_unbuf

	Total	Covered	Percent
Conditions	35	35	100.00
Logical	35	35	100.00
Non-Logical	0	0
Event	0	0

 LINE       197
 EXPRESSION ((((!1'b1) && (otp_err_e'(otp_err_i) == MacroEccUncorrError))) || (otp_err_e'(otp_err_i) inside {NoError, MacroEccCorrError}))
             ------------------------------1------------------------------    -----------------------------2-----------------------------

-1-	-2-	Status	Tests
0	0	Covered	T37,T134,T135
0	1	Covered	T1,T2,T3
1	0	Unreachable

 LINE       205
 EXPRESSION (otp_err_e'(otp_err_i) != NoError)
            -----------------1----------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T58,T59,T60

 LINE       258
 EXPRESSION ((((!1'b1) && (otp_err_e'(otp_err_i) == MacroEccUncorrError))) || (otp_err_e'(otp_err_i) inside {NoError, MacroEccCorrError}))
             ------------------------------1------------------------------    -----------------------------2-----------------------------

-1-	-2-	Status	Tests
0	0	Covered	T129,T138,T139
0	1	Covered	T1,T2,T3
1	0	Unreachable

 LINE       266
 EXPRESSION (otp_err_e'(otp_err_i) != NoError)
            -----------------1----------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T29,T118,T130

 LINE       282
 EXPRESSION (error_q == NoError)
            ----------1---------

-1-	Status	Tests
0	Covered	T7,T9,T37
1	Covered	T20,T21,T22

 LINE       310
 EXPRESSION (state_q != ErrorSt)
            ----------1---------

-1-	Status	Tests
0	Covered	T131,T125,T140
1	Covered	T131,T125,T140

 LINE       318
 EXPRESSION (state_q != ErrorSt)
            ----------1---------

-1-	Status	Tests
0	Covered	T7,T9,T37
1	Covered	T7,T9,T107

 LINE       330
 EXPRESSION ((tlul_rvalid_o && (tlul_rerror_o == '0)) ? otp_rdata_i[31:0] : '0)
             --------------------1-------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       330
 SUB-EXPRESSION (tlul_rvalid_o && (tlul_rerror_o == '0))
                 ------1------    ----------2----------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       330
 SUB-EXPRESSION (tlul_rerror_o == '0)
                ----------1----------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       335
 EXPRESSION ((otp_addr_sel == DigestAddrSel) ? DigestOffset : ({tlul_addr_q, 2'b0}))
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       335
 SUB-EXPRESSION (otp_addr_sel == DigestAddrSel)
                ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       344
 EXPRESSION 
 Number  Term
      1  (otp_addr_sel == DigestAddrSel) ? (2'((unsigned'(((otp_ctrl_pkg::ScrmblBlockWidth / otp_ctrl_pkg::OtpWidth) - 1))))) : (2'((unsigned'(((32 / otp_ctrl_pkg::OtpWidth) - 1))))))

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       344
 SUB-EXPRESSION (otp_addr_sel == DigestAddrSel)
                ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       371
 EXPRESSION (((~init_done_o)) ? MuBi8True : MuBi8False)
             --------1-------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       396
 EXPRESSION ((digest_o != '0) ? MuBi8True : MuBi8False)
             --------1-------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       396
 SUB-EXPRESSION (digest_o != '0)
                --------1-------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

---

FSM Coverage for Instance : tb.dut.gen_partitions[2].gen_unbuffered.u_part_unbuf

Summary for FSM :: state_q

	Total	Covered	Percent
States	7	7	100.00	(Not included in score)
Transitions	13	12	92.31
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
ErrorSt	209	Covered	T16
IdleSt	199	Covered	T16
InitSt	175	Covered	T16
InitWaitSt	185	Covered	T16
ReadSt	221	Covered	T16
ReadWaitSt	239	Covered	T16
ResetSt	173	Covered	T16

transitions	Line No.	Covered	Tests
IdleSt->ErrorSt	309	Covered	T16
IdleSt->ReadSt	221	Covered	T16
InitSt->ErrorSt	309	Covered	T16
InitSt->InitWaitSt	185	Covered	T16
InitWaitSt->ErrorSt	209	Covered	T16
InitWaitSt->IdleSt	199	Covered	T16
ReadSt->ErrorSt	309	Not Covered
ReadSt->IdleSt	242	Covered	T16
ReadSt->ReadWaitSt	239	Covered	T16
ReadWaitSt->ErrorSt	270	Covered	T16
ReadWaitSt->IdleSt	260	Covered	T16
ResetSt->ErrorSt	309	Covered	T16
ResetSt->InitSt	175	Covered	T16

Summary for FSM :: error_q

	Total	Covered	Percent
States	5	5	100.00	(Not included in score)
Transitions	11	10	90.91
Sequences	0	0

State, Transition and Sequence Details for FSM :: error_q

---

states	Line No.	Covered	Tests
AccessError	243	Covered	T16
CheckFailError	311	Covered	T16
FsmStateError	283	Covered	T16
MacroEccCorrError	206	Covered	T16
NoError	220	Covered	T16

transitions	Line No.	Covered	Tests	Exclude Annotation
AccessError->CheckFailError	311	Excluded		VC_COV_UNR
AccessError->FsmStateError	319	Covered	T16
AccessError->MacroEccCorrError	206	Excluded		VC_COV_UNR
AccessError->NoError	220	Covered	T16
CheckFailError->AccessError	243	Excluded		VC_COV_UNR
CheckFailError->FsmStateError	319	Excluded		VC_COV_UNR
CheckFailError->MacroEccCorrError	206	Excluded		VC_COV_UNR
CheckFailError->NoError	220	Covered	T16
FsmStateError->AccessError	243	Excluded		VC_COV_UNR
FsmStateError->CheckFailError	311	Excluded		VC_COV_UNR
FsmStateError->MacroEccCorrError	206	Excluded		VC_COV_UNR
FsmStateError->NoError	220	Covered	T16
MacroEccCorrError->AccessError	243	Excluded		VC_COV_UNR
MacroEccCorrError->CheckFailError	311	Not Covered
MacroEccCorrError->FsmStateError	319	Covered	T16
MacroEccCorrError->NoError	220	Covered	T16
NoError->AccessError	243	Covered	T16
NoError->CheckFailError	311	Covered	T16
NoError->FsmStateError	283	Covered	T16
NoError->MacroEccCorrError	206	Covered	T16

---

Branch Coverage for Instance : tb.dut.gen_partitions[2].gen_unbuffered.u_part_unbuf

	Line No.	Total	Covered	Percent
Branches		44	44	100.00
TERNARY	330	2	2	100.00
TERNARY	335	2	2	100.00
TERNARY	344	2	2	100.00
TERNARY	371	2	2	100.00
TERNARY	396	2	2	100.00
CASE	169	23	23	100.00
IF	308	3	3	100.00
IF	315	3	3	100.00
IF	437	2	2	100.00
IF	440	3	3	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_otp_ctrl_1.0/rtl/otp_ctrl_part_unbuf.sv' or '../src/lowrisc_ip_otp_ctrl_1.0/rtl/otp_ctrl_part_unbuf.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	330	((tlul_rvalid_o && (tlul_rerror_o == '0))) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	335	((otp_addr_sel == DigestAddrSel)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	344	((otp_addr_sel == DigestAddrSel)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	371	((~init_done_o)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	396	((digest_o != '0)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	169	case (state_q)
-2-:	174	if (init_req_i)
-3-:	184	if (otp_gnt_i)
-4-:	193	if (otp_rvalid_i)
-5-:	197	if ((((!1'b1) && (otp_err_e'(otp_err_i) == MacroEccUncorrError)) || (otp_err_e'(otp_err_i) inside {NoError, MacroEccCorrError})))
-6-:	205	if ((otp_err_e'(otp_err_i) != NoError))
-7-:	219	if (tlul_req_i)
-8-:	233	if (((({tlul_addr_q, 2'b0} >= 11'b01101100000) && ({1'b0, tlul_addr_q, 2'b0} < PartEnd)) && prim_mubi_pkg::mubi8_test_false_strict(access_o.read_lock)))
-9-:	238	if (otp_gnt_i)
-10-:	254	if (otp_rvalid_i)
-11-:	258	if ((((!1'b1) && (otp_err_e'(otp_err_i) == MacroEccUncorrError)) || (otp_err_e'(otp_err_i) inside {NoError, MacroEccCorrError})))
-12-:	266	if ((otp_err_e'(otp_err_i) != NoError))
-13-:	282	if ((error_q == NoError))
-14-:	287	if (pending_tlul_error_q)
-15-:	290	if (tlul_req_i)

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	-9-	-10-	-11-	-12-	-13-	-14-	-15-	Status	Tests
ResetSt	1	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
ResetSt	0	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
InitSt	-	1	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
InitSt	-	0	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
InitWaitSt	-	-	1	1	1	-	-	-	-	-	-	-	-	-	Covered	T58,T59,T60
InitWaitSt	-	-	1	1	0	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
InitWaitSt	-	-	1	0	-	-	-	-	-	-	-	-	-	-	Covered	T37,T134,T135
InitWaitSt	-	-	0	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
IdleSt	-	-	-	-	-	1	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
IdleSt	-	-	-	-	-	0	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
ReadSt	-	-	-	-	-	-	1	1	-	-	-	-	-	-	Covered	T1,T2,T3
ReadSt	-	-	-	-	-	-	1	0	-	-	-	-	-	-	Covered	T93,T136,T137
ReadSt	-	-	-	-	-	-	0	-	-	-	-	-	-	-	Covered	T1,T2,T3
ReadWaitSt	-	-	-	-	-	-	-	-	1	1	1	-	-	-	Covered	T29,T118,T130
ReadWaitSt	-	-	-	-	-	-	-	-	1	1	0	-	-	-	Covered	T1,T2,T3
ReadWaitSt	-	-	-	-	-	-	-	-	1	0	-	-	-	-	Covered	T129,T138,T139
ReadWaitSt	-	-	-	-	-	-	-	-	0	-	-	-	-	-	Covered	T1,T2,T3
ErrorSt	-	-	-	-	-	-	-	-	-	-	-	1	-	-	Covered	T20,T21,T22
ErrorSt	-	-	-	-	-	-	-	-	-	-	-	0	-	-	Covered	T7,T9,T37
ErrorSt	-	-	-	-	-	-	-	-	-	-	-	-	1	-	Covered	T7,T9,T107
ErrorSt	-	-	-	-	-	-	-	-	-	-	-	-	0	1	Covered	T7,T9,T107
ErrorSt	-	-	-	-	-	-	-	-	-	-	-	-	0	0	Covered	T7,T9,T37
default	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T20,T21,T22

	LineNo.	Expression
-1-:	308	if (ecc_err)
-2-:	310	if ((state_q != ErrorSt))

Branches:

-1-	-2-	Status	Tests
1	1	Covered	T131,T125,T140
1	0	Covered	T131,T125,T140
0	-	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	315	if (lc_ctrl_pkg::lc_tx_test_true_loose(escalate_en_i))
-2-:	318	if ((state_q != ErrorSt))

Branches:

-1-	-2-	Status	Tests
1	1	Covered	T7,T9,T107
1	0	Covered	T7,T9,T37
0	-	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	437	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	440	if ((!rst_ni))
-2-:	447	if (tlul_gnt_o)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
0	0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.gen_partitions[2].gen_unbuffered.u_part_unbuf

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	26	26	100.00	26	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	26	26	100.00	26	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AccessKnown_A	2147483647	2147483647	0	0
DigestKnown_A	2147483647	2147483647	0	0
DigestOffsetMustBeRepresentable_A	1157	1157	0	0
EccErrorState_A	2147483647	38356	0	0
ErrorKnown_A	2147483647	2147483647	0	0
FsmStateKnown_A	2147483647	2147483647	0	0
InitDoneKnown_A	2147483647	2147483647	0	0
InitReadLocksPartition_A	2147483647	386623315	0	0
InitWriteLocksPartition_A	2147483647	386623315	0	0
OffsetMustBeBlockAligned_A	1157	1157	0	0
OtpAddrKnown_A	2147483647	2147483647	0	0
OtpCmdKnown_A	2147483647	2147483647	0	0
OtpErrorState_A	2147483647	55	0	0
OtpReqKnown_A	2147483647	2147483647	0	0
OtpSizeKnown_A	2147483647	2147483647	0	0
OtpWdataKnown_A	2147483647	2147483647	0	0
ReadLockPropagation_A	2147483647	1320049958	0	0
SizeMustBeBlockAligned_A	1157	1157	0	0
TlulGntKnown_A	2147483647	2147483647	0	0
TlulRdataKnown_A	2147483647	2147483647	0	0
TlulReadOnReadLock_A	2147483647	11137	0	0
TlulRerrorKnown_A	2147483647	2147483647	0	0
TlulRvalidKnown_A	2147483647	2147483647	0	0
WriteLockPropagation_A	2147483647	1349262	0	0
gen_digest_write_lock.DigestWriteLocksPartition_A	2147483647	19804399	0	0
u_state_regs_A	2147483647	2147483647	0	0

AccessKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	73436	72051	0	0
T2	38018	37309	0	0
T3	110228	108967	0	0
T5	7499	6741	0	0
T6	50788	49798	0	0
T7	111091	111090	0	0
T8	8171	8083	0	0
T9	19415	19147	0	0
T10	10832	10630	0	0
T11	12755	12519	0	0

DigestKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	73436	72051	0	0
T2	38018	37309	0	0
T3	110228	108967	0	0
T5	7499	6741	0	0
T6	50788	49798	0	0
T7	111091	111090	0	0
T8	8171	8083	0	0
T9	19415	19147	0	0
T10	10832	10630	0	0
T11	12755	12519	0	0

DigestOffsetMustBeRepresentable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1157	1157	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0

EccErrorState_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	38356	0	0
T12	359213	0	0	0
T59	12777	0	0	0
T95	551829	0	0	0
T96	52693	0	0	0
T97	58743	0	0	0
T104	41425	0	0	0
T125	0	3468	0	0
T131	15303	3498	0	0
T133	0	2360	0	0
T140	0	2220	0	0
T141	0	3283	0	0
T142	0	2533	0	0
T144	0	3319	0	0
T145	0	3115	0	0
T146	0	2216	0	0
T149	0	2714	0	0
T152	14219	0	0	0
T179	18956	0	0	0
T180	30990	0	0	0

ErrorKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	73436	72051	0	0
T2	38018	37309	0	0
T3	110228	108967	0	0
T5	7499	6741	0	0
T6	50788	49798	0	0
T7	111091	111090	0	0
T8	8171	8083	0	0
T9	19415	19147	0	0
T10	10832	10630	0	0
T11	12755	12519	0	0

FsmStateKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	73436	72051	0	0
T2	38018	37309	0	0
T3	110228	108967	0	0
T5	7499	6741	0	0
T6	50788	49798	0	0
T7	111091	111090	0	0
T8	8171	8083	0	0
T9	19415	19147	0	0
T10	10832	10630	0	0
T11	12755	12519	0	0

InitDoneKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	73436	72051	0	0
T2	38018	37309	0	0
T3	110228	108967	0	0
T5	7499	6741	0	0
T6	50788	49798	0	0
T7	111091	111090	0	0
T8	8171	8083	0	0
T9	19415	19147	0	0
T10	10832	10630	0	0
T11	12755	12519	0	0

InitReadLocksPartition_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	386623315	0	0
T1	73436	1885	0	0
T2	38018	742	0	0
T3	110228	1272	0	0
T5	7499	593	0	0
T6	50788	1562	0	0
T7	111091	999635	0	0
T8	8171	89	0	0
T9	19415	10091	0	0
T10	10832	209	0	0
T11	12755	279	0	0

InitWriteLocksPartition_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	386623315	0	0
T1	73436	1885	0	0
T2	38018	742	0	0
T3	110228	1272	0	0
T5	7499	593	0	0
T6	50788	1562	0	0
T7	111091	999635	0	0
T8	8171	89	0	0
T9	19415	10091	0	0
T10	10832	209	0	0
T11	12755	279	0	0

OffsetMustBeBlockAligned_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1157	1157	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0

OtpAddrKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	73436	72051	0	0
T2	38018	37309	0	0
T3	110228	108967	0	0
T5	7499	6741	0	0
T6	50788	49798	0	0
T7	111091	111090	0	0
T8	8171	8083	0	0
T9	19415	19147	0	0
T10	10832	10630	0	0
T11	12755	12519	0	0

OtpCmdKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	73436	72051	0	0
T2	38018	37309	0	0
T3	110228	108967	0	0
T5	7499	6741	0	0
T6	50788	49798	0	0
T7	111091	111090	0	0
T8	8171	8083	0	0
T9	19415	19147	0	0
T10	10832	10630	0	0
T11	12755	12519	0	0

OtpErrorState_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	55	0	0
T23	13191	0	0	0
T26	17138	0	0	0
T37	12955	1	0	0
T48	11194	0	0	0
T58	13271	0	0	0
T93	43989	0	0	0
T94	64629	0	0	0
T107	14899	0	0	0
T108	10909	0	0	0
T124	0	1	0	0
T129	0	1	0	0
T134	10859	1	0	0
T135	0	1	0	0
T167	0	1	0	0
T168	0	1	0	0
T169	0	1	0	0
T170	0	1	0	0
T171	0	1	0	0

OtpReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	73436	72051	0	0
T2	38018	37309	0	0
T3	110228	108967	0	0
T5	7499	6741	0	0
T6	50788	49798	0	0
T7	111091	111090	0	0
T8	8171	8083	0	0
T9	19415	19147	0	0
T10	10832	10630	0	0
T11	12755	12519	0	0

OtpSizeKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	73436	72051	0	0
T2	38018	37309	0	0
T3	110228	108967	0	0
T5	7499	6741	0	0
T6	50788	49798	0	0
T7	111091	111090	0	0
T8	8171	8083	0	0
T9	19415	19147	0	0
T10	10832	10630	0	0
T11	12755	12519	0	0

OtpWdataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	73436	72051	0	0
T2	38018	37309	0	0
T3	110228	108967	0	0
T5	7499	6741	0	0
T6	50788	49798	0	0
T7	111091	111090	0	0
T8	8171	8083	0	0
T9	19415	19147	0	0
T10	10832	10630	0	0
T11	12755	12519	0	0

ReadLockPropagation_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1320049958	0	0
T1	73436	8272	0	0
T2	38018	1717	0	0
T3	110228	29716	0	0
T5	7499	0	0	0
T6	50788	3582	0	0
T7	111091	110702	0	0
T8	8171	0	0	0
T9	19415	11815	0	0
T10	10832	0	0	0
T11	12755	0	0	0
T93	0	4482	0	0
T94	0	172	0	0
T106	0	1327	0	0
T107	0	1249	0	0

SizeMustBeBlockAligned_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1157	1157	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0

TlulGntKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	73436	72051	0	0
T2	38018	37309	0	0
T3	110228	108967	0	0
T5	7499	6741	0	0
T6	50788	49798	0	0
T7	111091	111090	0	0
T8	8171	8083	0	0
T9	19415	19147	0	0
T10	10832	10630	0	0
T11	12755	12519	0	0

TlulRdataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	73436	72051	0	0
T2	38018	37309	0	0
T3	110228	108967	0	0
T5	7499	6741	0	0
T6	50788	49798	0	0
T7	111091	111090	0	0
T8	8171	8083	0	0
T9	19415	19147	0	0
T10	10832	10630	0	0
T11	12755	12519	0	0

TlulReadOnReadLock_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	11137	0	0
T1	73436	6	0	0
T2	38018	1	0	0
T3	110228	18	0	0
T5	7499	0	0	0
T6	50788	5	0	0
T7	111091	17	0	0
T8	8171	0	0	0
T9	19415	28	0	0
T10	10832	0	0	0
T11	12755	0	0	0
T29	0	14	0	0
T93	0	9	0	0
T107	0	16	0	0
T173	0	2	0	0

TlulRerrorKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	73436	72051	0	0
T2	38018	37309	0	0
T3	110228	108967	0	0
T5	7499	6741	0	0
T6	50788	49798	0	0
T7	111091	111090	0	0
T8	8171	8083	0	0
T9	19415	19147	0	0
T10	10832	10630	0	0
T11	12755	12519	0	0

TlulRvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	73436	72051	0	0
T2	38018	37309	0	0
T3	110228	108967	0	0
T5	7499	6741	0	0
T6	50788	49798	0	0
T7	111091	111090	0	0
T8	8171	8083	0	0
T9	19415	19147	0	0
T10	10832	10630	0	0
T11	12755	12519	0	0

WriteLockPropagation_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1349262	0	0
T1	73436	5982	0	0
T2	38018	0	0	0
T3	110228	8668	0	0
T5	7499	0	0	0
T6	50788	2082	0	0
T7	111091	0	0	0
T8	8171	0	0	0
T9	19415	0	0	0
T10	10832	0	0	0
T11	12755	0	0	0
T93	0	1407	0	0
T94	0	1004	0	0
T95	0	33268	0	0
T96	0	3048	0	0
T98	0	10220	0	0
T99	0	28042	0	0
T104	0	1050	0	0

gen_digest_write_lock.DigestWriteLocksPartition_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	19804399	0	0
T1	73436	61249	0	0
T2	38018	5006	0	0
T3	110228	91491	0	0
T5	7499	0	0	0
T6	50788	33285	0	0
T7	111091	0	0	0
T8	8171	0	0	0
T9	19415	0	0	0
T10	10832	0	0	0
T11	12755	0	0	0
T37	0	2670	0	0
T93	0	33638	0	0
T94	0	37506	0	0
T107	0	2832	0	0
T173	0	65748	0	0
T174	0	2573	0	0

u_state_regs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	73436	72051	0	0
T2	38018	37309	0	0
T3	110228	108967	0	0
T5	7499	6741	0	0
T6	50788	49798	0	0
T7	111091	111090	0	0
T8	8171	8083	0	0
T9	19415	19147	0	0
T10	10832	10630	0	0
T11	12755	12519	0	0