Unified Coverage Report :: Module :: otp_ctrl_core_csr_assert_fpv

Module : otp_ctrl_core_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
84.62						84.62

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_otp_ctrl_csr_assert_0/otp_ctrl_core_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.otp_ctrl_core_csr_assert	84.62						84.62

---

Module Instance : tb.dut.otp_ctrl_core_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
84.62						84.62

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
84.62						84.62

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
90.86	95.10	88.12	78.08		96.00	97.01	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : otp_ctrl_core_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	13	13	100.00	11	84.62
Cover properties	0	0		0
Cover sequences	0	0		0
Total	13	13	100.00	11	84.62

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	28618019	202065	0	0
check_regwen_rd_A	28618019	1707	0	0
check_timeout_rd_A	28618019	256	0	0
check_trigger_regwen_rd_A	28618019	1636	0	0
consistency_check_period_rd_A	28618019	1591	0	0
creator_sw_cfg_read_lock_rd_A	28618019	420	0	0
direct_access_address_rd_A	28618019	17	0	0
direct_access_wdata_0_rd_A	28618019	0	0	0
direct_access_wdata_1_rd_A	28618019	0	0	0
integrity_check_period_rd_A	28618019	1660	0	0
intr_enable_rd_A	28618019	2142	0	0
owner_sw_cfg_read_lock_rd_A	28618019	277	0	0
vendor_test_read_lock_rd_A	28618019	280	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	28618019	202065	0	0
T10	126774	194658	0	0
T72	23592	0	0	0
T82	10245	0	0	0
T89	0	359	0	0
T90	0	70	0	0
T91	0	5	0	0
T92	0	384	0	0
T93	0	3	0	0
T94	0	40	0	0
T95	0	2	0	0
T96	0	8	0	0
T97	0	122	0	0
T98	10821	0	0	0
T99	3395	0	0	0
T100	12490	0	0	0
T101	70651	0	0	0
T102	14870	0	0	0
T103	20261	0	0	0
T104	16351	0	0	0

check_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	28618019	1707	0	0
T95	59744	41	0	0
T96	125055	0	0	0
T97	9851	0	0	0
T105	0	24	0	0
T106	0	490	0	0
T107	0	43	0	0
T108	0	77	0	0
T109	0	56	0	0
T110	0	279	0	0
T111	0	8	0	0
T112	0	5	0	0
T113	0	16	0	0
T114	3967	0	0	0
T115	3598	0	0	0
T116	4141	0	0	0
T117	3997	0	0	0
T118	8947	0	0	0
T119	10146	0	0	0
T120	3469	0	0	0

check_timeout_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	28618019	256	0	0
T105	11593	63	0	0
T107	9025	15	0	0
T108	0	33	0	0
T113	0	32	0	0
T121	0	58	0	0
T122	0	3	0	0
T123	0	6	0	0
T124	0	40	0	0
T125	0	6	0	0
T126	5042	0	0	0
T127	58914	0	0	0
T128	6386	0	0	0
T129	6907	0	0	0
T130	3216	0	0	0
T131	5551	0	0	0
T132	3901	0	0	0
T133	3628	0	0	0

check_trigger_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	28618019	1636	0	0
T95	59744	39	0	0
T96	125055	0	0	0
T97	9851	0	0	0
T105	0	43	0	0
T106	0	442	0	0
T107	0	51	0	0
T108	0	41	0	0
T109	0	18	0	0
T110	0	217	0	0
T111	0	10	0	0
T112	0	2	0	0
T114	3967	0	0	0
T115	3598	0	0	0
T116	4141	0	0	0
T117	3997	0	0	0
T118	8947	0	0	0
T119	10146	0	0	0
T120	3469	0	0	0
T134	0	3	0	0

consistency_check_period_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	28618019	1591	0	0
T95	59744	46	0	0
T96	125055	0	0	0
T97	9851	0	0	0
T105	0	27	0	0
T106	0	440	0	0
T107	0	24	0	0
T108	0	10	0	0
T109	0	37	0	0
T110	0	290	0	0
T111	0	1	0	0
T112	0	8	0	0
T113	0	46	0	0
T114	3967	0	0	0
T115	3598	0	0	0
T116	4141	0	0	0
T117	3997	0	0	0
T118	8947	0	0	0
T119	10146	0	0	0
T120	3469	0	0	0

creator_sw_cfg_read_lock_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	28618019	420	0	0
T105	11593	68	0	0
T107	9025	75	0	0
T108	0	104	0	0
T113	0	57	0	0
T121	0	64	0	0
T122	0	8	0	0
T123	0	17	0	0
T124	0	20	0	0
T125	0	7	0	0
T126	5042	0	0	0
T127	58914	0	0	0
T128	6386	0	0	0
T129	6907	0	0	0
T130	3216	0	0	0
T131	5551	0	0	0
T132	3901	0	0	0
T133	3628	0	0	0

direct_access_address_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	28618019	17	0	0
T122	7473	4	0	0
T125	9985	13	0	0
T135	3431	0	0	0
T136	3854	0	0	0
T137	3244	0	0	0
T138	3212	0	0	0
T139	11245	0	0	0
T140	64576	0	0	0
T141	58506	0	0	0
T142	11954	0	0	0

direct_access_wdata_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	28618019	0	0	0

direct_access_wdata_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	28618019	0	0	0

integrity_check_period_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	28618019	1660	0	0
T95	59744	40	0	0
T96	125055	0	0	0
T97	9851	0	0	0
T105	0	43	0	0
T106	0	477	0	0
T107	0	18	0	0
T108	0	27	0	0
T109	0	37	0	0
T110	0	257	0	0
T111	0	13	0	0
T112	0	6	0	0
T113	0	38	0	0
T114	3967	0	0	0
T115	3598	0	0	0
T116	4141	0	0	0
T117	3997	0	0	0
T118	8947	0	0	0
T119	10146	0	0	0
T120	3469	0	0	0

intr_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	28618019	2142	0	0
T95	59744	62	0	0
T96	125055	0	0	0
T97	9851	0	0	0
T105	0	73	0	0
T106	0	444	0	0
T107	0	9	0	0
T108	0	34	0	0
T109	0	57	0	0
T114	3967	4	0	0
T115	3598	0	0	0
T116	4141	0	0	0
T117	3997	17	0	0
T118	8947	0	0	0
T119	10146	0	0	0
T120	3469	0	0	0
T132	0	16	0	0
T143	0	24	0	0

owner_sw_cfg_read_lock_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	28618019	277	0	0
T105	11593	51	0	0
T107	9025	46	0	0
T108	0	44	0	0
T113	0	30	0	0
T121	0	16	0	0
T122	0	6	0	0
T123	0	25	0	0
T124	0	56	0	0
T125	0	3	0	0
T126	5042	0	0	0
T127	58914	0	0	0
T128	6386	0	0	0
T129	6907	0	0	0
T130	3216	0	0	0
T131	5551	0	0	0
T132	3901	0	0	0
T133	3628	0	0	0

vendor_test_read_lock_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	28618019	280	0	0
T105	11593	46	0	0
T107	9025	36	0	0
T108	0	55	0	0
T113	0	51	0	0
T121	0	45	0	0
T122	0	5	0	0
T123	0	3	0	0
T124	0	34	0	0
T125	0	5	0	0
T126	5042	0	0	0
T127	58914	0	0	0
T128	6386	0	0	0
T129	6907	0	0	0
T130	3216	0	0	0
T131	5551	0	0	0
T132	3901	0	0	0
T133	3628	0	0	0